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GET /api/patches/624199/?format=api
{ "id": 624199, "url": "http://patchwork.ozlabs.org/api/patches/624199/?format=api", "web_url": "http://patchwork.ozlabs.org/project/openwrt/patch/1463682077-19339-28-git-send-email-sven.eckelmann@open-mesh.com/", "project": { "id": 45, "url": "http://patchwork.ozlabs.org/api/projects/45/?format=api", "name": "OpenWrt development", "link_name": "openwrt", "list_id": "openwrt-devel.lists.openwrt.org", "list_email": "openwrt-devel@lists.openwrt.org", "web_url": "http://openwrt.org/", "scm_url": "git://git.openwrt.org/openwrt.git", "webscm_url": "https://dev.openwrt.org/browser", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1463682077-19339-28-git-send-email-sven.eckelmann@open-mesh.com>", "list_archive_url": null, "date": "2016-05-19T18:21:11", "name": "[OpenWrt-Devel,CC,28/34] ar71xx: add kernel support for the OpenMesh OM5P-ACv2 board", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "9ae538169c45f0b23dcbe287d2287b557eafef43", "submitter": { "id": 68437, "url": "http://patchwork.ozlabs.org/api/people/68437/?format=api", "name": "Sven Eckelmann", "email": "sven.eckelmann@open-mesh.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/openwrt/patch/1463682077-19339-28-git-send-email-sven.eckelmann@open-mesh.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/624199/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/624199/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<openwrt-devel-bounces@lists.openwrt.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from arrakis.dune.hu (caladan.dune.hu [78.24.191.180])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3r9fl823fwz9sBX\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 20 May 2016 04:30:44 +1000 (AEST)", "from arrakis.dune.hu (localhost [127.0.0.1])\n\tby arrakis.dune.hu (Postfix) with ESMTP id 9BF99B91F71;\n\tThu, 19 May 2016 20:23:28 +0200 (CEST)", "from arrakis.dune.hu (localhost [127.0.0.1])\n\tby arrakis.dune.hu (Postfix) with ESMTP;\n\tThu, 19 May 2016 20:23:28 +0200 (CEST)", "from arrakis.dune.hu (localhost [127.0.0.1])\n\tby arrakis.dune.hu (Postfix) with ESMTP id AF464B92008\n\tfor <openwrt-devel@lists.openwrt.org>;\n\tThu, 19 May 2016 20:22:16 +0200 (CEST)", "from mail-wm0-f48.google.com (mail-wm0-f48.google.com\n\t[74.125.82.48]) by arrakis.dune.hu (Postfix) with ESMTPS\n\tfor <openwrt-devel@lists.openwrt.org>;\n\tThu, 19 May 2016 20:22:16 +0200 (CEST)", "by mail-wm0-f48.google.com with SMTP id a17so138692376wme.0\n\tfor <openwrt-devel@lists.openwrt.org>;\n\tThu, 19 May 2016 11:22:16 -0700 (PDT)", "from sven-desktop.home.narfation.org\n\t(p579E6DC9.dip0.t-ipconnect.de. [87.158.109.201])\n\tby smtp.gmail.com with ESMTPSA id\n\tpm4sm15633848wjb.35.2016.05.19.11.22.15\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tThu, 19 May 2016 11:22:15 -0700 (PDT)" ], "Authentication-Results": "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=open-mesh-com.20150623.gappssmtp.com\n\theader.i=@open-mesh-com.20150623.gappssmtp.com\n\theader.b=0vebukrJ; dkim-atps=neutral", "X-Spam-Checker-Version": "SpamAssassin 3.4.1 (2015-04-28) on arrakis.dune.hu", "X-Spam-Level": "", "X-Spam-Status": "No, score=-1.5 required=5.0 tests=BAYES_00,T_DKIM_INVALID\n\tautolearn=unavailable autolearn_force=no version=3.4.1", "X-policyd-weight": "using cached result; rate:hard: -7", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=open-mesh-com.20150623.gappssmtp.com; s=20150623;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=OwBgZVHTFrYb36jxcEXbOarwDGbmQqyMDsKmw4WaThg=;\n\tb=0vebukrJgoPgqy94YZcDj1ejevigmEV+1Wc5/sIPRzQAEO0Oj2grFqHXEgrhsXdwpy\n\tL/QMI2KJg6MiomQ+TMMO8HOy6isdd2lrvNBmPvVteT4tZwdyeqyDvO8o6B1HoFGH32C3\n\t1BLSS/GZg8GXn3KOH+zdbxIf6TAe7tDJjfIzHm9GOZR7X0pu82BPcdI5Lt3Es+8KtetX\n\t6n4+jevc1sj7MzIl4pLQaRwsO++pvfbGErnXbPqRHv8rYaxbHz7Xha0Ly5NShqkxeJmz\n\tWRPpY4S+IMMho68ART+BOZfa7jDFu+JiOTWI05ape+WR+xGlsgVJzu9u8U10nVaqh5Yo\n\tks4w==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20130820;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=OwBgZVHTFrYb36jxcEXbOarwDGbmQqyMDsKmw4WaThg=;\n\tb=SBlytIjGlr3XROIACbxLtNu2UKa8SvOTzGqMB280JbAp4esj3A7m/dTpfubDU5X4/q\n\tWSQ7S9tHrItk6mIOmEKZ/oLJlHRaEioJbPYAryhTJStVS+TsYRs6dRh8fJTNK73+64kx\n\tpfp9dNA4KmySaJmvMRTwRXRK2AxtgJFRp3gVMsafSMhgwB3fe8ZAFV/apSy5+5kU0u8N\n\t0Rgdjh5MrGallCYQ2ltfWlw7sOmoBBNo2PSgfjFIEhGz/PN5laMVq79R5mpltgtmUSfc\n\ts0EiSJYLvXsR8gDXQYo2B2r7SK8MVcFbMfa5dZnnZwRKQfbOwV0YvPJOjcrJ16rXiymL\n\tZ+vw==", "X-Gm-Message-State": "AOPr4FXwaEpDohXbMot/1nJ6D8a9bPz/TDg3lu4ph3ZKBlYT81BjsxtT3HbVVRzB1Qsf/k6a", "X-Received": "by 10.194.242.167 with SMTP id\n\twr7mr14954628wjc.145.1463682136286; \n\tThu, 19 May 2016 11:22:16 -0700 (PDT)", "From": "Sven Eckelmann <sven.eckelmann@open-mesh.com>", "To": "openwrt-devel@lists.openwrt.org", "Date": "Thu, 19 May 2016 20:21:11 +0200", "Message-Id": "<1463682077-19339-28-git-send-email-sven.eckelmann@open-mesh.com>", "X-Mailer": "git-send-email 2.8.1", "In-Reply-To": "<1463682077-19339-1-git-send-email-sven.eckelmann@open-mesh.com>", "References": "<1463682077-19339-1-git-send-email-sven.eckelmann@open-mesh.com>", "Subject": "[OpenWrt-Devel] [PATCH CC 28/34] ar71xx: add kernel support for the\n\tOpenMesh OM5P-ACv2 board", "X-BeenThere": "openwrt-devel@lists.openwrt.org", "X-Mailman-Version": "2.1.20", "Precedence": "list", "List-Id": "OpenWrt Development List <openwrt-devel.lists.openwrt.org>", "List-Unsubscribe": "<https://lists.openwrt.org/cgi-bin/mailman/options/openwrt-devel>,\n\t<mailto:openwrt-devel-request@lists.openwrt.org?subject=unsubscribe>", "List-Archive": "<http://lists.openwrt.org/pipermail/openwrt-devel/>", "List-Post": "<mailto:openwrt-devel@lists.openwrt.org>", "List-Help": "<mailto:openwrt-devel-request@lists.openwrt.org?subject=help>", "List-Subscribe": "<https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel>,\n\t<mailto:openwrt-devel-request@lists.openwrt.org?subject=subscribe>", "Cc": "Sven Eckelmann <sven.eckelmann@open-mesh.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "openwrt-devel-bounces@lists.openwrt.org", "Sender": "\"openwrt-devel\" <openwrt-devel-bounces@lists.openwrt.org>" }, "content": "Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>\n\nBackport of r49149\n---\n target/linux/ar71xx/config-3.18 | 1 +\n .../ar71xx/files/arch/mips/ath79/mach-om5pacv2.c | 216 +++++++++++++++++++++\n .../816-MIPS-ath79-add-om5pacv-support.patch | 39 ++++\n 3 files changed, 256 insertions(+)\n create mode 100644 target/linux/ar71xx/files/arch/mips/ath79/mach-om5pacv2.c\n create mode 100644 target/linux/ar71xx/patches-3.18/816-MIPS-ath79-add-om5pacv-support.patch", "diff": "diff --git a/target/linux/ar71xx/config-3.18 b/target/linux/ar71xx/config-3.18\nindex 9a66711..e4bed08 100644\n--- a/target/linux/ar71xx/config-3.18\n+++ b/target/linux/ar71xx/config-3.18\n@@ -92,6 +92,7 @@ CONFIG_ATH79_MACH_NBG6716=y\n CONFIG_ATH79_MACH_OM2P=y\n CONFIG_ATH79_MACH_OM5P=y\n CONFIG_ATH79_MACH_OM5P_AC=y\n+CONFIG_ATH79_MACH_OM5P_ACv2=y\n CONFIG_ATH79_MACH_ONION_OMEGA=y\n CONFIG_ATH79_MACH_PB42=y\n CONFIG_ATH79_MACH_PB44=y\ndiff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-om5pacv2.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-om5pacv2.c\nnew file mode 100644\nindex 0000000..587ca32\n--- /dev/null\n+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-om5pacv2.c\n@@ -0,0 +1,216 @@\n+/*\n+ * OpenMesh OM5P-ACv2 support\n+ *\n+ * Copyright (C) 2013 Marek Lindner <marek@open-mesh.com>\n+ * Copyright (C) 2014-2016 Sven Eckelmann <sven@open-mesh.com>\n+ * Copyright (C) 2015 Open-Mesh - Jim Collar <jim.collar@eqware.net>\n+ *\n+ * This program is free software; you can redistribute it and/or modify it\n+ * under the terms of the GNU General Public License version 2 as published\n+ * by the Free Software Foundation.\n+ */\n+\n+#include <linux/gpio.h>\n+#include <linux/mdio-gpio.h>\n+#include <linux/mtd/mtd.h>\n+#include <linux/mtd/partitions.h>\n+#include <linux/platform_device.h>\n+#include <linux/i2c.h>\n+#include <linux/i2c-algo-bit.h>\n+#include <linux/i2c-gpio.h>\n+#include <linux/platform_data/phy-at803x.h>\n+\n+#include <asm/mach-ath79/ar71xx_regs.h>\n+#include <asm/mach-ath79/ath79.h>\n+\n+#include \"common.h\"\n+#include \"dev-ap9x-pci.h\"\n+#include \"dev-eth.h\"\n+#include \"dev-gpio-buttons.h\"\n+#include \"dev-leds-gpio.h\"\n+#include \"dev-m25p80.h\"\n+#include \"dev-wmac.h\"\n+#include \"machtypes.h\"\n+#include \"pci.h\"\n+\n+#define OM5PACV2_GPIO_LED_POWER\t14\n+#define OM5PACV2_GPIO_LED_GREEN\t13\n+#define OM5PACV2_GPIO_LED_RED\t23\n+#define OM5PACV2_GPIO_LED_YELLOW\t15\n+#define OM5PACV2_GPIO_BTN_RESET\t1\n+#define OM5PACV2_GPIO_I2C_SCL\t18\n+#define OM5PACV2_GPIO_I2C_SDA\t19\n+#define OM5PACV2_GPIO_PA_DCDC\t2\n+#define OM5PACV2_GPIO_PA_HIGH\t16\n+\n+#define OM5PACV2_KEYS_POLL_INTERVAL\t20\t/* msecs */\n+#define OM5PACV2_KEYS_DEBOUNCE_INTERVAL\t(3 * OM5PACV2_KEYS_POLL_INTERVAL)\n+\n+#define OM5PACV2_WMAC_CALDATA_OFFSET\t0x1000\n+\n+static struct gpio_led om5pacv2_leds_gpio[] __initdata = {\n+\t{\n+\t\t.name\t\t= \"om5pac:blue:power\",\n+\t\t.gpio\t\t= OM5PACV2_GPIO_LED_POWER,\n+\t\t.active_low\t= 1,\n+\t}, {\n+\t\t.name\t\t= \"om5pac:red:wifi\",\n+\t\t.gpio\t\t= OM5PACV2_GPIO_LED_RED,\n+\t\t.active_low\t= 1,\n+\t}, {\n+\t\t.name\t\t= \"om5pac:yellow:wifi\",\n+\t\t.gpio\t\t= OM5PACV2_GPIO_LED_YELLOW,\n+\t\t.active_low\t= 1,\n+\t}, {\n+\t\t.name\t\t= \"om5pac:green:wifi\",\n+\t\t.gpio\t\t= OM5PACV2_GPIO_LED_GREEN,\n+\t\t.active_low\t= 1,\n+\t}\n+};\n+\n+static struct gpio_keys_button om5pacv2_gpio_keys[] __initdata = {\n+\t{\n+\t\t.desc\t\t= \"reset\",\n+\t\t.type\t\t= EV_KEY,\n+\t\t.code\t\t= KEY_RESTART,\n+\t\t.debounce_interval = OM5PACV2_KEYS_DEBOUNCE_INTERVAL,\n+\t\t.gpio\t\t= OM5PACV2_GPIO_BTN_RESET,\n+\t\t.active_low\t= 1,\n+\t}\n+};\n+\n+static struct i2c_gpio_platform_data om5pacv2_i2c_device_platdata = {\n+\t.sda_pin\t\t= OM5PACV2_GPIO_I2C_SDA,\n+\t.scl_pin\t\t= OM5PACV2_GPIO_I2C_SCL,\n+\t.udelay\t\t\t= 10,\n+\t.sda_is_open_drain\t= 1,\n+\t.scl_is_open_drain\t= 1,\n+};\n+\n+static struct platform_device om5pacv2_i2c_device = {\n+\t.name\t\t= \"i2c-gpio\",\n+\t.id\t\t= 0,\n+\t.dev\t\t= {\n+\t\t.platform_data\t= &om5pacv2_i2c_device_platdata,\n+\t},\n+};\n+\n+static struct i2c_board_info om5pacv2_i2c_devs[] __initdata = {\n+\t{\n+\t\tI2C_BOARD_INFO(\"tmp423\", 0x4e),\n+\t},\n+};\n+\n+static struct flash_platform_data om5pacv2_flash_data = {\n+\t.type = \"mx25l12805d\",\n+};\n+\n+static struct at803x_platform_data om5pacv2_an_at803x_data = {\n+\t.disable_smarteee = 1,\n+\t.enable_rgmii_rx_delay = 1,\n+\t.enable_rgmii_tx_delay = 1,\n+};\n+\n+static struct at803x_platform_data om5pacv2_an_at8031_data = {\n+\t.disable_smarteee = 1,\n+\t.enable_rgmii_rx_delay = 1,\n+\t.enable_rgmii_tx_delay = 1,\n+};\n+\n+static struct mdio_board_info om5pacv2_an_mdio0_info[] = {\n+\t{\n+\t\t.bus_id = \"ag71xx-mdio.0\",\n+\t\t.phy_addr = 4,\n+\t\t.platform_data = &om5pacv2_an_at803x_data,\n+\t},\n+\t{\n+\t\t.bus_id = \"ag71xx-mdio.1\",\n+\t\t.phy_addr = 1,\n+\t\t.platform_data = &om5pacv2_an_at8031_data,\n+\t},\n+};\n+\n+static void __init om5p_acv2_setup_qca955x_eth_cfg(u32 mask,\n+\t\t\t\t\t\t unsigned int rxd,\n+\t\t\t\t\t\t unsigned int rxdv,\n+\t\t\t\t\t\t unsigned int txd,\n+\t\t\t\t\t\t unsigned int txe)\n+{\n+\tvoid __iomem *base;\n+\tu32 t;\n+\n+\tbase = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);\n+\n+\tt = mask;\n+\tt |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;\n+\tt |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;\n+\tt |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;\n+\tt |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;\n+\n+\t__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);\n+\n+\tiounmap(base);\n+}\n+\n+static void __init om5p_acv2_setup(void)\n+{\n+\tu8 *art = (u8 *)KSEG1ADDR(0x1fff0000);\n+\tu8 mac[6];\n+\n+\t/* power amplifier high power, 4.2V at RFFM4203/4503 instead of 3.3 */\n+\tath79_gpio_function_enable(QCA955X_GPIO_FUNC_JTAG_DISABLE);\n+\tath79_gpio_output_select(OM5PACV2_GPIO_PA_DCDC, QCA955X_GPIO_OUT_GPIO);\n+\tath79_gpio_output_select(OM5PACV2_GPIO_PA_HIGH, QCA955X_GPIO_OUT_GPIO);\n+\tgpio_request_one(OM5PACV2_GPIO_PA_DCDC, GPIOF_OUT_INIT_HIGH,\n+\t\t\t \"PA DC/DC\");\n+\tgpio_request_one(OM5PACV2_GPIO_PA_HIGH, GPIOF_OUT_INIT_HIGH, \"PA HIGH\");\n+\n+\t/* temperature sensor */\n+\tplatform_device_register(&om5pacv2_i2c_device);\n+\ti2c_register_board_info(0, om5pacv2_i2c_devs,\n+\t\t\t\tARRAY_SIZE(om5pacv2_i2c_devs));\n+\n+\tath79_register_m25p80(&om5pacv2_flash_data);\n+\tath79_register_leds_gpio(-1, ARRAY_SIZE(om5pacv2_leds_gpio),\n+\t\t\t\t om5pacv2_leds_gpio);\n+\tath79_register_gpio_keys_polled(-1, OM5PACV2_KEYS_POLL_INTERVAL,\n+\t\t\t\t\tARRAY_SIZE(om5pacv2_gpio_keys),\n+\t\t\t\t\tom5pacv2_gpio_keys);\n+\n+\tath79_init_mac(mac, art, 0x02);\n+\tath79_register_wmac(art + OM5PACV2_WMAC_CALDATA_OFFSET, mac);\n+\n+\tom5p_acv2_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 2, 2, 0, 0);\n+\tath79_register_mdio(0, 0x0);\n+\tath79_register_mdio(1, 0x0);\n+\n+\tmdiobus_register_board_info(om5pacv2_an_mdio0_info,\n+\t\t\t\t ARRAY_SIZE(om5pacv2_an_mdio0_info));\n+\n+\tath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00);\n+\tath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01);\n+\n+\t/* GMAC0 is connected to the PHY4 */\n+\tath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;\n+\tath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;\n+\tath79_eth0_data.phy_mask = BIT(4);\n+\tath79_eth0_pll_data.pll_1000 = 0x82000101;\n+\tath79_eth0_pll_data.pll_100 = 0x80000101;\n+\tath79_eth0_pll_data.pll_10 = 0x80001313;\n+\tath79_register_eth(0);\n+\n+\t/* GMAC1 is connected to MDIO1 in SGMII mode */\n+\tath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;\n+\tath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev;\n+\tath79_eth1_data.phy_mask = BIT(1);\n+\tath79_eth1_pll_data.pll_1000 = 0x03000101;\n+\tath79_eth1_pll_data.pll_100 = 0x80000101;\n+\tath79_eth1_pll_data.pll_10 = 0x80001313;\n+\tath79_eth1_data.speed = SPEED_1000;\n+\tath79_eth1_data.duplex = DUPLEX_FULL;\n+\tath79_register_eth(1);\n+\n+\tath79_register_pci();\n+}\n+\n+MIPS_MACHINE(ATH79_MACH_OM5P_ACv2, \"OM5P-ACv2\", \"OpenMesh OM5P ACv2\", om5p_acv2_setup);\ndiff --git a/target/linux/ar71xx/patches-3.18/816-MIPS-ath79-add-om5pacv-support.patch b/target/linux/ar71xx/patches-3.18/816-MIPS-ath79-add-om5pacv-support.patch\nnew file mode 100644\nindex 0000000..fbbf171\n--- /dev/null\n+++ b/target/linux/ar71xx/patches-3.18/816-MIPS-ath79-add-om5pacv-support.patch\n@@ -0,0 +1,39 @@\n+--- a/arch/mips/ath79/Kconfig\n++++ b/arch/mips/ath79/Kconfig\n+@@ -808,6 +808,16 @@ config ATH79_MACH_OM5P_AC\n+ \tselect ATH79_DEV_M25P80\n+ \tselect ATH79_DEV_WMAC\n+ \n++config ATH79_MACH_OM5P_ACv2\n++\tbool \"OpenMesh OM5P-ACv2 board support\"\n++\tselect SOC_QCA955X\n++\tselect ATH79_DEV_AP9X_PCI if PCI\n++\tselect ATH79_DEV_ETH\n++\tselect ATH79_DEV_GPIO_BUTTONS\n++\tselect ATH79_DEV_LEDS_GPIO\n++\tselect ATH79_DEV_M25P80\n++\tselect ATH79_DEV_WMAC\n++\n+ config ATH79_MACH_ONION_OMEGA\n+ \tbool \"ONION OMEGA support\"\n+ \tselect SOC_AR933X\n+--- a/arch/mips/ath79/Makefile\n++++ b/arch/mips/ath79/Makefile\n+@@ -101,6 +101,7 @@ obj-$(CONFIG_ATH79_MACH_NBG460N)\t+= mach\n+ obj-$(CONFIG_ATH79_MACH_OM2P)\t\t+= mach-om2p.o\n+ obj-$(CONFIG_ATH79_MACH_OM5P)\t\t+= mach-om5p.o\n+ obj-$(CONFIG_ATH79_MACH_OM5P_AC)\t+= mach-om5pac.o\n++obj-$(CONFIG_ATH79_MACH_OM5P_ACv2)\t+= mach-om5pacv2.o\n+ obj-$(CONFIG_ATH79_MACH_ONION_OMEGA)\t+= mach-onion-omega.o\n+ obj-$(CONFIG_ATH79_MACH_PB42)\t\t+= mach-pb42.o\n+ obj-$(CONFIG_ATH79_MACH_PB44)\t\t+= mach-pb44.o\n+--- a/arch/mips/ath79/machtypes.h\n++++ b/arch/mips/ath79/machtypes.h\n+@@ -96,6 +96,7 @@ enum ath79_mach_type {\n+ \tATH79_MACH_OM2Pv2,\t\t/* OpenMesh OM2Pv2 */\n+ \tATH79_MACH_OM2P,\t\t/* OpenMesh OM2P */\n+ \tATH79_MACH_OM5P_AC,\t\t/* OpenMesh OM5P-AC */\n++\tATH79_MACH_OM5P_ACv2,\t\t/* OpenMesh OM5P-ACv2 */\n+ \tATH79_MACH_OM5P_AN,\t\t/* OpenMesh OM5P-AN */\n+ \tATH79_MACH_OM5P,\t\t/* OpenMesh OM5P */\n+ \tATH79_MACH_ONION_OMEGA,\t\t/* ONION OMEGA */\n", "prefixes": [ "OpenWrt-Devel", "CC", "28/34" ] }