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GET /api/patches/624184/?format=api
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{
    "id": 624184,
    "url": "http://patchwork.ozlabs.org/api/patches/624184/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/openwrt/patch/1463682077-19339-13-git-send-email-sven.eckelmann@open-mesh.com/",
    "project": {
        "id": 45,
        "url": "http://patchwork.ozlabs.org/api/projects/45/?format=api",
        "name": "OpenWrt development",
        "link_name": "openwrt",
        "list_id": "openwrt-devel.lists.openwrt.org",
        "list_email": "openwrt-devel@lists.openwrt.org",
        "web_url": "http://openwrt.org/",
        "scm_url": "git://git.openwrt.org/openwrt.git",
        "webscm_url": "https://dev.openwrt.org/browser",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<1463682077-19339-13-git-send-email-sven.eckelmann@open-mesh.com>",
    "list_archive_url": null,
    "date": "2016-05-19T18:20:56",
    "name": "[OpenWrt-Devel,CC,13/34] ar71xx: Add QCA955X GPIO mux and function definitions",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "0838905e1a7f4416527d434d9d17fa7aa4b53d64",
    "submitter": {
        "id": 68437,
        "url": "http://patchwork.ozlabs.org/api/people/68437/?format=api",
        "name": "Sven Eckelmann",
        "email": "sven.eckelmann@open-mesh.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/openwrt/patch/1463682077-19339-13-git-send-email-sven.eckelmann@open-mesh.com/mbox/",
    "series": [],
    "comments": "http://patchwork.ozlabs.org/api/patches/624184/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/624184/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<openwrt-devel-bounces@lists.openwrt.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
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        "X-Received": "by 10.28.27.17 with SMTP id b17mr15233868wmb.19.1463682114590;\n\tThu, 19 May 2016 11:21:54 -0700 (PDT)",
        "From": "Sven Eckelmann <sven.eckelmann@open-mesh.com>",
        "To": "openwrt-devel@lists.openwrt.org",
        "Date": "Thu, 19 May 2016 20:20:56 +0200",
        "Message-Id": "<1463682077-19339-13-git-send-email-sven.eckelmann@open-mesh.com>",
        "X-Mailer": "git-send-email 2.8.1",
        "In-Reply-To": "<1463682077-19339-1-git-send-email-sven.eckelmann@open-mesh.com>",
        "References": "<1463682077-19339-1-git-send-email-sven.eckelmann@open-mesh.com>",
        "Subject": "[OpenWrt-Devel] [PATCH CC 13/34] ar71xx: Add QCA955X GPIO mux and\n\tfunction definitions",
        "X-BeenThere": "openwrt-devel@lists.openwrt.org",
        "X-Mailman-Version": "2.1.20",
        "Precedence": "list",
        "List-Id": "OpenWrt Development List <openwrt-devel.lists.openwrt.org>",
        "List-Unsubscribe": "<https://lists.openwrt.org/cgi-bin/mailman/options/openwrt-devel>,\n\t<mailto:openwrt-devel-request@lists.openwrt.org?subject=unsubscribe>",
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        "Cc": "Sven Eckelmann <sven.eckelmann@open-mesh.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain; charset=\"utf-8\"",
        "Content-Transfer-Encoding": "base64",
        "Errors-To": "openwrt-devel-bounces@lists.openwrt.org",
        "Sender": "\"openwrt-devel\" <openwrt-devel-bounces@lists.openwrt.org>"
    },
    "content": "Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>\n\nBackport of r49075\n---\n .../601-MIPS-ath79-add-more-register-defines.patch | 79 +++++++++++++++++++++-\n ...79-add-gpio-func-register-for-QCA955x-SoC.patch | 26 -------\n 2 files changed, 77 insertions(+), 28 deletions(-)",
    "diff": "diff --git a/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch\nindex 797977f..0126f6a 100644\n--- a/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch\n+++ b/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch\n@@ -194,7 +194,7 @@\n  #define AR933X_BOOTSTRAP_REF_CLK_40\tBIT(0)\n  \n  #define AR934X_BOOTSTRAP_SW_OPTION8\tBIT(23)\n-@@ -529,6 +626,12 @@\n+@@ -529,8 +626,22 @@\n  #define AR71XX_GPIO_REG_INT_ENABLE\t0x24\n  #define AR71XX_GPIO_REG_FUNC\t\t0x28\n  \n@@ -206,8 +206,18 @@\n +#define AR934X_GPIO_REG_OUT_FUNC5\t0x40\n  #define AR934X_GPIO_REG_FUNC\t\t0x6c\n  \n++#define QCA955X_GPIO_REG_OUT_FUNC0\t0x2c\n++#define QCA955X_GPIO_REG_OUT_FUNC1\t0x30\n++#define QCA955X_GPIO_REG_OUT_FUNC2\t0x34\n++#define QCA955X_GPIO_REG_OUT_FUNC3\t0x38\n++#define QCA955X_GPIO_REG_OUT_FUNC4\t0x3c\n++#define QCA955X_GPIO_REG_OUT_FUNC5\t0x40\n++#define QCA955X_GPIO_REG_FUNC\t\t0x6c\n++\n  #define AR71XX_GPIO_COUNT\t\t16\n-@@ -560,4 +663,170 @@\n+ #define AR7240_GPIO_COUNT\t\t18\n+ #define AR7241_GPIO_COUNT\t\t20\n+@@ -560,4 +671,235 @@\n  #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT\t13\n  #define AR934X_SRIF_DPLL2_OUTDIV_MASK\t0x7\n  \n@@ -288,6 +298,71 @@\n +#define AR934X_GPIO_OUT_EXT_LNA0\t46\n +#define AR934X_GPIO_OUT_EXT_LNA1\t47\n +\n++#define QCA955X_GPIO_FUNC_CLK_OBS7_EN\t\tBIT(9)\n++#define QCA955X_GPIO_FUNC_CLK_OBS6_EN\t\tBIT(8)\n++#define QCA955X_GPIO_FUNC_CLK_OBS5_EN\t\tBIT(7)\n++#define QCA955X_GPIO_FUNC_CLK_OBS4_EN\t\tBIT(6)\n++#define QCA955X_GPIO_FUNC_CLK_OBS3_EN\t\tBIT(5)\n++#define QCA955X_GPIO_FUNC_CLK_OBS2_EN\t\tBIT(4)\n++#define QCA955X_GPIO_FUNC_CLK_OBS1_EN\t\tBIT(3)\n++#define QCA955X_GPIO_FUNC_JTAG_DISABLE\t\tBIT(1)\n++\n++#define QCA955X_GPIO_OUT_GPIO\t\t0\n++#define QCA955X_MII_EXT_MDI\t\t1\n++#define QCA955X_SLIC_DATA_OUT\t\t3\n++#define QCA955X_SLIC_PCM_FS\t\t4\n++#define QCA955X_SLIC_PCM_CLK\t\t5\n++#define QCA955X_SPI_CLK\t\t\t8\n++#define QCA955X_SPI_CS_0\t\t9\n++#define QCA955X_SPI_CS_1\t\t10\n++#define QCA955X_SPI_CS_2\t\t11\n++#define QCA955X_SPI_MISO\t\t12\n++#define QCA955X_I2S_CLK\t\t\t13\n++#define QCA955X_I2S_WS\t\t\t14\n++#define QCA955X_I2S_SD\t\t\t15\n++#define QCA955X_I2S_MCK\t\t\t16\n++#define QCA955X_SPDIF_OUT\t\t17\n++#define QCA955X_UART1_TD\t\t18\n++#define QCA955X_UART1_RTS\t\t19\n++#define QCA955X_UART1_RD\t\t20\n++#define QCA955X_UART1_CTS\t\t21\n++#define QCA955X_UART0_SOUT\t\t22\n++#define QCA955X_SPDIF2_OUT\t\t23\n++#define QCA955X_LED_SGMII_SPEED0\t24\n++#define QCA955X_LED_SGMII_SPEED1\t25\n++#define QCA955X_LED_SGMII_DUPLEX\t26\n++#define QCA955X_LED_SGMII_LINK_UP\t27\n++#define QCA955X_SGMII_SPEED0_INVERT\t28\n++#define QCA955X_SGMII_SPEED1_INVERT\t29\n++#define QCA955X_SGMII_DUPLEX_INVERT\t30\n++#define QCA955X_SGMII_LINK_UP_INVERT\t31\n++#define QCA955X_GE1_MII_MDO\t\t32\n++#define QCA955X_GE1_MII_MDC\t\t33\n++#define QCA955X_SWCOM2\t\t\t38\n++#define QCA955X_SWCOM3\t\t\t39\n++#define QCA955X_MAC2_GPIO\t\t40\n++#define QCA955X_MAC3_GPIO\t\t41\n++#define QCA955X_ATT_LED\t\t\t42\n++#define QCA955X_PWR_LED\t\t\t43\n++#define QCA955X_TX_FRAME\t\t44\n++#define QCA955X_RX_CLEAR_EXTERNAL\t45\n++#define QCA955X_LED_NETWORK_EN\t\t46\n++#define QCA955X_LED_POWER_EN\t\t47\n++#define QCA955X_WMAC_GLUE_WOW\t\t68\n++#define QCA955X_RX_CLEAR_EXTENSION\t70\n++#define QCA955X_CP_NAND_CS1\t\t73\n++#define QCA955X_USB_SUSPEND\t\t74\n++#define QCA955X_ETH_TX_ERR\t\t75\n++#define QCA955X_DDR_DQ_OE\t\t76\n++#define QCA955X_CLKREQ_N_EP\t\t77\n++#define QCA955X_CLKREQ_N_RC\t\t78\n++#define QCA955X_CLK_OBS0\t\t79\n++#define QCA955X_CLK_OBS1\t\t80\n++#define QCA955X_CLK_OBS2\t\t81\n++#define QCA955X_CLK_OBS3\t\t82\n++#define QCA955X_CLK_OBS4\t\t83\n++#define QCA955X_CLK_OBS5\t\t84\n++\n +/*\n + * MII_CTRL block\n + */\ndiff --git a/target/linux/ar71xx/patches-3.18/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch b/target/linux/ar71xx/patches-3.18/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch\nindex 076a4a1..a36b8c3 100644\n--- a/target/linux/ar71xx/patches-3.18/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch\n+++ b/target/linux/ar71xx/patches-3.18/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch\n@@ -42,29 +42,3 @@\n  \ts = 8 * (gpio % 4);\n  \n  \tspin_lock_irqsave(&ath79_gpio_lock, flags);\n---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h\n-@@ -868,6 +868,14 @@\n- #define QCA953X_GPIO_OUT_MUX_LED_LINK4\t\t44\n- #define QCA953X_GPIO_OUT_MUX_LED_LINK5\t\t45\n- \n-+#define QCA955X_GPIO_REG_OUT_FUNC0\t0x2c\n-+#define QCA955X_GPIO_REG_OUT_FUNC1\t0x30\n-+#define QCA955X_GPIO_REG_OUT_FUNC2\t0x34\n-+#define QCA955X_GPIO_REG_OUT_FUNC3\t0x38\n-+#define QCA955X_GPIO_REG_OUT_FUNC4\t0x3c\n-+#define QCA955X_GPIO_REG_OUT_FUNC5\t0x40\n-+#define QCA955X_GPIO_REG_FUNC\t\t0x6c\n-+\n- #define QCA956X_GPIO_REG_OUT_FUNC0\t0x2c\n- #define QCA956X_GPIO_REG_OUT_FUNC1\t0x30\n- #define QCA956X_GPIO_REG_OUT_FUNC2\t0x34\n-@@ -1007,6 +1015,8 @@\n- #define AR934X_GPIO_OUT_EXT_LNA0\t46\n- #define AR934X_GPIO_OUT_EXT_LNA1\t47\n- \n-+#define QCA955X_GPIO_OUT_GPIO\t\t0\n-+\n- /*\n-  * MII_CTRL block\n-  */\n",
    "prefixes": [
        "OpenWrt-Devel",
        "CC",
        "13/34"
    ]
}