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GET /api/patches/591651/?format=api
{ "id": 591651, "url": "http://patchwork.ozlabs.org/api/patches/591651/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1457049194-9281-8-git-send-email-gwshan@linux.vnet.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1457049194-9281-8-git-send-email-gwshan@linux.vnet.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1457049194-9281-8-git-send-email-gwshan@linux.vnet.ibm.com/", "date": "2016-03-03T23:53:09", "name": "[v15,07/12] powerpc/powernv: Support EEH reset for VF PE", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "3bfff757118744eea8d5026535c22e47630e2775", "submitter": { "id": 63923, "url": "http://patchwork.ozlabs.org/api/people/63923/?format=api", "name": "Gavin Shan", "email": "gwshan@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1457049194-9281-8-git-send-email-gwshan@linux.vnet.ibm.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/591651/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/591651/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 72E781401AD\n\tfor <patchwork-incoming@ozlabs.org>;\n\tFri, 4 Mar 2016 11:00:50 +1100 (AEDT)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 594F21A1769\n\tfor <patchwork-incoming@ozlabs.org>;\n\tFri, 4 Mar 2016 11:00:50 +1100 (AEDT)", "from e23smtp04.au.ibm.com (e23smtp04.au.ibm.com [202.81.31.146])\n\t(using TLSv1.2 with cipher CAMELLIA256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 819841A0C82\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tFri, 4 Mar 2016 10:54:39 +1100 (AEDT)", "from localhost\n\tby e23smtp04.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <linuxppc-dev@lists.ozlabs.org> from <gwshan@linux.vnet.ibm.com>; \n\tFri, 4 Mar 2016 09:54:39 +1000", "from d23dlp01.au.ibm.com (202.81.31.203)\n\tby e23smtp04.au.ibm.com (202.81.31.210) with IBM ESMTP SMTP Gateway:\n\tAuthorized Use Only! Violators will be prosecuted; \n\tFri, 4 Mar 2016 09:54:37 +1000", "from d23relay10.au.ibm.com (d23relay10.au.ibm.com [9.190.26.77])\n\tby d23dlp01.au.ibm.com (Postfix) with ESMTP id 5EA2B2CE805D\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tFri, 4 Mar 2016 10:54:37 +1100 (EST)", "from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97])\n\tby d23relay10.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n\tu23NsT6f63111346\n\tfor <linuxppc-dev@lists.ozlabs.org>; Fri, 4 Mar 2016 10:54:37 +1100", "from d23av03.au.ibm.com (localhost [127.0.0.1])\n\tby d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id\n\tu23Ns4Lv002701\n\tfor <linuxppc-dev@lists.ozlabs.org>; Fri, 4 Mar 2016 10:54:05 +1100", "from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14])\n\tby d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id\n\tu23Ns4Dr002230; Fri, 4 Mar 2016 10:54:04 +1100", "from bran.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114])\n\tby ozlabs.au.ibm.com (Postfix) with ESMTP id 703E9A027A;\n\tFri, 4 Mar 2016 10:53:17 +1100 (AEDT)", "from gwshan (shangw.ozlabs.ibm.com [10.61.2.199])\n\tby bran.ozlabs.ibm.com (Postfix) with ESMTP id 6D862E39EB;\n\tFri, 4 Mar 2016 10:53:17 +1100 (AEDT)", "by gwshan (Postfix, from userid 1000)\n\tid 5B2709424AF; Fri, 4 Mar 2016 10:53:17 +1100 (AEDT)" ], "X-IBM-Helo": "d23dlp01.au.ibm.com", "X-IBM-MailFrom": "gwshan@linux.vnet.ibm.com", "X-IBM-RcptTo": "linuxppc-dev@lists.ozlabs.org", "From": "Gavin Shan <gwshan@linux.vnet.ibm.com>", "To": "linuxppc-dev@lists.ozlabs.org", "Subject": "[PATCH v15 07/12] powerpc/powernv: Support EEH reset for VF PE", "Date": "Fri, 4 Mar 2016 10:53:09 +1100", "Message-Id": "<1457049194-9281-8-git-send-email-gwshan@linux.vnet.ibm.com>", "X-Mailer": "git-send-email 2.1.0", "In-Reply-To": "<1457049194-9281-1-git-send-email-gwshan@linux.vnet.ibm.com>", "References": "<1457049194-9281-1-git-send-email-gwshan@linux.vnet.ibm.com>", "X-TM-AS-MML": "disable", "X-Content-Scanned": "Fidelis XPS MAILER", "x-cbid": "16030323-0013-0000-0000-000002D9B4EF", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.20", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Wei Yang <weiyang@linux.vnet.ibm.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "From: Wei Yang <weiyang@linux.vnet.ibm.com>\n\nPEs for VFs don't have primary bus. So they have to have their own reset\nbackend, which is used during EEH recovery. The patch implements the reset\nbackend for VF's PE by issuing FLR or AF FLR to the VFs, which are contained\nin the PE.\n\nSigned-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>\nAcked-by: Gavin Shan <gwshan@linux.vnet.ibm.com>\n---\n arch/powerpc/include/asm/eeh.h | 1 +\n arch/powerpc/kernel/eeh.c | 9 +-\n arch/powerpc/platforms/powernv/eeh-powernv.c | 127 ++++++++++++++++++++++++++-\n 3 files changed, 133 insertions(+), 4 deletions(-)", "diff": "diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h\nindex 0c551a2..b5b5f45 100644\n--- a/arch/powerpc/include/asm/eeh.h\n+++ b/arch/powerpc/include/asm/eeh.h\n@@ -137,6 +137,7 @@ struct eeh_dev {\n \tint pcix_cap;\t\t\t/* Saved PCIx capability\t*/\n \tint pcie_cap;\t\t\t/* Saved PCIe capability\t*/\n \tint aer_cap;\t\t\t/* Saved AER capability\t\t*/\n+\tint af_cap;\t\t\t/* Saved AF capability\t\t*/\n \tstruct eeh_pe *pe;\t\t/* Associated PE\t\t*/\n \tstruct list_head list;\t\t/* Form link list in the PE\t*/\n \tstruct pci_controller *phb;\t/* Associated PHB\t\t*/\ndiff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c\nindex 8c6005c..0d72462 100644\n--- a/arch/powerpc/kernel/eeh.c\n+++ b/arch/powerpc/kernel/eeh.c\n@@ -761,7 +761,8 @@ int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state stat\n \tcase pcie_deassert_reset:\n \t\teeh_ops->reset(pe, EEH_RESET_DEACTIVATE);\n \t\teeh_unfreeze_pe(pe, false);\n-\t\teeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED);\n+\t\tif (!(pe->type & EEH_PE_VF))\n+\t\t\teeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED);\n \t\teeh_pe_dev_traverse(pe, eeh_restore_dev_state, dev);\n \t\teeh_pe_state_clear(pe, EEH_PE_ISOLATED);\n \t\tbreak;\n@@ -769,14 +770,16 @@ int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state stat\n \t\teeh_pe_state_mark_with_cfg(pe, EEH_PE_ISOLATED);\n \t\teeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);\n \t\teeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);\n-\t\teeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);\n+\t\tif (!(pe->type & EEH_PE_VF))\n+\t\t\teeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);\n \t\teeh_ops->reset(pe, EEH_RESET_HOT);\n \t\tbreak;\n \tcase pcie_warm_reset:\n \t\teeh_pe_state_mark_with_cfg(pe, EEH_PE_ISOLATED);\n \t\teeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);\n \t\teeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);\n-\t\teeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);\n+\t\tif (!(pe->type & EEH_PE_VF))\n+\t\t\teeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);\n \t\teeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);\n \t\tbreak;\n \tdefault:\ndiff --git a/arch/powerpc/platforms/powernv/eeh-powernv.c b/arch/powerpc/platforms/powernv/eeh-powernv.c\nindex 830526e..e26256b 100644\n--- a/arch/powerpc/platforms/powernv/eeh-powernv.c\n+++ b/arch/powerpc/platforms/powernv/eeh-powernv.c\n@@ -371,6 +371,7 @@ static void *pnv_eeh_probe(struct pci_dn *pdn, void *data)\n \tedev->mode\t&= 0xFFFFFF00;\n \tedev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX);\n \tedev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP);\n+\tedev->af_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF);\n \tedev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR);\n \tif ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) {\n \t\tedev->mode |= EEH_DEV_BRIDGE;\n@@ -879,6 +880,120 @@ void pnv_pci_reset_secondary_bus(struct pci_dev *dev)\n \t}\n }\n \n+static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type,\n+\t\t\t\t int pos, u16 mask)\n+{\n+\tstruct eeh_dev *edev = pdn_to_eeh_dev(pdn);\n+\tint i, status = 0;\n+\n+\t/* Wait for Transaction Pending bit to be cleared */\n+\tfor (i = 0; i < 4; i++) {\n+\t\teeh_ops->read_config(pdn, pos, 2, &status);\n+\t\tif (!(status & mask))\n+\t\t\treturn;\n+\n+\t\tmsleep((1 << i) * 100);\n+\t}\n+\n+\tpr_warn(\"%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\\n\",\n+\t\t__func__, type,\n+\t\tedev->phb->global_number, pdn->busno,\n+\t\tPCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));\n+}\n+\n+static int pnv_eeh_do_flr(struct pci_dn *pdn, int option)\n+{\n+\tstruct eeh_dev *edev = pdn_to_eeh_dev(pdn);\n+\tu32 reg = 0;\n+\n+\tif (WARN_ON(!edev->pcie_cap))\n+\t\treturn -ENOTTY;\n+\n+\teeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®);\n+\tif (!(reg & PCI_EXP_DEVCAP_FLR))\n+\t\treturn -ENOTTY;\n+\n+\tswitch (option) {\n+\tcase EEH_RESET_HOT:\n+\tcase EEH_RESET_FUNDAMENTAL:\n+\t\tpnv_eeh_wait_for_pending(pdn, \"\",\n+\t\t\t\t\t edev->pcie_cap + PCI_EXP_DEVSTA,\n+\t\t\t\t\t PCI_EXP_DEVSTA_TRPND);\n+\t\teeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,\n+\t\t\t\t 4, ®);\n+\t\treg |= PCI_EXP_DEVCTL_BCR_FLR;\n+\t\teeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,\n+\t\t\t\t 4, reg);\n+\t\tmsleep(EEH_PE_RST_HOLD_TIME);\n+\t\tbreak;\n+\tcase EEH_RESET_DEACTIVATE:\n+\t\teeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,\n+\t\t\t\t 4, ®);\n+\t\treg &= ~PCI_EXP_DEVCTL_BCR_FLR;\n+\t\teeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,\n+\t\t\t\t 4, reg);\n+\t\tmsleep(EEH_PE_RST_SETTLE_TIME);\n+\t\tbreak;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option)\n+{\n+\tstruct eeh_dev *edev = pdn_to_eeh_dev(pdn);\n+\tu32 cap = 0;\n+\n+\tif (WARN_ON(!edev->af_cap))\n+\t\treturn -ENOTTY;\n+\n+\teeh_ops->read_config(pdn, edev->af_cap + PCI_AF_CAP, 1, &cap);\n+\tif (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))\n+\t\treturn -ENOTTY;\n+\n+\tswitch (option) {\n+\tcase EEH_RESET_HOT:\n+\tcase EEH_RESET_FUNDAMENTAL:\n+\t\t/*\n+\t\t * Wait for Transaction Pending bit to clear. A word-aligned\n+\t\t * test is used, so we use the conrol offset rather than status\n+\t\t * and shift the test bit to match.\n+\t\t */\n+\t\tpnv_eeh_wait_for_pending(pdn, \"AF\",\n+\t\t\t\t\t edev->af_cap + PCI_AF_CTRL,\n+\t\t\t\t\t PCI_AF_STATUS_TP << 8);\n+\t\teeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL,\n+\t\t\t\t 1, PCI_AF_CTRL_FLR);\n+\t\tmsleep(EEH_PE_RST_HOLD_TIME);\n+\t\tbreak;\n+\tcase EEH_RESET_DEACTIVATE:\n+\t\teeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1, 0);\n+\t\tmsleep(EEH_PE_RST_SETTLE_TIME);\n+\t\tbreak;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option)\n+{\n+\tstruct eeh_dev *edev;\n+\tstruct pci_dn *pdn;\n+\tint ret;\n+\n+\t/* The VF PE should have only one child device */\n+\tedev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, list);\n+\tpdn = eeh_dev_to_pdn(edev);\n+\tif (!pdn)\n+\t\treturn -ENXIO;\n+\n+\tret = pnv_eeh_do_flr(pdn, option);\n+\tif (!ret)\n+\t\treturn ret;\n+\n+\treturn pnv_eeh_do_af_flr(pdn, option);\n+}\n+\n /**\n * pnv_eeh_reset - Reset the specified PE\n * @pe: EEH PE\n@@ -940,7 +1055,9 @@ static int pnv_eeh_reset(struct eeh_pe *pe, int option)\n \t\t}\n \n \t\tbus = eeh_pe_bus_get(pe);\n-\t\tif (pci_is_root_bus(bus) ||\n+\t\tif (pe->type & EEH_PE_VF)\n+\t\t\tret = pnv_eeh_reset_vf_pe(pe, option);\n+\t\telse if (pci_is_root_bus(bus) ||\n \t\t\tpci_is_root_bus(bus->parent))\n \t\t\tret = pnv_eeh_root_reset(hose, option);\n \t\telse\n@@ -1079,6 +1196,14 @@ static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn)\n \tif (!edev || !edev->pe)\n \t\treturn false;\n \n+\t/*\n+\t * We will issue FLR or AF FLR to all VFs, which are contained\n+\t * in VF PE. It relies on the EEH PCI config accessors. So we\n+\t * can't block them during the window.\n+\t */\n+\tif (edev->physfn && (edev->pe->state & EEH_PE_RESET))\n+\t\treturn false;\n+\n \tif (edev->pe->state & EEH_PE_CFG_BLOCKED)\n \t\treturn true;\n \n", "prefixes": [ "v15", "07/12" ] }