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GET /api/patches/584398/?format=api
{ "id": 584398, "url": "http://patchwork.ozlabs.org/api/patches/584398/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1455754344-6372-12-git-send-email-avinash.dayanand@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1455754344-6372-12-git-send-email-avinash.dayanand@intel.com>", "list_archive_url": null, "date": "2016-02-18T00:12:21", "name": "[next,S29,11/14] i40e: Use the new rx ctl register helpers. Don't use AQ calls from clear_hw.", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "342cf7757ce903ff3445cb13094c60d6dcb1bd0b", "submitter": { "id": 67689, "url": "http://patchwork.ozlabs.org/api/people/67689/?format=api", "name": "Dayanand, Avinash", "email": "avinash.dayanand@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1455754344-6372-12-git-send-email-avinash.dayanand@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/584398/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/584398/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\tby ozlabs.org (Postfix) with ESMTP id C88BB140273\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 18 Feb 2016 11:12:41 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 26BCD9230A;\n\tThu, 18 Feb 2016 00:12:41 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id gD-ijYK87+Q5; Thu, 18 Feb 2016 00:12:37 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id EB80192375;\n\tThu, 18 Feb 2016 00:12:32 +0000 (UTC)", "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ash.osuosl.org (Postfix) with ESMTP id 8173C1C0BC2\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 18 Feb 2016 00:12:30 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 771F13115A\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 18 Feb 2016 00:12:30 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id UM84UPFXJTC4 for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 18 Feb 2016 00:12:27 +0000 (UTC)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby silver.osuosl.org (Postfix) with ESMTP id 91C7133B0C\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 18 Feb 2016 00:12:26 +0000 (UTC)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga103.fm.intel.com with ESMTP; 17 Feb 2016 16:12:27 -0800", "from jahay1-mobl2.amr.corp.intel.com (HELO\n\tlocalhost.localdomain.localdomain) ([134.134.3.116])\n\tby fmsmga002.fm.intel.com with ESMTP; 17 Feb 2016 16:12:26 -0800" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.22,463,1449561600\"; d=\"scan'208\";a=\"918067187\"", "From": "Avinash Dayanand <avinash.dayanand@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Wed, 17 Feb 2016 16:12:21 -0800", "Message-Id": "<1455754344-6372-12-git-send-email-avinash.dayanand@intel.com>", "X-Mailer": "git-send-email 2.1.0", "In-Reply-To": "<1455754344-6372-1-git-send-email-avinash.dayanand@intel.com>", "References": "<1455754344-6372-1-git-send-email-avinash.dayanand@intel.com>", "Subject": "[Intel-wired-lan] [next PATCH S29 11/14] i40e: Use the new rx ctl\n\tregister helpers. Don't use AQ calls from clear_hw.", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "From: Shannon Nelson <shannon.nelson@intel.com>\n\nUse the new AdminQ functions for safely accessing the Rx control\nregisters that may be affected by heavy small packet traffic.\n\nWe can't use AdminQ calls in i40e_clear_hw() because the HW is being\ninitialized and the AdminQ is not alive. We recently added an AQ\nrelated replacement for reading PFLAN_QALLOC, and this patch puts\nback the original register read.\n\nSigned-off-by: Shannon Nelson <shannon.nelson@intel.com>\nChange-ID: Ib027168c954a5733299aa3a4ce5f8218c6bb5636\n---\nTesting Hints:\n\tPlease be sure that flow director and RSS configuration changes\n\twork as expected both with and without stress traffic.\n\tMake sure the driver Loads.\n\n drivers/net/ethernet/intel/i40e/i40e_common.c | 2 +-\n drivers/net/ethernet/intel/i40e/i40e_ethtool.c | 8 ++++----\n drivers/net/ethernet/intel/i40e/i40e_fcoe.c | 8 ++++----\n drivers/net/ethernet/intel/i40e/i40e_main.c | 20 ++++++++++----------\n drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c | 7 ++++---\n 5 files changed, 23 insertions(+), 22 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c\nindex 74d9599..4596294 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_common.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_common.c\n@@ -1328,7 +1328,7 @@ void i40e_clear_hw(struct i40e_hw *hw)\n \tnum_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>\n \t\t I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;\n \n-\tval = i40e_read_rx_ctl(hw, I40E_PFLAN_QALLOC);\n+\tval = rd32(hw, I40E_PFLAN_QALLOC);\n \tbase_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>\n \t\t I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;\n \tj = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c\nindex 86765d4..8705702 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c\n@@ -2181,8 +2181,8 @@ static int i40e_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,\n static int i40e_set_rss_hash_opt(struct i40e_pf *pf, struct ethtool_rxnfc *nfc)\n {\n \tstruct i40e_hw *hw = &pf->hw;\n-\tu64 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |\n-\t\t ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);\n+\tu64 hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |\n+\t\t ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);\n \n \t/* RSS does not support anything other than hashing\n \t * to queues on src and dst IPs and ports\n@@ -2291,8 +2291,8 @@ static int i40e_set_rss_hash_opt(struct i40e_pf *pf, struct ethtool_rxnfc *nfc)\n \t\treturn -EINVAL;\n \t}\n \n-\twr32(hw, I40E_PFQF_HENA(0), (u32)hena);\n-\twr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));\n+\ti40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);\n+\ti40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));\n \ti40e_flush(hw);\n \n \t/* Save setting for future output/update */\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_fcoe.c b/drivers/net/ethernet/intel/i40e/i40e_fcoe.c\nindex 052df93..8ad162c 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_fcoe.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_fcoe.c\n@@ -295,11 +295,11 @@ void i40e_init_pf_fcoe(struct i40e_pf *pf)\n \t}\n \n \t/* enable FCoE hash filter */\n-\tval = rd32(hw, I40E_PFQF_HENA(1));\n+\tval = i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1));\n \tval |= BIT(I40E_FILTER_PCTYPE_FCOE_OX - 32);\n \tval |= BIT(I40E_FILTER_PCTYPE_FCOE_RX - 32);\n \tval &= I40E_PFQF_HENA_PTYPE_ENA_MASK;\n-\twr32(hw, I40E_PFQF_HENA(1), val);\n+\ti40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), val);\n \n \t/* enable flag */\n \tpf->flags |= I40E_FLAG_FCOE_ENABLED;\n@@ -317,11 +317,11 @@ void i40e_init_pf_fcoe(struct i40e_pf *pf)\n \tpf->filter_settings.fcoe_cntx_num = I40E_DMA_CNTX_SIZE_4K;\n \n \t/* Setup max frame with FCoE_MTU plus L2 overheads */\n-\tval = rd32(hw, I40E_GLFCOE_RCTL);\n+\tval = i40e_read_rx_ctl(hw, I40E_GLFCOE_RCTL);\n \tval &= ~I40E_GLFCOE_RCTL_MAX_SIZE_MASK;\n \tval |= ((FCOE_MTU + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)\n \t\t << I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT);\n-\twr32(hw, I40E_GLFCOE_RCTL, val);\n+\ti40e_write_rx_ctl(hw, I40E_GLFCOE_RCTL, val);\n \n \tdev_info(&pf->pdev->dev, \"FCoE is supported.\\n\");\n }\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c\nindex 3c910ef..7388c1a 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_main.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_main.c\n@@ -8028,7 +8028,7 @@ static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed,\n \t\tu32 *seed_dw = (u32 *)seed;\n \n \t\tfor (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)\n-\t\t\twr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]);\n+\t\t\ti40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), seed_dw[i]);\n \t}\n \n \tif (lut) {\n@@ -8065,7 +8065,7 @@ static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed,\n \t\tu32 *seed_dw = (u32 *)seed;\n \n \t\tfor (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)\n-\t\t\tseed_dw[i] = rd32(hw, I40E_PFQF_HKEY(i));\n+\t\t\tseed_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));\n \t}\n \tif (lut) {\n \t\tu32 *lut_dw = (u32 *)lut;\n@@ -8148,19 +8148,19 @@ static int i40e_pf_config_rss(struct i40e_pf *pf)\n \tint ret;\n \n \t/* By default we enable TCP/UDP with IPv4/IPv6 ptypes */\n-\thena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |\n-\t\t((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);\n+\thena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |\n+\t\t((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);\n \thena |= i40e_pf_get_default_rss_hena(pf);\n \n-\twr32(hw, I40E_PFQF_HENA(0), (u32)hena);\n-\twr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));\n+\ti40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);\n+\ti40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));\n \n \t/* Determine the RSS table size based on the hardware capabilities */\n-\treg_val = rd32(hw, I40E_PFQF_CTL_0);\n+\treg_val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);\n \treg_val = (pf->rss_table_size == 512) ?\n \t\t\t(reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :\n \t\t\t(reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);\n-\twr32(hw, I40E_PFQF_CTL_0, reg_val);\n+\ti40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, reg_val);\n \n \t/* Determine the RSS size of the VSI */\n \tif (!vsi->rss_size)\n@@ -11207,8 +11207,8 @@ static void i40e_remove(struct pci_dev *pdev)\n \ti40e_ptp_stop(pf);\n \n \t/* Disable RSS in hw */\n-\twr32(hw, I40E_PFQF_HENA(0), 0);\n-\twr32(hw, I40E_PFQF_HENA(1), 0);\n+\ti40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);\n+\ti40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);\n \n \t/* no more scheduling of any task */\n \tset_bit(__I40E_DOWN, &pf->state);\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c\nindex 5dcd198..93d8d98 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c\n@@ -602,8 +602,8 @@ static void i40e_enable_vf_mappings(struct i40e_vf *vf)\n \t * that VF queues be mapped using this method, even when they are\n \t * contiguous in real life\n \t */\n-\twr32(hw, I40E_VSILAN_QBASE(vf->lan_vsi_id),\n-\t I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);\n+\ti40e_write_rx_ctl(hw, I40E_VSILAN_QBASE(vf->lan_vsi_id),\n+\t\t\t I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);\n \n \t/* enable VF vplan_qtable mappings */\n \treg = I40E_VPLAN_MAPENA_TXRX_ENA_MASK;\n@@ -630,7 +630,8 @@ static void i40e_enable_vf_mappings(struct i40e_vf *vf)\n \t\t\t\t\t\t (j * 2) + 1);\n \t\t\treg |= qid << 16;\n \t\t}\n-\t\twr32(hw, I40E_VSILAN_QTABLE(j, vf->lan_vsi_id), reg);\n+\t\ti40e_write_rx_ctl(hw, I40E_VSILAN_QTABLE(j, vf->lan_vsi_id),\n+\t\t\t\t reg);\n \t}\n \n \ti40e_flush(hw);\n", "prefixes": [ "next", "S29", "11/14" ] }