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GET /api/patches/584397/?format=api
{ "id": 584397, "url": "http://patchwork.ozlabs.org/api/patches/584397/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1455754344-6372-2-git-send-email-avinash.dayanand@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1455754344-6372-2-git-send-email-avinash.dayanand@intel.com>", "list_archive_url": null, "date": "2016-02-18T00:12:11", "name": "[next,S29,01/14] i40e: Add functions to blink led on 10GBaseT PHY", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "d5d4683cc5b366de4e393ca9220d544b76928b60", "submitter": { "id": 67689, "url": "http://patchwork.ozlabs.org/api/people/67689/?format=api", "name": "Dayanand, Avinash", "email": "avinash.dayanand@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1455754344-6372-2-git-send-email-avinash.dayanand@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/584397/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/584397/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\tby ozlabs.org (Postfix) with ESMTP id 7C0D414018C\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 18 Feb 2016 11:12:41 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id CF955921C8;\n\tThu, 18 Feb 2016 00:12:40 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 6NyW0fi6T+37; Thu, 18 Feb 2016 00:12:34 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 7F1F79230A;\n\tThu, 18 Feb 2016 00:12:32 +0000 (UTC)", "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ash.osuosl.org (Postfix) with ESMTP id 202CD1C0BC2\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 18 Feb 2016 00:12:29 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 1C1F23115A\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 18 Feb 2016 00:12:29 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id b7T8x1jBL1nG for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 18 Feb 2016 00:12:25 +0000 (UTC)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby silver.osuosl.org (Postfix) with ESMTP id 8BAF1338FA\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 18 Feb 2016 00:12:25 +0000 (UTC)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga103.fm.intel.com with ESMTP; 17 Feb 2016 16:12:26 -0800", "from jahay1-mobl2.amr.corp.intel.com (HELO\n\tlocalhost.localdomain.localdomain) ([134.134.3.116])\n\tby fmsmga002.fm.intel.com with ESMTP; 17 Feb 2016 16:12:25 -0800" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.22,463,1449561600\"; d=\"scan'208\";a=\"918067168\"", "From": "Avinash Dayanand <avinash.dayanand@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Wed, 17 Feb 2016 16:12:11 -0800", "Message-Id": "<1455754344-6372-2-git-send-email-avinash.dayanand@intel.com>", "X-Mailer": "git-send-email 2.1.0", "In-Reply-To": "<1455754344-6372-1-git-send-email-avinash.dayanand@intel.com>", "References": "<1455754344-6372-1-git-send-email-avinash.dayanand@intel.com>", "Subject": "[Intel-wired-lan] [next PATCH S29 01/14] i40e: Add functions to\n\tblink led on 10GBaseT PHY", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "From: Carolyn Wyborny <carolyn.wyborny@intel.com>\n\nThis patch adds functions to blink led on devices using\n10GBaseT PHY since MAC registers used in other designs\ndo not work in this device configuration.\n\nSigned-off-by: Carolyn Wyborny <carolyn.wyborny@intel.com>\nChange-ID: Id4b88c93c649fd2b88073a00b42867a77c761ca3\n---\n drivers/net/ethernet/intel/i40e/i40e_common.c | 329 +++++++++++++++++++++\n drivers/net/ethernet/intel/i40e/i40e_prototype.h | 13 +\n drivers/net/ethernet/intel/i40e/i40e_type.h | 16 +\n drivers/net/ethernet/intel/i40evf/i40e_prototype.h | 7 +\n 4 files changed, 365 insertions(+)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c\nindex f923933..447729f 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_common.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_common.c\n@@ -4214,3 +4214,332 @@ i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,\n \n \treturn status;\n }\n+\n+/**\n+ * i40e_read_phy_register\n+ * @hw: pointer to the HW structure\n+ * @page: registers page number\n+ * @reg: register address in the page\n+ * @phy_adr: PHY address on MDIO interface\n+ * @value: PHY register value\n+ *\n+ * Reads specified PHY register value\n+ **/\n+i40e_status i40e_read_phy_register(struct i40e_hw *hw,\n+\t\t\t\t u8 page, u16 reg, u8 phy_addr,\n+\t\t\t\t u16 *value)\n+{\n+\ti40e_status status = I40E_ERR_TIMEOUT;\n+\tu32 command = 0;\n+\tu16 retry = 1000;\n+\tu8 port_num = hw->func_caps.mdio_port_num;\n+\n+\tcommand = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |\n+\t\t (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |\n+\t\t (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |\n+\t\t (I40E_MDIO_OPCODE_ADDRESS) |\n+\t\t (I40E_MDIO_STCODE) |\n+\t\t (I40E_GLGEN_MSCA_MDICMD_MASK) |\n+\t\t (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);\n+\twr32(hw, I40E_GLGEN_MSCA(port_num), command);\n+\tdo {\n+\t\tcommand = rd32(hw, I40E_GLGEN_MSCA(port_num));\n+\t\tif (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {\n+\t\t\tstatus = 0;\n+\t\t\tbreak;\n+\t\t}\n+\t\tusleep_range(10, 20);\n+\t\tretry--;\n+\t} while (retry);\n+\n+\tif (status) {\n+\t\ti40e_debug(hw, I40E_DEBUG_PHY,\n+\t\t\t \"PHY: Can't write command to external PHY.\\n\");\n+\t\tgoto phy_read_end;\n+\t}\n+\n+\tcommand = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |\n+\t\t (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |\n+\t\t (I40E_MDIO_OPCODE_READ) |\n+\t\t (I40E_MDIO_STCODE) |\n+\t\t (I40E_GLGEN_MSCA_MDICMD_MASK) |\n+\t\t (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);\n+\tstatus = I40E_ERR_TIMEOUT;\n+\tretry = 1000;\n+\twr32(hw, I40E_GLGEN_MSCA(port_num), command);\n+\tdo {\n+\t\tcommand = rd32(hw, I40E_GLGEN_MSCA(port_num));\n+\t\tif (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {\n+\t\t\tstatus = 0;\n+\t\t\tbreak;\n+\t\t}\n+\t\tusleep_range(10, 20);\n+\t\tretry--;\n+\t} while (retry);\n+\n+\tif (!status) {\n+\t\tcommand = rd32(hw, I40E_GLGEN_MSRWD(port_num));\n+\t\t*value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>\n+\t\t\t I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;\n+\t} else {\n+\t\ti40e_debug(hw, I40E_DEBUG_PHY,\n+\t\t\t \"PHY: Can't read register value from external PHY.\\n\");\n+\t}\n+\n+phy_read_end:\n+\treturn status;\n+}\n+\n+/**\n+ * i40e_write_phy_register\n+ * @hw: pointer to the HW structure\n+ * @page: registers page number\n+ * @reg: register address in the page\n+ * @phy_adr: PHY address on MDIO interface\n+ * @value: PHY register value\n+ *\n+ * Writes value to specified PHY register\n+ **/\n+i40e_status i40e_write_phy_register(struct i40e_hw *hw,\n+\t\t\t\t u8 page, u16 reg, u8 phy_addr,\n+\t\t\t\t u16 value)\n+{\n+\ti40e_status status = I40E_ERR_TIMEOUT;\n+\tu32 command = 0;\n+\tu16 retry = 1000;\n+\tu8 port_num = hw->func_caps.mdio_port_num;\n+\n+\tcommand = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |\n+\t\t (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |\n+\t\t (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |\n+\t\t (I40E_MDIO_OPCODE_ADDRESS) |\n+\t\t (I40E_MDIO_STCODE) |\n+\t\t (I40E_GLGEN_MSCA_MDICMD_MASK) |\n+\t\t (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);\n+\twr32(hw, I40E_GLGEN_MSCA(port_num), command);\n+\tdo {\n+\t\tcommand = rd32(hw, I40E_GLGEN_MSCA(port_num));\n+\t\tif (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {\n+\t\t\tstatus = 0;\n+\t\t\tbreak;\n+\t\t}\n+\t\tusleep_range(10, 20);\n+\t\tretry--;\n+\t} while (retry);\n+\tif (status) {\n+\t\ti40e_debug(hw, I40E_DEBUG_PHY,\n+\t\t\t \"PHY: Can't write command to external PHY.\\n\");\n+\t\tgoto phy_write_end;\n+\t}\n+\n+\tcommand = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;\n+\twr32(hw, I40E_GLGEN_MSRWD(port_num), command);\n+\n+\tcommand = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |\n+\t\t (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |\n+\t\t (I40E_MDIO_OPCODE_WRITE) |\n+\t\t (I40E_MDIO_STCODE) |\n+\t\t (I40E_GLGEN_MSCA_MDICMD_MASK) |\n+\t\t (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);\n+\tstatus = I40E_ERR_TIMEOUT;\n+\tretry = 1000;\n+\twr32(hw, I40E_GLGEN_MSCA(port_num), command);\n+\tdo {\n+\t\tcommand = rd32(hw, I40E_GLGEN_MSCA(port_num));\n+\t\tif (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {\n+\t\t\tstatus = 0;\n+\t\t\tbreak;\n+\t\t}\n+\t\tusleep_range(10, 20);\n+\t\tretry--;\n+\t} while (retry);\n+\n+phy_write_end:\n+\treturn status;\n+}\n+\n+/**\n+ * i40e_get_phy_address\n+ * @hw: pointer to the HW structure\n+ * @dev_num: PHY port num that address we want\n+ * @phy_addr: Returned PHY address\n+ *\n+ * Gets PHY address for current port\n+ **/\n+u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)\n+{\n+\tu8 port_num = hw->func_caps.mdio_port_num;\n+\tu32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));\n+\n+\treturn (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;\n+}\n+\n+/**\n+ * i40e_blink_phy_led\n+ * @hw: pointer to the HW structure\n+ * @time: time how long led will blinks in secs\n+ * @interval: gap between LED on and off in msecs\n+ *\n+ * Blinks PHY link LED\n+ **/\n+i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,\n+\t\t\t\t u32 time, u32 interval)\n+{\n+\ti40e_status status = 0;\n+\tu32 i;\n+\tu16 led_ctl;\n+\tu16 gpio_led_port;\n+\tu16 led_reg;\n+\tu16 led_addr = I40E_PHY_LED_PROV_REG_1;\n+\tu8 phy_addr = 0;\n+\tu8 port_num;\n+\n+\ti = rd32(hw, I40E_PFGEN_PORTNUM);\n+\tport_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);\n+\tphy_addr = i40e_get_phy_address(hw, port_num);\n+\n+\tfor (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,\n+\t led_addr++) {\n+\t\tstatus = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\tled_addr, phy_addr, &led_reg);\n+\t\tif (status)\n+\t\t\tgoto phy_blinking_end;\n+\t\tled_ctl = led_reg;\n+\t\tif (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {\n+\t\t\tled_reg = 0;\n+\t\t\tstatus = i40e_write_phy_register(hw,\n+\t\t\t\t\t\t\t I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\t\t led_addr, phy_addr,\n+\t\t\t\t\t\t\t led_reg);\n+\t\t\tif (status)\n+\t\t\t\tgoto phy_blinking_end;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tif (time > 0 && interval > 0) {\n+\t\tfor (i = 0; i < time * 1000; i += interval) {\n+\t\t\tstatus = i40e_read_phy_register(hw,\n+\t\t\t\t\t\t\tI40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\t\tled_addr, phy_addr,\n+\t\t\t\t\t\t\t&led_reg);\n+\t\t\tif (status)\n+\t\t\t\tgoto restore_config;\n+\t\t\tif (led_reg & I40E_PHY_LED_MANUAL_ON)\n+\t\t\t\tled_reg = 0;\n+\t\t\telse\n+\t\t\t\tled_reg = I40E_PHY_LED_MANUAL_ON;\n+\t\t\tstatus = i40e_write_phy_register(hw,\n+\t\t\t\t\t\t\t I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\t\t led_addr, phy_addr,\n+\t\t\t\t\t\t\t led_reg);\n+\t\t\tif (status)\n+\t\t\t\tgoto restore_config;\n+\t\t\tmsleep(interval);\n+\t\t}\n+\t}\n+\n+restore_config:\n+\tstatus = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,\n+\t\t\t\t\t phy_addr, led_ctl);\n+\n+phy_blinking_end:\n+\treturn status;\n+}\n+\n+/**\n+ * i40e_led_get_phy - return current on/off mode\n+ * @hw: pointer to the hw struct\n+ * @led_addr: address of led register to use\n+ * @val: original value of register to use\n+ *\n+ **/\n+i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,\n+\t\t\t u16 *val)\n+{\n+\ti40e_status status = 0;\n+\tu16 gpio_led_port;\n+\tu8 phy_addr = 0;\n+\tu16 reg_val;\n+\tu16 temp_addr;\n+\tu8 port_num;\n+\tu32 i;\n+\n+\ttemp_addr = I40E_PHY_LED_PROV_REG_1;\n+\ti = rd32(hw, I40E_PFGEN_PORTNUM);\n+\tport_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);\n+\tphy_addr = i40e_get_phy_address(hw, port_num);\n+\n+\tfor (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,\n+\t temp_addr++) {\n+\t\tstatus = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\ttemp_addr, phy_addr, ®_val);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t\t*val = reg_val;\n+\t\tif (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {\n+\t\t\t*led_addr = temp_addr;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\treturn status;\n+}\n+\n+/**\n+ * i40e_led_set_phy\n+ * @hw: pointer to the HW structure\n+ * @on: true or false\n+ * @mode: original val plus bit for set or ignore\n+ * Set led's on or off when controlled by the PHY\n+ *\n+ **/\n+i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,\n+\t\t\t u16 led_addr, u32 mode)\n+{\n+\ti40e_status status = 0;\n+\tu16 led_ctl = 0;\n+\tu16 led_reg = 0;\n+\tu8 phy_addr = 0;\n+\tu8 port_num;\n+\tu32 i;\n+\n+\ti = rd32(hw, I40E_PFGEN_PORTNUM);\n+\tport_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);\n+\tphy_addr = i40e_get_phy_address(hw, port_num);\n+\n+\tstatus = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,\n+\t\t\t\t\tphy_addr, &led_reg);\n+\tif (status)\n+\t\treturn status;\n+\tled_ctl = led_reg;\n+\tif (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {\n+\t\tled_reg = 0;\n+\t\tstatus = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\t led_addr, phy_addr, led_reg);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\tstatus = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\tled_addr, phy_addr, &led_reg);\n+\tif (status)\n+\t\tgoto restore_config;\n+\tif (on)\n+\t\tled_reg = I40E_PHY_LED_MANUAL_ON;\n+\telse\n+\t\tled_reg = 0;\n+\tstatus = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t led_addr, phy_addr, led_reg);\n+\tif (status)\n+\t\tgoto restore_config;\n+\tif (mode & I40E_PHY_LED_MODE_ORIG) {\n+\t\tled_ctl = (mode & I40E_PHY_LED_MODE_MASK);\n+\t\tstatus = i40e_write_phy_register(hw,\n+\t\t\t\t\t\t I40E_PHY_COM_REG_PAGE,\n+\t\t\t\t\t\t led_addr, phy_addr, led_ctl);\n+\t}\n+\treturn status;\n+restore_config:\n+\tstatus = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,\n+\t\t\t\t\t phy_addr, led_ctl);\n+\treturn status;\n+}\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_prototype.h b/drivers/net/ethernet/intel/i40e/i40e_prototype.h\nindex e8deabd..ca2f7ac 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_prototype.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_prototype.h\n@@ -74,6 +74,12 @@ i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,\n \n u32 i40e_led_get(struct i40e_hw *hw);\n void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink);\n+i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,\n+\t\t\t u16 led_addr, u32 mode);\n+i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,\n+\t\t\t u16 *val);\n+i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,\n+\t\t\t\t u32 time, u32 interval);\n \n /* admin send queue commands */\n \n@@ -336,4 +342,11 @@ i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,\n \t\t\t struct i40e_asq_cmd_details *cmd_details);\n void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,\n \t\t\t\t\t\t u16 vsi_seid);\n+i40e_status i40e_read_phy_register(struct i40e_hw *hw, u8 page,\n+\t\t\t\t u16 reg, u8 phy_addr, u16 *value);\n+i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page,\n+\t\t\t\t u16 reg, u8 phy_addr, u16 value);\n+u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num);\n+i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,\n+\t\t\t\t u32 time, u32 interval);\n #endif /* _I40E_PROTOTYPE_H_ */\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_type.h b/drivers/net/ethernet/intel/i40e/i40e_type.h\nindex b59a021..0a0baf7 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_type.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_type.h\n@@ -90,6 +90,22 @@ enum i40e_debug_mask {\n \tI40E_DEBUG_ALL\t\t\t= 0xFFFFFFFF\n };\n \n+#define I40E_MDIO_STCODE 0\n+#define I40E_MDIO_OPCODE_ADDRESS 0\n+#define I40E_MDIO_OPCODE_WRITE I40E_MASK(1, \\\n+\t\t\t\t\t\t I40E_GLGEN_MSCA_OPCODE_SHIFT)\n+#define I40E_MDIO_OPCODE_READ_INC_ADDR I40E_MASK(2, \\\n+\t\t\t\t\t\t I40E_GLGEN_MSCA_OPCODE_SHIFT)\n+#define I40E_MDIO_OPCODE_READ I40E_MASK(3, \\\n+\t\t\t\t\t\t I40E_GLGEN_MSCA_OPCODE_SHIFT)\n+\n+#define I40E_PHY_COM_REG_PAGE 0x1E\n+#define I40E_PHY_LED_LINK_MODE_MASK 0xF0\n+#define I40E_PHY_LED_MANUAL_ON 0x100\n+#define I40E_PHY_LED_PROV_REG_1 0xC430\n+#define I40E_PHY_LED_MODE_MASK 0xFFFF\n+#define I40E_PHY_LED_MODE_ORIG 0x80000000\n+\n /* These are structs for managing the hardware information and the operations.\n * The structures of function pointers are filled out at init time when we\n * know for sure exactly which hardware we're working with. This gives us the\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_prototype.h b/drivers/net/ethernet/intel/i40evf/i40e_prototype.h\nindex cbd9a1b..fa34d85 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_prototype.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_prototype.h\n@@ -103,4 +103,11 @@ i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,\n \t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,\n \t\t\t\t\t\t u16 vsi_seid);\n+i40e_status i40e_read_phy_register(struct i40e_hw *hw, u8 page,\n+\t\t\t\t u16 reg, u8 phy_addr, u16 *value);\n+i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page,\n+\t\t\t\t u16 reg, u8 phy_addr, u16 value);\n+u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num);\n+i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,\n+\t\t\t\t u32 time, u32 interval);\n #endif /* _I40E_PROTOTYPE_H_ */\n", "prefixes": [ "next", "S29", "01/14" ] }