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GET /api/patches/584396/?format=api
{ "id": 584396, "url": "http://patchwork.ozlabs.org/api/patches/584396/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1455754344-6372-10-git-send-email-avinash.dayanand@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1455754344-6372-10-git-send-email-avinash.dayanand@intel.com>", "list_archive_url": null, "date": "2016-02-18T00:12:19", "name": "[next,S29,09/14] i40e: add adminq commands for rx ctl registers", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "077668210176367d025c088f0400c57af919cbe3", "submitter": { "id": 67689, "url": "http://patchwork.ozlabs.org/api/people/67689/?format=api", "name": "Dayanand, Avinash", "email": "avinash.dayanand@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1455754344-6372-10-git-send-email-avinash.dayanand@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/584396/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/584396/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\tby ozlabs.org (Postfix) with ESMTP id 7D37E140273\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 18 Feb 2016 11:12:38 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id D1152922AD;\n\tThu, 18 Feb 2016 00:12:37 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id XnPpOCyBy9UU; Thu, 18 Feb 2016 00:12:33 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 3E29A92299;\n\tThu, 18 Feb 2016 00:12:32 +0000 (UTC)", "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ash.osuosl.org (Postfix) with ESMTP id 867C91C0BC2\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 18 Feb 2016 00:12:28 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 82EFF339BB\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 18 Feb 2016 00:12:28 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id IYdUCWXWGwhK for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 18 Feb 2016 00:12:27 +0000 (UTC)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby silver.osuosl.org (Postfix) with ESMTP id 702EF33B05\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 18 Feb 2016 00:12:26 +0000 (UTC)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga103.fm.intel.com with ESMTP; 17 Feb 2016 16:12:27 -0800", "from jahay1-mobl2.amr.corp.intel.com (HELO\n\tlocalhost.localdomain.localdomain) ([134.134.3.116])\n\tby fmsmga002.fm.intel.com with ESMTP; 17 Feb 2016 16:12:25 -0800" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.22,463,1449561600\"; d=\"scan'208\";a=\"918067184\"", "From": "Avinash Dayanand <avinash.dayanand@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Wed, 17 Feb 2016 16:12:19 -0800", "Message-Id": "<1455754344-6372-10-git-send-email-avinash.dayanand@intel.com>", "X-Mailer": "git-send-email 2.1.0", "In-Reply-To": "<1455754344-6372-1-git-send-email-avinash.dayanand@intel.com>", "References": "<1455754344-6372-1-git-send-email-avinash.dayanand@intel.com>", "Subject": "[Intel-wired-lan] [next PATCH S29 09/14] i40e: add adminq commands\n\tfor rx ctl registers", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "From: Shannon Nelson <shannon.nelson@intel.com>\n\nAdd the new opcodes and struct used for asking the firmware to update Rx\ncontrol registers that need extra care when being accessed while under\nheavy traffic - e.g. sustained 64byte packets at line rate on all ports.\nThe firmware will take extra steps to be sure the register accesses\nare successful.\n\nThe registers involved are:\n\tPFQF_CTL_0\n\tPFQF_HENA\n\tPFQF_FDALLOC\n\tPFQF_HREGION\n\tPFLAN_QALLOC\n\tVPQF_CTL\n\tVFQF_HENA\n\tVFQF_HREGION\n\tVSIQF_CTL\n\tVSILAN_QBASE\n\tVSILAN_QTABLE\n\tVSIQF_TCREGION\n\tPFQF_HKEY\n\tVFQF_HKEY\n\tPRTQF_CTL_0\n\tGLFCOE_RCTL\n\tGLFCOE_RSOF\n\tGLQF_CTL\n\tGLQF_SWAP\n\tGLQF_HASH_MSK\n\tGLQF_HASH_INSET\n\tGLQF_HSYM\n\tGLQF_FC_MSK\n\tGLQF_FC_INSET\n\tGLQF_FD_MSK\n\tPRTQF_FD_INSET\n\tPRTQF_FD_FLXINSET\n\tPRTQF_FD_MSK\n\nSigned-off-by: Shannon Nelson <shannon.nelson@intel.com>\nChange-ID: I56c8144000da66ad99f68948d8a184b2ec2aeb3e\n---\n drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h | 16 ++++++++++++++++\n drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h | 16 ++++++++++++++++\n 2 files changed, 32 insertions(+)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h\nindex bb7ecbb..8d5c65a 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h\n@@ -146,6 +146,8 @@ enum i40e_admin_queue_opc {\n \ti40e_aqc_opc_set_port_parameters\t= 0x0203,\n \ti40e_aqc_opc_get_switch_resource_alloc\t= 0x0204,\n \ti40e_aqc_opc_set_switch_config\t\t= 0x0205,\n+\ti40e_aqc_opc_rx_ctl_reg_read\t\t= 0x0206,\n+\ti40e_aqc_opc_rx_ctl_reg_write\t\t= 0x0207,\n \n \ti40e_aqc_opc_add_vsi\t\t\t= 0x0210,\n \ti40e_aqc_opc_update_vsi_parameters\t= 0x0211,\n@@ -696,6 +698,20 @@ struct i40e_aqc_set_switch_config {\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);\n \n+/* Read Receive control registers (direct 0x0206)\n+ * Write Receive control registers (direct 0x0207)\n+ * used for accessing Rx control registers that can be\n+ * slow and need special handling when under high Rx load\n+ */\n+struct i40e_aqc_rx_ctl_reg_read_write {\n+\t__le32 reserved1;\n+\t__le32 address;\n+\t__le32 reserved2;\n+\t__le32 value;\n+};\n+\n+I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);\n+\n /* Add VSI (indirect 0x0210)\n * this indirect command uses struct i40e_aqc_vsi_properties_data\n * as the indirect buffer (128 bytes)\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h\nindex 815e481..aad8d62 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h\n@@ -146,6 +146,8 @@ enum i40e_admin_queue_opc {\n \ti40e_aqc_opc_set_port_parameters\t= 0x0203,\n \ti40e_aqc_opc_get_switch_resource_alloc\t= 0x0204,\n \ti40e_aqc_opc_set_switch_config\t\t= 0x0205,\n+\ti40e_aqc_opc_rx_ctl_reg_read\t\t= 0x0206,\n+\ti40e_aqc_opc_rx_ctl_reg_write\t\t= 0x0207,\n \n \ti40e_aqc_opc_add_vsi\t\t\t= 0x0210,\n \ti40e_aqc_opc_update_vsi_parameters\t= 0x0211,\n@@ -693,6 +695,20 @@ struct i40e_aqc_set_switch_config {\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);\n \n+/* Read Receive control registers (direct 0x0206)\n+ * Write Receive control registers (direct 0x0207)\n+ * used for accessing Rx control registers that can be\n+ * slow and need special handling when under high Rx load\n+ */\n+struct i40e_aqc_rx_ctl_reg_read_write {\n+\t__le32 reserved1;\n+\t__le32 address;\n+\t__le32 reserved2;\n+\t__le32 value;\n+};\n+\n+I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);\n+\n /* Add VSI (indirect 0x0210)\n * this indirect command uses struct i40e_aqc_vsi_properties_data\n * as the indirect buffer (128 bytes)\n", "prefixes": [ "next", "S29", "09/14" ] }