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GET /api/patches/584392/?format=api
{ "id": 584392, "url": "http://patchwork.ozlabs.org/api/patches/584392/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1455754344-6372-11-git-send-email-avinash.dayanand@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1455754344-6372-11-git-send-email-avinash.dayanand@intel.com>", "list_archive_url": null, "date": "2016-02-18T00:12:20", "name": "[next,S29,10/14] i40e: implement and use rx ctl helper functions", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "a331998b7b9c1d93be5100dced43451aaddeb4c8", "submitter": { "id": 67689, "url": "http://patchwork.ozlabs.org/api/people/67689/?format=api", "name": "Dayanand, Avinash", "email": "avinash.dayanand@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1455754344-6372-11-git-send-email-avinash.dayanand@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/584392/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/584392/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ozlabs.org (Postfix) with ESMTP id C9E7B14018C\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 18 Feb 2016 11:12:33 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 2757C93609;\n\tThu, 18 Feb 2016 00:12:33 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id GriX48uGASUw; Thu, 18 Feb 2016 00:12:30 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 33FEA94B7C;\n\tThu, 18 Feb 2016 00:12:29 +0000 (UTC)", "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id 5D7541C0BC2\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 18 Feb 2016 00:12:27 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 588DBA5BCC\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 18 Feb 2016 00:12:27 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id PyKaBk80ieuV for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 18 Feb 2016 00:12:26 +0000 (UTC)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 76C20A5C61\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 18 Feb 2016 00:12:26 +0000 (UTC)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga103.fm.intel.com with ESMTP; 17 Feb 2016 16:12:27 -0800", "from jahay1-mobl2.amr.corp.intel.com (HELO\n\tlocalhost.localdomain.localdomain) ([134.134.3.116])\n\tby fmsmga002.fm.intel.com with ESMTP; 17 Feb 2016 16:12:25 -0800" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.22,463,1449561600\"; d=\"scan'208\";a=\"918067186\"", "From": "Avinash Dayanand <avinash.dayanand@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Wed, 17 Feb 2016 16:12:20 -0800", "Message-Id": "<1455754344-6372-11-git-send-email-avinash.dayanand@intel.com>", "X-Mailer": "git-send-email 2.1.0", "In-Reply-To": "<1455754344-6372-1-git-send-email-avinash.dayanand@intel.com>", "References": "<1455754344-6372-1-git-send-email-avinash.dayanand@intel.com>", "Subject": "[Intel-wired-lan] [next PATCH S29 10/14] i40e: implement and use rx\n\tctl helper functions", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "From: Shannon Nelson <shannon.nelson@intel.com>\n\nUse the new AdminQ functions for safely accessing the Rx control\nregisters that may be affected by heavy small packet traffic.\n\nSigned-off-by: Shannon Nelson <shannon.nelson@intel.com>\nChange-ID: Ibb00983e8dcba71f4b760222a609a5fcaa726f18\n---\n drivers/net/ethernet/intel/i40e/i40e_common.c | 128 ++++++++++++++++++++-\n drivers/net/ethernet/intel/i40e/i40e_prototype.h | 8 ++\n drivers/net/ethernet/intel/i40evf/i40e_common.c | 125 ++++++++++++++++++++\n drivers/net/ethernet/intel/i40evf/i40e_prototype.h | 8 ++\n 4 files changed, 266 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c\nindex 3a57e59..74d9599 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_common.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_common.c\n@@ -1328,7 +1328,7 @@ void i40e_clear_hw(struct i40e_hw *hw)\n \tnum_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>\n \t\t I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;\n \n-\tval = rd32(hw, I40E_PFLAN_QALLOC);\n+\tval = i40e_read_rx_ctl(hw, I40E_PFLAN_QALLOC);\n \tbase_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>\n \t\t I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;\n \tj = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>\n@@ -3882,7 +3882,7 @@ i40e_status i40e_set_filter_control(struct i40e_hw *hw,\n \t\treturn ret;\n \n \t/* Read the PF Queue Filter control register */\n-\tval = rd32(hw, I40E_PFQF_CTL_0);\n+\tval = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);\n \n \t/* Program required PE hash buckets for the PF */\n \tval &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;\n@@ -3919,7 +3919,7 @@ i40e_status i40e_set_filter_control(struct i40e_hw *hw,\n \tif (settings->enable_macvlan)\n \t\tval |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;\n \n-\twr32(hw, I40E_PFQF_CTL_0, val);\n+\ti40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);\n \n \treturn 0;\n }\n@@ -4575,3 +4575,125 @@ restore_config:\n \t\t\t\t\t phy_addr, led_ctl);\n \treturn status;\n }\n+\n+/**\n+ * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register\n+ * @hw: pointer to the hw struct\n+ * @reg_addr: register address\n+ * @reg_val: ptr to register value\n+ * @cmd_details: pointer to command details structure or NULL\n+ *\n+ * Use the firmware to read the Rx control register,\n+ * especially useful if the Rx unit is under heavy pressure\n+ **/\n+i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,\n+\t\t\t\tu32 reg_addr, u32 *reg_val,\n+\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n+{\n+\tstruct i40e_aq_desc desc;\n+\tstruct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =\n+\t\t(struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;\n+\ti40e_status status;\n+\n+\tif (!reg_val)\n+\t\treturn I40E_ERR_PARAM;\n+\n+\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);\n+\n+\tcmd_resp->address = cpu_to_le32(reg_addr);\n+\n+\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n+\n+\tif (status == 0)\n+\t\t*reg_val = le32_to_cpu(cmd_resp->value);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * i40e_read_rx_ctl - read from an Rx control register\n+ * @hw: pointer to the hw struct\n+ * @reg_addr: register address\n+ **/\n+u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)\n+{\n+\ti40e_status status = 0;\n+\tbool use_register;\n+\tint retry = 5;\n+\tu32 val = 0;\n+\n+\tuse_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);\n+\tif (!use_register) {\n+do_retry:\n+\t\tstatus = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);\n+\t\tif (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {\n+\t\t\tusleep_range(1000, 2000);\n+\t\t\tretry--;\n+\t\t\tgoto do_retry;\n+\t\t}\n+\t}\n+\n+\t/* if the AQ access failed, try the old-fashioned way */\n+\tif (status || use_register)\n+\t\tval = rd32(hw, reg_addr);\n+\n+\treturn val;\n+}\n+\n+/**\n+ * i40e_aq_rx_ctl_write_register\n+ * @hw: pointer to the hw struct\n+ * @reg_addr: register address\n+ * @reg_val: register value\n+ * @cmd_details: pointer to command details structure or NULL\n+ *\n+ * Use the firmware to write to an Rx control register,\n+ * especially useful if the Rx unit is under heavy pressure\n+ **/\n+i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,\n+\t\t\t\tu32 reg_addr, u32 reg_val,\n+\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n+{\n+\tstruct i40e_aq_desc desc;\n+\tstruct i40e_aqc_rx_ctl_reg_read_write *cmd =\n+\t\t(struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;\n+\ti40e_status status;\n+\n+\ti40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);\n+\n+\tcmd->address = cpu_to_le32(reg_addr);\n+\tcmd->value = cpu_to_le32(reg_val);\n+\n+\tstatus = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * i40e_write_rx_ctl - write to an Rx control register\n+ * @hw: pointer to the hw struct\n+ * @reg_addr: register address\n+ * @reg_val: register value\n+ **/\n+void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)\n+{\n+\ti40e_status status = 0;\n+\tbool use_register;\n+\tint retry = 5;\n+\n+\tuse_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);\n+\tif (!use_register) {\n+do_retry:\n+\t\tstatus = i40e_aq_rx_ctl_write_register(hw, reg_addr,\n+\t\t\t\t\t\t reg_val, NULL);\n+\t\tif (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {\n+\t\t\tusleep_range(1000, 2000);\n+\t\t\tretry--;\n+\t\t\tgoto do_retry;\n+\t\t}\n+\t}\n+\n+\t/* if the AQ access failed, try the old-fashioned way */\n+\tif (status || use_register)\n+\t\twr32(hw, reg_addr, reg_val);\n+}\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_prototype.h b/drivers/net/ethernet/intel/i40e/i40e_prototype.h\nindex ca2f7ac..d51eee5 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_prototype.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_prototype.h\n@@ -342,6 +342,14 @@ i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,\n \t\t\t struct i40e_asq_cmd_details *cmd_details);\n void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,\n \t\t\t\t\t\t u16 vsi_seid);\n+i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,\n+\t\t\t\tu32 reg_addr, u32 *reg_val,\n+\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n+u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr);\n+i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,\n+\t\t\t\tu32 reg_addr, u32 reg_val,\n+\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n+void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);\n i40e_status i40e_read_phy_register(struct i40e_hw *hw, u8 page,\n \t\t\t\t u16 reg, u8 phy_addr, u16 *value);\n i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page,\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_common.c b/drivers/net/ethernet/intel/i40evf/i40e_common.c\nindex 938783e..771ac6a 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_common.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_common.c\n@@ -904,6 +904,131 @@ struct i40e_rx_ptype_decoded i40evf_ptype_lookup[] = {\n };\n \n /**\n+ * i40evf_aq_rx_ctl_read_register - use FW to read from an Rx control register\n+ * @hw: pointer to the hw struct\n+ * @reg_addr: register address\n+ * @reg_val: ptr to register value\n+ * @cmd_details: pointer to command details structure or NULL\n+ *\n+ * Use the firmware to read the Rx control register,\n+ * especially useful if the Rx unit is under heavy pressure\n+ **/\n+i40e_status i40evf_aq_rx_ctl_read_register(struct i40e_hw *hw,\n+\t\t\t\tu32 reg_addr, u32 *reg_val,\n+\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n+{\n+\tstruct i40e_aq_desc desc;\n+\tstruct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =\n+\t\t(struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;\n+\ti40e_status status;\n+\n+\tif (!reg_val)\n+\t\treturn I40E_ERR_PARAM;\n+\n+\ti40evf_fill_default_direct_cmd_desc(&desc,\n+\t\t\t\t\t i40e_aqc_opc_rx_ctl_reg_read);\n+\n+\tcmd_resp->address = cpu_to_le32(reg_addr);\n+\n+\tstatus = i40evf_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n+\n+\tif (status == 0)\n+\t\t*reg_val = le32_to_cpu(cmd_resp->value);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * i40evf_read_rx_ctl - read from an Rx control register\n+ * @hw: pointer to the hw struct\n+ * @reg_addr: register address\n+ **/\n+u32 i40evf_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)\n+{\n+\ti40e_status status = 0;\n+\tbool use_register;\n+\tint retry = 5;\n+\tu32 val = 0;\n+\n+\tuse_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);\n+\tif (!use_register) {\n+do_retry:\n+\t\tstatus = i40evf_aq_rx_ctl_read_register(hw, reg_addr,\n+\t\t\t\t\t\t\t&val, NULL);\n+\t\tif (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {\n+\t\t\tusleep_range(1000, 2000);\n+\t\t\tretry--;\n+\t\t\tgoto do_retry;\n+\t\t}\n+\t}\n+\n+\t/* if the AQ access failed, try the old-fashioned way */\n+\tif (status || use_register)\n+\t\tval = rd32(hw, reg_addr);\n+\n+\treturn val;\n+}\n+\n+/**\n+ * i40evf_aq_rx_ctl_write_register\n+ * @hw: pointer to the hw struct\n+ * @reg_addr: register address\n+ * @reg_val: register value\n+ * @cmd_details: pointer to command details structure or NULL\n+ *\n+ * Use the firmware to write to an Rx control register,\n+ * especially useful if the Rx unit is under heavy pressure\n+ **/\n+i40e_status i40evf_aq_rx_ctl_write_register(struct i40e_hw *hw,\n+\t\t\t\tu32 reg_addr, u32 reg_val,\n+\t\t\t\tstruct i40e_asq_cmd_details *cmd_details)\n+{\n+\tstruct i40e_aq_desc desc;\n+\tstruct i40e_aqc_rx_ctl_reg_read_write *cmd =\n+\t\t(struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;\n+\ti40e_status status;\n+\n+\ti40evf_fill_default_direct_cmd_desc(&desc,\n+\t\t\t\t\t i40e_aqc_opc_rx_ctl_reg_write);\n+\n+\tcmd->address = cpu_to_le32(reg_addr);\n+\tcmd->value = cpu_to_le32(reg_val);\n+\n+\tstatus = i40evf_asq_send_command(hw, &desc, NULL, 0, cmd_details);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * i40evf_write_rx_ctl - write to an Rx control register\n+ * @hw: pointer to the hw struct\n+ * @reg_addr: register address\n+ * @reg_val: register value\n+ **/\n+void i40evf_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)\n+{\n+\ti40e_status status = 0;\n+\tbool use_register;\n+\tint retry = 5;\n+\n+\tuse_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);\n+\tif (!use_register) {\n+do_retry:\n+\t\tstatus = i40evf_aq_rx_ctl_write_register(hw, reg_addr,\n+\t\t\t\t\t\t\t reg_val, NULL);\n+\t\tif (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {\n+\t\t\tusleep_range(1000, 2000);\n+\t\t\tretry--;\n+\t\t\tgoto do_retry;\n+\t\t}\n+\t}\n+\n+\t/* if the AQ access failed, try the old-fashioned way */\n+\tif (status || use_register)\n+\t\twr32(hw, reg_addr, reg_val);\n+}\n+\n+/**\n * i40e_aq_send_msg_to_pf\n * @hw: pointer to the hardware structure\n * @v_opcode: opcodes for VF-PF communication\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_prototype.h b/drivers/net/ethernet/intel/i40evf/i40e_prototype.h\nindex fa34d85..d89d521 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_prototype.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_prototype.h\n@@ -103,6 +103,14 @@ i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,\n \t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,\n \t\t\t\t\t\t u16 vsi_seid);\n+i40e_status i40evf_aq_rx_ctl_read_register(struct i40e_hw *hw,\n+\t\t\t\tu32 reg_addr, u32 *reg_val,\n+\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n+u32 i40evf_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr);\n+i40e_status i40evf_aq_rx_ctl_write_register(struct i40e_hw *hw,\n+\t\t\t\tu32 reg_addr, u32 reg_val,\n+\t\t\t\tstruct i40e_asq_cmd_details *cmd_details);\n+void i40evf_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);\n i40e_status i40e_read_phy_register(struct i40e_hw *hw, u8 page,\n \t\t\t\t u16 reg, u8 phy_addr, u16 *value);\n i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page,\n", "prefixes": [ "next", "S29", "10/14" ] }