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GET /api/patches/584386/?format=api
{ "id": 584386, "url": "http://patchwork.ozlabs.org/api/patches/584386/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1455754344-6372-8-git-send-email-avinash.dayanand@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1455754344-6372-8-git-send-email-avinash.dayanand@intel.com>", "list_archive_url": null, "date": "2016-02-18T00:12:17", "name": "[next,S29,07/14] i40e: Expose some registers to program parser, FD and RSS logic", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "a98a8e9ae94eb7568acb6c0cb9d4765bab2f4824", "submitter": { "id": 67689, "url": "http://patchwork.ozlabs.org/api/people/67689/?format=api", "name": "Dayanand, Avinash", "email": "avinash.dayanand@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1455754344-6372-8-git-send-email-avinash.dayanand@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/584386/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/584386/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ozlabs.org (Postfix) with ESMTP id 2A1ED14018C\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 18 Feb 2016 11:12:30 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 736FE95517;\n\tThu, 18 Feb 2016 00:12:29 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id zcnF-WM8rw2q; Thu, 18 Feb 2016 00:12:28 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id B1F9993609;\n\tThu, 18 Feb 2016 00:12:28 +0000 (UTC)", "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id F31461C0BC2\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 18 Feb 2016 00:12:26 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id EECFCA5D16\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 18 Feb 2016 00:12:26 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id QzK5owWFYXOz for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 18 Feb 2016 00:12:26 +0000 (UTC)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 4E247A5BCC\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 18 Feb 2016 00:12:26 +0000 (UTC)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga103.fm.intel.com with ESMTP; 17 Feb 2016 16:12:26 -0800", "from jahay1-mobl2.amr.corp.intel.com (HELO\n\tlocalhost.localdomain.localdomain) ([134.134.3.116])\n\tby fmsmga002.fm.intel.com with ESMTP; 17 Feb 2016 16:12:25 -0800" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.22,463,1449561600\"; d=\"scan'208\";a=\"918067181\"", "From": "Avinash Dayanand <avinash.dayanand@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Wed, 17 Feb 2016 16:12:17 -0800", "Message-Id": "<1455754344-6372-8-git-send-email-avinash.dayanand@intel.com>", "X-Mailer": "git-send-email 2.1.0", "In-Reply-To": "<1455754344-6372-1-git-send-email-avinash.dayanand@intel.com>", "References": "<1455754344-6372-1-git-send-email-avinash.dayanand@intel.com>", "Subject": "[Intel-wired-lan] [next PATCH S29 07/14] i40e: Expose some\n\tregisters to program parser, FD and RSS logic", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "From: Anjali Singhai Jain <anjali.singhai@intel.com>\n\nThis patch adds 7 new register definitions for programming the\nparser, flow director and RSS blocks in the HW.\n\nSigned-off-by: Anjali Singhai Jain <anjali.singhai@intel.com>\nChange-ID: I31e76673125275f3c69a14c646361919d04dc987\n---\n drivers/net/ethernet/intel/i40e/i40e_register.h | 48 +++++++++++++++++++++++++\n 1 file changed, 48 insertions(+)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_register.h b/drivers/net/ethernet/intel/i40e/i40e_register.h\nindex dc0402f..86ca27f 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_register.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_register.h\n@@ -2045,6 +2045,14 @@\n #define I40E_PRTPM_TLPIC 0x001E43C0 /* Reset: GLOBR */\n #define I40E_PRTPM_TLPIC_ETLPIC_SHIFT 0\n #define I40E_PRTPM_TLPIC_ETLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_TLPIC_ETLPIC_SHIFT)\n+#define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */\n+#define I40E_GL_PRS_FVBM_MAX_INDEX 3\n+#define I40E_GL_PRS_FVBM_FV_BYTE_INDX_SHIFT 0\n+#define I40E_GL_PRS_FVBM_FV_BYTE_INDX_MASK I40E_MASK(0x7F, I40E_GL_PRS_FVBM_FV_BYTE_INDX_SHIFT)\n+#define I40E_GL_PRS_FVBM_RULE_BUS_INDX_SHIFT 8\n+#define I40E_GL_PRS_FVBM_RULE_BUS_INDX_MASK I40E_MASK(0x3F, I40E_GL_PRS_FVBM_RULE_BUS_INDX_SHIFT)\n+#define I40E_GL_PRS_FVBM_MSK_ENA_SHIFT 31\n+#define I40E_GL_PRS_FVBM_MSK_ENA_MASK I40E_MASK(0x1, I40E_GL_PRS_FVBM_MSK_ENA_SHIFT)\n #define I40E_GLRPB_DPSS 0x000AC828 /* Reset: CORER */\n #define I40E_GLRPB_DPSS_DPS_TCN_SHIFT 0\n #define I40E_GLRPB_DPSS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_DPSS_DPS_TCN_SHIFT)\n@@ -2216,6 +2224,14 @@\n #define I40E_PRTQF_FD_FLXINSET_MAX_INDEX 63\n #define I40E_PRTQF_FD_FLXINSET_INSET_SHIFT 0\n #define I40E_PRTQF_FD_FLXINSET_INSET_MASK I40E_MASK(0xFF, I40E_PRTQF_FD_FLXINSET_INSET_SHIFT)\n+#define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */\n+#define I40E_PRTQF_FD_INSET_MAX_INDEX 63\n+#define I40E_PRTQF_FD_INSET_INSET_SHIFT 0\n+#define I40E_PRTQF_FD_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT)\n+#define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */\n+#define I40E_PRTQF_FD_INSET_MAX_INDEX 63\n+#define I40E_PRTQF_FD_INSET_INSET_SHIFT 0\n+#define I40E_PRTQF_FD_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT)\n #define I40E_PRTQF_FD_MSK(_i, _j) (0x00252000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */\n #define I40E_PRTQF_FD_MSK_MAX_INDEX 63\n #define I40E_PRTQF_FD_MSK_MASK_SHIFT 0\n@@ -5155,6 +5171,38 @@\n #define I40E_GLQF_FD_PCTYPES_MAX_INDEX 63\n #define I40E_GLQF_FD_PCTYPES_FD_PCTYPE_SHIFT 0\n #define I40E_GLQF_FD_PCTYPES_FD_PCTYPE_MASK I40E_MASK(0x3F, I40E_GLQF_FD_PCTYPES_FD_PCTYPE_SHIFT)\n+#define I40E_GLQF_FD_MSK(_i, _j) (0x00267200 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */\n+#define I40E_GLQF_FD_MSK_MAX_INDEX 1\n+#define I40E_GLQF_FD_MSK_MASK_SHIFT 0\n+#define I40E_GLQF_FD_MSK_MASK_MASK I40E_MASK(0xFFFF, I40E_GLQF_FD_MSK_MASK_SHIFT)\n+#define I40E_GLQF_FD_MSK_OFFSET_SHIFT 16\n+#define I40E_GLQF_FD_MSK_OFFSET_MASK I40E_MASK(0x3F, I40E_GLQF_FD_MSK_OFFSET_SHIFT)\n+#define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */\n+#define I40E_GLQF_HASH_INSET_MAX_INDEX 1\n+#define I40E_GLQF_HASH_INSET_INSET_SHIFT 0\n+#define I40E_GLQF_HASH_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_HASH_INSET_INSET_SHIFT)\n+#define I40E_GLQF_HASH_MSK(_i, _j) (0x00267A00 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */\n+#define I40E_GLQF_HASH_MSK_MAX_INDEX 1\n+#define I40E_GLQF_HASH_MSK_MASK_SHIFT 0\n+#define I40E_GLQF_HASH_MSK_MASK_MASK I40E_MASK(0xFFFF, I40E_GLQF_HASH_MSK_MASK_SHIFT)\n+#define I40E_GLQF_HASH_MSK_OFFSET_SHIFT 16\n+#define I40E_GLQF_HASH_MSK_OFFSET_MASK I40E_MASK(0x3F, I40E_GLQF_HASH_MSK_OFFSET_SHIFT)\n+#define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4)) /* _i=0...63 */ /* Reset: CORER */\n+#define I40E_GLQF_ORT_MAX_INDEX 63\n+#define I40E_GLQF_ORT_PIT_INDX_SHIFT 0\n+#define I40E_GLQF_ORT_PIT_INDX_MASK I40E_MASK(0x1F, I40E_GLQF_ORT_PIT_INDX_SHIFT)\n+#define I40E_GLQF_ORT_FIELD_CNT_SHIFT 5\n+#define I40E_GLQF_ORT_FIELD_CNT_MASK I40E_MASK(0x3, I40E_GLQF_ORT_FIELD_CNT_SHIFT)\n+#define I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT 7\n+#define I40E_GLQF_ORT_FLX_PAYLOAD_MASK I40E_MASK(0x1, I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT)\n+#define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4)) /* _i=0...23 */ /* Reset: CORER */\n+#define I40E_GLQF_PIT_MAX_INDEX 23\n+#define I40E_GLQF_PIT_SOURCE_OFF_SHIFT 0\n+#define I40E_GLQF_PIT_SOURCE_OFF_MASK I40E_MASK(0x1F, I40E_GLQF_PIT_SOURCE_OFF_SHIFT)\n+#define I40E_GLQF_PIT_FSIZE_SHIFT 5\n+#define I40E_GLQF_PIT_FSIZE_MASK I40E_MASK(0x1F, I40E_GLQF_PIT_FSIZE_SHIFT)\n+#define I40E_GLQF_PIT_DEST_OFF_SHIFT 10\n+#define I40E_GLQF_PIT_DEST_OFF_MASK I40E_MASK(0x3F, I40E_GLQF_PIT_DEST_OFF_SHIFT)\n #define I40E_GLQF_FDEVICTENA(_i) (0x00270384 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */\n #define I40E_GLQF_FDEVICTENA_MAX_INDEX 1\n #define I40E_GLQF_FDEVICTENA_GLQF_FDEVICTENA_SHIFT 0\n", "prefixes": [ "next", "S29", "07/14" ] }