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GET /api/patches/567111/?format=api
{ "id": 567111, "url": "http://patchwork.ozlabs.org/api/patches/567111/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1452687149-11281-10-git-send-email-christopher.s.hall@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1452687149-11281-10-git-send-email-christopher.s.hall@intel.com>", "list_archive_url": null, "date": "2016-01-13T12:12:29", "name": "[v6,9/9] Adds hardware supported cross timestamp", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "75b16e83dc39423ac184369814a6a9abb4624017", "submitter": { "id": 66720, "url": "http://patchwork.ozlabs.org/api/people/66720/?format=api", "name": "Hall, Christopher S", "email": "christopher.s.hall@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1452687149-11281-10-git-send-email-christopher.s.hall@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/567111/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/567111/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ozlabs.org (Postfix) with ESMTP id 5F5EE1402C4\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 14 Jan 2016 06:18:47 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id ADA7D94867;\n\tWed, 13 Jan 2016 19:18:46 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id KunsuwhXVslg; Wed, 13 Jan 2016 19:18:45 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 8AC8B94660;\n\tWed, 13 Jan 2016 19:18:45 +0000 (UTC)", "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\tby ash.osuosl.org (Postfix) with ESMTP id A6E011C0F8E\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 13 Jan 2016 19:18:42 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id D733B8C841\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 13 Jan 2016 19:18:41 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 8liAqkuH0Hzi for <intel-wired-lan@lists.osuosl.org>;\n\tWed, 13 Jan 2016 19:18:41 +0000 (UTC)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 2AE9C8C969\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 13 Jan 2016 19:18:41 +0000 (UTC)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby fmsmga102.fm.intel.com with ESMTP; 13 Jan 2016 11:18:41 -0800", "from foofoo.jf.intel.com (HELO localhost.localdomain)\n\t([134.134.172.151])\n\tby FMSMGA003.fm.intel.com with ESMTP; 13 Jan 2016 11:18:41 -0800" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.22,290,1449561600\"; d=\"scan'208\";a=\"632939126\"", "From": "\"Christopher S. Hall\" <christopher.s.hall@intel.com>", "To": "tglx@linutronix.de, richardcochran@gmail.com, mingo@redhat.com,\n\tjohn.stultz@linaro.org, hpa@zytor.com, jeffrey.t.kirsher@intel.com", "Date": "Wed, 13 Jan 2016 04:12:29 -0800", "Message-Id": "<1452687149-11281-10-git-send-email-christopher.s.hall@intel.com>", "X-Mailer": "git-send-email 2.1.4", "In-Reply-To": "<1452687149-11281-1-git-send-email-christopher.s.hall@intel.com>", "References": "<1452687149-11281-1-git-send-email-christopher.s.hall@intel.com>", "Cc": "\"Christopher S. Hall\" <christopher.s.hall@intel.com>,\n\tkevin.b.stanton@intel.com, netdev@vger.kernel.org, x86@kernel.org,\n\tlinux-kernel@vger.kernel.org, intel-wired-lan@lists.osuosl.org", "Subject": "[Intel-wired-lan] [PATCH v6 9/9] Adds hardware supported cross\n\ttimestamp", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "Modern Intel systems supports cross timestamping of the network device\nclock and Always Running Timer (ART) in hardware. This allows the\ndevice time and system time to be precisely correlated. The timestamp\npair is returned through e1000e_phc_get_syncdevicetime() used by\nget_system_device_crosststamp(). The hardware cross-timestamp result\nis made available to applications through the PTP_SYS_OFFSET_PRECISE\nioctl which calls e1000e_phc_getcrosststamp().\n\nSigned-off-by: Christopher S. Hall <christopher.s.hall@intel.com>\n---\n drivers/net/ethernet/intel/Kconfig | 9 +++\n drivers/net/ethernet/intel/e1000e/defines.h | 5 ++\n drivers/net/ethernet/intel/e1000e/ptp.c | 88 +++++++++++++++++++++++++++++\n drivers/net/ethernet/intel/e1000e/regs.h | 4 ++\n 4 files changed, 106 insertions(+)", "diff": "diff --git a/drivers/net/ethernet/intel/Kconfig b/drivers/net/ethernet/intel/Kconfig\nindex 4163b16..62bbddc 100644\n--- a/drivers/net/ethernet/intel/Kconfig\n+++ b/drivers/net/ethernet/intel/Kconfig\n@@ -83,6 +83,15 @@ config E1000E\n \t To compile this driver as a module, choose M here. The module\n \t will be called e1000e.\n \n+config E1000E_HWTS\n+\tbool \"Support HW cross-timestamp on PCH devices\"\n+\tdefault y\n+\tdepends on E1000E && X86\n+\t---help---\n+\t Say Y to enable hardware supported cross-timestamping on PCH\n+\t devices. The cross-timestamp is available through the PTP clock\n+\t driver precise cross-timestamp ioctl (PTP_SYS_OFFSET_PRECISE).\n+\n config IGB\n \ttristate \"Intel(R) 82575/82576 PCI-Express Gigabit Ethernet support\"\n \tdepends on PCI\ndiff --git a/drivers/net/ethernet/intel/e1000e/defines.h b/drivers/net/ethernet/intel/e1000e/defines.h\nindex 133d407..13cff75 100644\n--- a/drivers/net/ethernet/intel/e1000e/defines.h\n+++ b/drivers/net/ethernet/intel/e1000e/defines.h\n@@ -527,6 +527,11 @@\n #define E1000_RXCW_C 0x20000000 /* Receive config */\n #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */\n \n+/* HH Time Sync */\n+#define E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK\t0x0000F000 /* max delay */\n+#define E1000_TSYNCTXCTL_SYNC_COMP\t\t0x40000000 /* sync complete */\n+#define E1000_TSYNCTXCTL_START_SYNC\t\t0x80000000 /* initiate sync */\n+\n #define E1000_TSYNCTXCTL_VALID\t\t0x00000001 /* Tx timestamp valid */\n #define E1000_TSYNCTXCTL_ENABLED\t0x00000010 /* enable Tx timestamping */\n \ndiff --git a/drivers/net/ethernet/intel/e1000e/ptp.c b/drivers/net/ethernet/intel/e1000e/ptp.c\nindex 25a0ad5..84a53f7 100644\n--- a/drivers/net/ethernet/intel/e1000e/ptp.c\n+++ b/drivers/net/ethernet/intel/e1000e/ptp.c\n@@ -26,6 +26,11 @@\n \n #include \"e1000.h\"\n \n+#ifdef CONFIG_E1000E_HWTS\n+#include <asm/tsc.h>\n+#include <linux/ktime.h>\n+#endif\n+\n /**\n * e1000e_phc_adjfreq - adjust the frequency of the hardware clock\n * @ptp: ptp clock structure\n@@ -98,6 +103,82 @@ static int e1000e_phc_adjtime(struct ptp_clock_info *ptp, s64 delta)\n \treturn 0;\n }\n \n+#ifdef CONFIG_E1000E_HWTS\n+#define MAX_HW_WAIT_COUNT (3)\n+\n+/**\n+ * e1000e_phc_get_syncdevicetime - Callback given to timekeeping code reads system/device registers\n+ * @device: current device time\n+ * @system: system counter value read synchronously with device time\n+ * @ctx: context provided by timekeeping code\n+ *\n+ * Read device and system (ART) clock simultaneously and return the corrected\n+ * clock values in ns.\n+ **/\n+static int e1000e_phc_get_syncdevicetime(ktime_t *device,\n+\t\t\t\t\t struct system_counterval_t *system,\n+\t\t\t\t\t void *ctx)\n+{\n+\tstruct e1000_adapter *adapter = (struct e1000_adapter *)ctx;\n+\tstruct e1000_hw *hw = &adapter->hw;\n+\tunsigned long flags;\n+\tint i;\n+\tu32 tsync_ctrl;\n+\tcycle_t dev_cycles;\n+\n+\ttsync_ctrl = er32(TSYNCTXCTL);\n+\ttsync_ctrl |= E1000_TSYNCTXCTL_START_SYNC |\n+\t\tE1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK;\n+\tew32(TSYNCTXCTL, tsync_ctrl);\n+\tfor (i = 0; i < MAX_HW_WAIT_COUNT; ++i) {\n+\t\tudelay(1);\n+\t\ttsync_ctrl = er32(TSYNCTXCTL);\n+\t\tif (tsync_ctrl & E1000_TSYNCTXCTL_SYNC_COMP)\n+\t\t\tbreak;\n+\t}\n+\n+\tif (i == MAX_HW_WAIT_COUNT)\n+\t\treturn -ETIMEDOUT;\n+\n+\tdev_cycles = er32(SYSSTMPH);\n+\tdev_cycles <<= 32;\n+\tdev_cycles |= er32(SYSSTMPL);\n+\tspin_lock_irqsave(&adapter->systim_lock, flags);\n+\t*device = ns_to_ktime(timecounter_cyc2time(&adapter->tc, dev_cycles));\n+\tspin_unlock_irqrestore(&adapter->systim_lock, flags);\n+\n+\tsystem->cycles = er32(PLTSTMPH);\n+\tsystem->cycles <<= 32;\n+\tsystem->cycles |= er32(PLTSTMPL);\n+\tsystem->cs = art_timestamper.related_cs;\n+\tsystem->cycles = art_timestamper.convert(&art_timestamper,\n+\t\t\t\t\t\t system->cycles);\n+\treturn 0;\n+}\n+\n+/**\n+ * e1000e_phc_getsynctime - Reads the current system/device cross timestamp\n+ * @ptp: ptp clock structure\n+ * @cts: structure containing timestamp\n+ *\n+ * Read device and system (ART) clock simultaneously and return the scaled\n+ * clock values in ns.\n+ **/\n+static int e1000e_phc_getcrosststamp(struct ptp_clock_info *ptp,\n+\t\t\t\t struct system_device_crosststamp *xtstamp)\n+{\n+\tstruct e1000_adapter *adapter = container_of(ptp, struct e1000_adapter,\n+\t\t\t\t\t\t ptp_clock_info);\n+\tstruct sync_device_time_cb sync_devicetime;\n+\tint ret;\n+\n+\tsync_devicetime.get_time = e1000e_phc_get_syncdevicetime;\n+\tsync_devicetime.ctx = adapter;\n+\tret = get_device_system_crosststamp(&sync_devicetime, NULL, xtstamp);\n+\treturn ret;\n+}\n+#endif/*CONFIG_E1000E_HWTS*/\n+\n /**\n * e1000e_phc_gettime - Reads the current time from the hardware clock\n * @ptp: ptp clock structure\n@@ -236,6 +317,13 @@ void e1000e_ptp_init(struct e1000_adapter *adapter)\n \t\tbreak;\n \t}\n \n+#ifdef CONFIG_E1000E_HWTS\n+\t/* CPU must have ART and GBe must be from Sunrise Point or greater */\n+\tif (hw->mac.type >= e1000_pch_spt && boot_cpu_has(X86_FEATURE_ART))\n+\t\tadapter->ptp_clock_info.getcrosststamp =\n+\t\t\te1000e_phc_getcrosststamp;\n+#endif/*CONFIG_E1000E_HWTS*/\n+\n \tINIT_DELAYED_WORK(&adapter->systim_overflow_work,\n \t\t\t e1000e_systim_overflow_work);\n \ndiff --git a/drivers/net/ethernet/intel/e1000e/regs.h b/drivers/net/ethernet/intel/e1000e/regs.h\nindex 1d5e0b7..0cb4d36 100644\n--- a/drivers/net/ethernet/intel/e1000e/regs.h\n+++ b/drivers/net/ethernet/intel/e1000e/regs.h\n@@ -245,6 +245,10 @@\n #define E1000_SYSTIML\t0x0B600\t/* System time register Low - RO */\n #define E1000_SYSTIMH\t0x0B604\t/* System time register High - RO */\n #define E1000_TIMINCA\t0x0B608\t/* Increment attributes register - RW */\n+#define E1000_SYSSTMPL 0x0B648 /* HH Timesync system stamp low register */\n+#define E1000_SYSSTMPH 0x0B64C /* HH Timesync system stamp hi register */\n+#define E1000_PLTSTMPL 0x0B640 /* HH Timesync platform stamp low register */\n+#define E1000_PLTSTMPH 0x0B644 /* HH Timesync platform stamp hi register */\n #define E1000_RXMTRL\t0x0B634\t/* Time sync Rx EtherType and Msg Type - RW */\n #define E1000_RXUDP\t0x0B638\t/* Time Sync Rx UDP Port - RW */\n \n", "prefixes": [ "v6", "9/9" ] }