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GET /api/patches/561/?format=api
{ "id": 561, "url": "http://patchwork.ozlabs.org/api/patches/561/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1221777901-2967-1-git-send-email-galak@kernel.crashing.org/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1221777901-2967-1-git-send-email-galak@kernel.crashing.org>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1221777901-2967-1-git-send-email-galak@kernel.crashing.org/", "date": "2008-09-18T22:44:58", "name": "[v8,1/4] powerpc: Introduce local (non-broadcast) forms of tlb invalidates", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f5f2c5d66236d6a1b4a1565b94eac9d925954cf0", "submitter": { "id": 5, "url": "http://patchwork.ozlabs.org/api/people/5/?format=api", "name": "Kumar Gala", "email": "galak@kernel.crashing.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1221777901-2967-1-git-send-email-galak@kernel.crashing.org/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/561/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/561/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@ozlabs.org" ], "Received": [ "from ozlabs.org (localhost [127.0.0.1])\n\tby ozlabs.org (Postfix) with ESMTP id 1F8D3DE0D6\n\tfor <patchwork-incoming@ozlabs.org>;\n\tFri, 19 Sep 2008 08:45:38 +1000 (EST)", "from gate.crashing.org (gate.crashing.org [63.228.1.57])\n\t(using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits))\n\t(Client did not present a certificate)\n\tby ozlabs.org (Postfix) with ESMTPS id EECAFDDF19\n\tfor <linuxppc-dev@ozlabs.org>; Fri, 19 Sep 2008 08:45:05 +1000 (EST)", "from localhost (localhost.localdomain [127.0.0.1])\n\tby gate.crashing.org (8.14.1/8.13.8) with ESMTP id m8IMj11Z019844\n\tfor <linuxppc-dev@ozlabs.org>; Thu, 18 Sep 2008 17:45:01 -0500" ], "From": "Kumar Gala <galak@kernel.crashing.org>", "To": "linuxppc-dev@ozlabs.org", "Subject": "[PATCH v8 1/4] powerpc: Introduce local (non-broadcast) forms of tlb\n\tinvalidates", "Date": "Thu, 18 Sep 2008 17:44:58 -0500", "Message-Id": "<1221777901-2967-1-git-send-email-galak@kernel.crashing.org>", "X-Mailer": "git-send-email 1.5.5.1", "X-BeenThere": "linuxppc-dev@ozlabs.org", "X-Mailman-Version": "2.1.11", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List <linuxppc-dev.ozlabs.org>", "List-Unsubscribe": "<https://ozlabs.org/mailman/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://ozlabs.org/pipermail/linuxppc-dev>", "List-Post": "<mailto:linuxppc-dev@ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@ozlabs.org?subject=help>", "List-Subscribe": "<https://ozlabs.org/mailman/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@ozlabs.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org" }, "content": "Introduced a new set of low level tlb invalidate functions that do not\nbroadcast invalidates on the bus:\n\n_tlbil_all - invalidate all\n_tlbil_pid - invalidate based on process id (or mm context)\n_tlbil_va - invalidate based on virtual address (ea + pid)\n\nOn non-SMP configs _tlbil_all should be functionally equivalent to _tlbia and\n_tlbil_va should be functionally equivalent to _tlbie.\n\nThe intent of this change is to handle SMP based invalidates via IPIs instead\nof broadcasts as the mechanism scales better for larger number of cores.\n\nOn e500 (fsl-booke mmu) based cores move to using MMUCSR for invalidate alls\nand tlbsx/tlbwe for invalidate virtual address.\n\nSigned-off-by: Kumar Gala <galak@kernel.crashing.org>", "diff": "diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h\nindex be980f4..6745376 100644\n--- a/arch/powerpc/include/asm/reg_booke.h\n+++ b/arch/powerpc/include/asm/reg_booke.h\n@@ -109,6 +109,7 @@\n #define SPRN_EVPR\t0x3D6\t/* Exception Vector Prefix Register */\n #define SPRN_L1CSR0\t0x3F2\t/* L1 Cache Control and Status Register 0 */\n #define SPRN_L1CSR1\t0x3F3\t/* L1 Cache Control and Status Register 1 */\n+#define SPRN_MMUCSR0\t0x3F4\t/* MMU Control and Status Register 0 */\n #define SPRN_PIT\t0x3DB\t/* Programmable Interval Timer */\n #define SPRN_BUCSR\t0x3F5\t/* Branch Unit Control and Status */\n #define SPRN_L2CSR0\t0x3F9\t/* L2 Data Cache Control and Status Register 0 */\n@@ -410,6 +411,12 @@\n #define L2CSR0_L2LOA\t0x00000080\t/* L2 Cache Lock Overflow Allocate */\n #define L2CSR0_L2LO\t0x00000020\t/* L2 Cache Lock Overflow */\n \n+/* Bit definitions for MMUCSR0 */\n+#define MMUCSR0_TLB1FI\t0x00000002\t/* TLB1 Flash invalidate */\n+#define MMUCSR0_TLB0FI\t0x00000004\t/* TLB0 Flash invalidate */\n+#define MMUCSR0_TLB2FI\t0x00000040\t/* TLB2 Flash invalidate */\n+#define MMUCSR0_TLB3FI\t0x00000020\t/* TLB3 Flash invalidate */\n+\n /* Bit definitions for SGR. */\n #define SGR_NORMAL\t0\t\t/* Speculative fetching allowed. */\n #define SGR_GUARDED\t1\t\t/* Speculative fetching disallowed. */\ndiff --git a/arch/powerpc/include/asm/tlbflush.h b/arch/powerpc/include/asm/tlbflush.h\nindex 361cd5c..a2c6bfd 100644\n--- a/arch/powerpc/include/asm/tlbflush.h\n+++ b/arch/powerpc/include/asm/tlbflush.h\n@@ -29,6 +29,9 @@\n #include <linux/mm.h>\n \n extern void _tlbie(unsigned long address, unsigned int pid);\n+extern void _tlbil_all(void);\n+extern void _tlbil_pid(unsigned int pid);\n+extern void _tlbil_va(unsigned long address, unsigned int pid);\n \n #if defined(CONFIG_40x) || defined(CONFIG_8xx)\n #define _tlbia()\tasm volatile (\"tlbia; sync\" : : : \"memory\")\n@@ -38,31 +41,31 @@ extern void _tlbia(void);\n \n static inline void flush_tlb_mm(struct mm_struct *mm)\n {\n-\t_tlbia();\n+\t_tlbil_pid(mm->context.id);\n }\n \n static inline void flush_tlb_page(struct vm_area_struct *vma,\n \t\t\t\t unsigned long vmaddr)\n {\n-\t_tlbie(vmaddr, vma ? vma->vm_mm->context.id : 0);\n+\t_tlbil_va(vmaddr, vma ? vma->vm_mm->context.id : 0);\n }\n \n static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,\n \t\t\t\t\t unsigned long vmaddr)\n {\n-\t_tlbie(vmaddr, vma ? vma->vm_mm->context.id : 0);\n+\tflush_tlb_page(vma, vmaddr);\n }\n \n static inline void flush_tlb_range(struct vm_area_struct *vma,\n \t\t\t\t unsigned long start, unsigned long end)\n {\n-\t_tlbia();\n+\t_tlbil_pid(vma->vm_mm->context.id);\n }\n \n static inline void flush_tlb_kernel_range(unsigned long start,\n \t\t\t\t\t unsigned long end)\n {\n-\t_tlbia();\n+\t_tlbil_pid(0);\n }\n \n #elif defined(CONFIG_PPC32)\ndiff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S\nindex 7a6dfbc..e9c8ab6 100644\n--- a/arch/powerpc/kernel/misc_32.S\n+++ b/arch/powerpc/kernel/misc_32.S\n@@ -274,6 +274,10 @@ _GLOBAL(real_writeb)\n /*\n * Flush MMU TLB\n */\n+#ifndef CONFIG_FSL_BOOKE\n+_GLOBAL(_tlbil_all)\n+_GLOBAL(_tlbil_pid)\n+#endif\n _GLOBAL(_tlbia)\n #if defined(CONFIG_40x)\n \tsync\t\t\t/* Flush to memory before changing mapping */\n@@ -344,6 +348,9 @@ _GLOBAL(_tlbia)\n /*\n * Flush MMU TLB for a particular address\n */\n+#ifndef CONFIG_FSL_BOOKE\n+_GLOBAL(_tlbil_va)\n+#endif\n _GLOBAL(_tlbie)\n #if defined(CONFIG_40x)\n \t/* We run the search with interrupts disabled because we have to change\n@@ -436,6 +443,53 @@ _GLOBAL(_tlbie)\n #endif /* ! CONFIG_40x */\n \tblr\n \n+#if defined(CONFIG_FSL_BOOKE)\n+/*\n+ * Flush MMU TLB, but only on the local processor (no broadcast)\n+ */\n+_GLOBAL(_tlbil_all)\n+#define MMUCSR0_TLBFI\t(MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \\\n+\t\t\t MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)\n+\tli\tr3,(MMUCSR0_TLBFI)@l\n+\tmtspr\tSPRN_MMUCSR0, r3\n+1:\n+\tmfspr\tr3,SPRN_MMUCSR0\n+\tandi.\tr3,r3,MMUCSR0_TLBFI@l\n+\tbne\t1b\n+\tblr\n+\n+/*\n+ * Flush MMU TLB for a particular process id, but only on the local processor\n+ * (no broadcast)\n+ */\n+_GLOBAL(_tlbil_pid)\n+/* we currently do an invalidate all since we don't have per pid invalidate */\n+\tli\tr3,(MMUCSR0_TLBFI)@l\n+\tmtspr\tSPRN_MMUCSR0, r3\n+1:\n+\tmfspr\tr3,SPRN_MMUCSR0\n+\tandi.\tr3,r3,MMUCSR0_TLBFI@l\n+\tbne\t1b\n+\tblr\n+\n+/*\n+ * Flush MMU TLB for a particular address, but only on the local processor\n+ * (no broadcast)\n+ */\n+_GLOBAL(_tlbil_va)\n+\tslwi\tr4,r4,16\n+\tmtspr\tSPRN_MAS6,r4\t\t/* assume AS=0 for now */\n+\ttlbsx\t0,r3\n+\tmfspr\tr4,SPRN_MAS1\t\t/* check valid */\n+\tandis.\tr3,r4,MAS1_VALID@h\n+\tbeqlr\n+\trlwinm\tr4,r4,0,1,31\n+\tmtspr\tSPRN_MAS1,r4\n+\ttlbwe\n+\tblr\n+#endif /* CONFIG_FSL_BOOKE */\n+\n+\n /*\n * Flush instruction cache.\n * This is a no-op on the 601.\ndiff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c\nindex e1ea4fe..8edc235 100644\n--- a/arch/powerpc/kernel/ppc_ksyms.c\n+++ b/arch/powerpc/kernel/ppc_ksyms.c\n@@ -119,6 +119,9 @@ EXPORT_SYMBOL(flush_instruction_cache);\n EXPORT_SYMBOL(flush_tlb_kernel_range);\n EXPORT_SYMBOL(flush_tlb_page);\n EXPORT_SYMBOL(_tlbie);\n+#if defined(CONFIG_4xx) || defined(CONFIG_8xx) || defined(CONFIG_FSL_BOOKE)\n+EXPORT_SYMBOL(_tlbil_va);\n+#endif\n #endif\n EXPORT_SYMBOL(__flush_icache_range);\n EXPORT_SYMBOL(flush_dcache_range);\n", "prefixes": [ "v8", "1/4" ] }