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GET /api/patches/540136/?format=api
{ "id": 540136, "url": "http://patchwork.ozlabs.org/api/patches/540136/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/624966880.305749.1446575829241.JavaMail.zimbra@xes-inc.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<624966880.305749.1446575829241.JavaMail.zimbra@xes-inc.com>", "list_archive_url": null, "date": "2015-11-03T18:37:09", "name": "[1/5] igb: Remove GS40G specific defines/functions", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "5d427fbd27d45246940bef73cde3687f30ed3bde", "submitter": { "id": 10211, "url": "http://patchwork.ozlabs.org/api/people/10211/?format=api", "name": "Aaron Sierra", "email": "asierra@xes-inc.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/624966880.305749.1446575829241.JavaMail.zimbra@xes-inc.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/540136/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/540136/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ozlabs.org (Postfix) with ESMTP id 5573B1413DB\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 5 Nov 2015 05:59:30 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id A48DB939B0;\n\tWed, 4 Nov 2015 18:59:29 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id Xyh90vIW9C2Q; Wed, 4 Nov 2015 18:59:27 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 8E4079398D;\n\tWed, 4 Nov 2015 18:59:26 +0000 (UTC)", "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id 10E381C15DE\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 3 Nov 2015 19:34:26 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 0CC2484294\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 3 Nov 2015 19:34:26 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id zDobDcPWm6fw for <intel-wired-lan@lists.osuosl.org>;\n\tTue, 3 Nov 2015 19:34:25 +0000 (UTC)", "from xes-mad.com (xes-mad.com [216.165.139.218])\n\tby fraxinus.osuosl.org (Postfix) with ESMTPS id F36D9842D8\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 3 Nov 2015 19:34:24 +0000 (UTC)", "from zimbra.xes-mad.com (zimbra.xes-mad.com [10.52.0.127])\n\tby xes-mad.com (8.13.8/8.13.8) with ESMTP id tA3Ib9OS028479;\n\tTue, 3 Nov 2015 12:37:09 -0600" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "from auto-whitelisted by SQLgrey-1.7.6", "Date": "Tue, 3 Nov 2015 12:37:09 -0600 (CST)", "From": "Aaron Sierra <asierra@xes-inc.com>", "To": "Jeff Kirsher <jeffrey.t.kirsher@intel.com>,\n\tintel-wired-lan@lists.osuosl.org", "Message-ID": "<624966880.305749.1446575829241.JavaMail.zimbra@xes-inc.com>", "In-Reply-To": "<596383518.303713.1446574778623.JavaMail.zimbra@xes-inc.com>", "MIME-Version": "1.0", "X-Originating-IP": "[10.52.16.65]", "X-Mailer": "Zimbra 8.0.6_GA_5922 (ZimbraWebClient - FF40 (Linux)/8.0.6_GA_5922)", "Thread-Topic": "Remove GS40G specific defines/functions", "Thread-Index": "QFYzfRV8AkJ9PZe+GcRsrka/s9xYOQ==", "X-Mailman-Approved-At": "Wed, 04 Nov 2015 18:59:25 +0000", "Cc": "Joe Schultz <jschultz@xes-inc.com>", "Subject": "[Intel-wired-lan] [PATCH 1/5] igb: Remove GS40G specific\n\tdefines/functions", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "The I210 internal PHY can be accessed just as well with the access\nfunctions shared by 82580, I350, and I354 devices. A side effect of\nrelying on the common functions, is that I210 cable length support\nis folded back into the common case which effectively reverts the\nfollowing commit:\n\n commit 59f301046b276f87483b3afa3201a4273def06a9\n Author: Carolyn Wyborny <carolyn.wyborny@intel.com>\n Date: Wed Oct 10 04:42:59 2012 +0000\n\n igb: Update get cable length function for i210/i211\n\nCc: Carolyn Wyborny <carolyn.wyborny@intel.com>\nSigned-off-by: Aaron Sierra <asierra@xes-inc.com>\n---\n drivers/net/ethernet/intel/igb/e1000_82575.c | 13 ++---\n drivers/net/ethernet/intel/igb/e1000_i210.c | 5 +-\n drivers/net/ethernet/intel/igb/e1000_i210.h | 2 +-\n drivers/net/ethernet/intel/igb/e1000_phy.c | 82 +---------------------------\n drivers/net/ethernet/intel/igb/e1000_phy.h | 15 +----\n 5 files changed, 11 insertions(+), 106 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/igb/e1000_82575.c b/drivers/net/ethernet/intel/igb/e1000_82575.c\nindex 7a73510..299afff 100644\n--- a/drivers/net/ethernet/intel/igb/e1000_82575.c\n+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c\n@@ -45,8 +45,6 @@ static s32 igb_get_cfg_done_82575(struct e1000_hw *);\n static s32 igb_init_hw_82575(struct e1000_hw *);\n static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);\n static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);\n-static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);\n-static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);\n static s32 igb_reset_hw_82575(struct e1000_hw *);\n static s32 igb_reset_hw_82580(struct e1000_hw *);\n static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);\n@@ -205,13 +203,10 @@ static s32 igb_init_phy_params_82575(struct e1000_hw *hw)\n \t\tcase e1000_82580:\n \t\tcase e1000_i350:\n \t\tcase e1000_i354:\n-\t\t\tphy->ops.read_reg = igb_read_phy_reg_82580;\n-\t\t\tphy->ops.write_reg = igb_write_phy_reg_82580;\n-\t\t\tbreak;\n \t\tcase e1000_i210:\n \t\tcase e1000_i211:\n-\t\t\tphy->ops.read_reg = igb_read_phy_reg_gs40g;\n-\t\t\tphy->ops.write_reg = igb_write_phy_reg_gs40g;\n+\t\t\tphy->ops.read_reg = igb_read_phy_reg_82580;\n+\t\t\tphy->ops.write_reg = igb_write_phy_reg_82580;\n \t\t\tbreak;\n \t\tdefault:\n \t\t\tphy->ops.read_reg = igb_read_phy_reg_igp;\n@@ -2145,7 +2140,7 @@ void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)\n * Reads the MDI control register in the PHY at offset and stores the\n * information read to data.\n **/\n-static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)\n+s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)\n {\n \ts32 ret_val;\n \n@@ -2169,7 +2164,7 @@ out:\n *\n * Writes data to MDI control register in the PHY at offset.\n **/\n-static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)\n+s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)\n {\n \ts32 ret_val;\n \ndiff --git a/drivers/net/ethernet/intel/igb/e1000_i210.c b/drivers/net/ethernet/intel/igb/e1000_i210.c\nindex 65d9316..4253f7e 100644\n--- a/drivers/net/ethernet/intel/igb/e1000_i210.c\n+++ b/drivers/net/ethernet/intel/igb/e1000_i210.c\n@@ -861,10 +861,10 @@ s32 igb_pll_workaround_i210(struct e1000_hw *hw)\n \tif (ret_val)\n \t\tnvm_word = E1000_INVM_DEFAULT_AL;\n \ttmp_nvm = nvm_word | E1000_INVM_PLL_WO_VAL;\n+\tigb_write_phy_reg_82580(hw, I347AT4_PAGE_SELECT, E1000_PHY_PLL_FREQ_PAGE);\n \tfor (i = 0; i < E1000_MAX_PLL_TRIES; i++) {\n \t\t/* check current state directly from internal PHY */\n-\t\tigb_read_phy_reg_gs40g(hw, (E1000_PHY_PLL_FREQ_PAGE |\n-\t\t\t\t\t E1000_PHY_PLL_FREQ_REG), &phy_word);\n+\t\tigb_read_phy_reg_82580(hw, E1000_PHY_PLL_FREQ_REG, &phy_word);\n \t\tif ((phy_word & E1000_PHY_PLL_UNCONF)\n \t\t != E1000_PHY_PLL_UNCONF) {\n \t\t\tret_val = 0;\n@@ -896,6 +896,7 @@ s32 igb_pll_workaround_i210(struct e1000_hw *hw)\n \t\t/* restore WUC register */\n \t\twr32(E1000_WUC, wuc);\n \t}\n+\tigb_write_phy_reg_82580(hw, I347AT4_PAGE_SELECT, 0);\n \t/* restore MDICNFG setting */\n \twr32(E1000_MDICNFG, mdicnfg);\n \treturn ret_val;\ndiff --git a/drivers/net/ethernet/intel/igb/e1000_i210.h b/drivers/net/ethernet/intel/igb/e1000_i210.h\nindex 3442b63..8aef787 100644\n--- a/drivers/net/ethernet/intel/igb/e1000_i210.h\n+++ b/drivers/net/ethernet/intel/igb/e1000_i210.h\n@@ -84,7 +84,7 @@ enum E1000_INVM_STRUCTURE_TYPE {\n #define E1000_PCI_PMCSR_D3\t\t0x03\n #define E1000_MAX_PLL_TRIES\t\t5\n #define E1000_PHY_PLL_UNCONF\t\t0xFF\n-#define E1000_PHY_PLL_FREQ_PAGE\t\t0xFC0000\n+#define E1000_PHY_PLL_FREQ_PAGE\t\t0xFC\n #define E1000_PHY_PLL_FREQ_REG\t\t0x000E\n #define E1000_INVM_DEFAULT_AL\t\t0x202F\n #define E1000_INVM_AUTOLOAD\t\t0x0A\ndiff --git a/drivers/net/ethernet/intel/igb/e1000_phy.c b/drivers/net/ethernet/intel/igb/e1000_phy.c\nindex 23ec28f..ec1aea5 100644\n--- a/drivers/net/ethernet/intel/igb/e1000_phy.c\n+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c\n@@ -1719,30 +1719,10 @@ s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw)\n \tu16 phy_data, phy_data2, index, default_page, is_cm;\n \n \tswitch (hw->phy.id) {\n-\tcase I210_I_PHY_ID:\n-\t\t/* Get cable length from PHY Cable Diagnostics Control Reg */\n-\t\tret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +\n-\t\t\t\t\t (I347AT4_PCDL + phy->addr),\n-\t\t\t\t\t &phy_data);\n-\t\tif (ret_val)\n-\t\t\treturn ret_val;\n-\n-\t\t/* Check if the unit of cable length is meters or cm */\n-\t\tret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +\n-\t\t\t\t\t I347AT4_PCDC, &phy_data2);\n-\t\tif (ret_val)\n-\t\t\treturn ret_val;\n-\n-\t\tis_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);\n-\n-\t\t/* Populate the phy structure with cable length in meters */\n-\t\tphy->min_cable_length = phy_data / (is_cm ? 100 : 1);\n-\t\tphy->max_cable_length = phy_data / (is_cm ? 100 : 1);\n-\t\tphy->cable_length = phy_data / (is_cm ? 100 : 1);\n-\t\tbreak;\n \tcase M88E1543_E_PHY_ID:\n \tcase M88E1512_E_PHY_ID:\n \tcase I347AT4_E_PHY_ID:\n+\tcase I210_I_PHY_ID:\n \t\t/* Remember the original page select and set it to 7 */\n \t\tret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,\n \t\t\t\t\t &default_page);\n@@ -2494,66 +2474,6 @@ out:\n }\n \n /**\n- * igb_write_phy_reg_gs40g - Write GS40G PHY register\n- * @hw: pointer to the HW structure\n- * @offset: lower half is register offset to write to\n- * upper half is page to use.\n- * @data: data to write at register offset\n- *\n- * Acquires semaphore, if necessary, then writes the data to PHY register\n- * at the offset. Release any acquired semaphores before exiting.\n- **/\n-s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)\n-{\n-\ts32 ret_val;\n-\tu16 page = offset >> GS40G_PAGE_SHIFT;\n-\n-\toffset = offset & GS40G_OFFSET_MASK;\n-\tret_val = hw->phy.ops.acquire(hw);\n-\tif (ret_val)\n-\t\treturn ret_val;\n-\n-\tret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);\n-\tif (ret_val)\n-\t\tgoto release;\n-\tret_val = igb_write_phy_reg_mdic(hw, offset, data);\n-\n-release:\n-\thw->phy.ops.release(hw);\n-\treturn ret_val;\n-}\n-\n-/**\n- * igb_read_phy_reg_gs40g - Read GS40G PHY register\n- * @hw: pointer to the HW structure\n- * @offset: lower half is register offset to read to\n- * upper half is page to use.\n- * @data: data to read at register offset\n- *\n- * Acquires semaphore, if necessary, then reads the data in the PHY register\n- * at the offset. Release any acquired semaphores before exiting.\n- **/\n-s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)\n-{\n-\ts32 ret_val;\n-\tu16 page = offset >> GS40G_PAGE_SHIFT;\n-\n-\toffset = offset & GS40G_OFFSET_MASK;\n-\tret_val = hw->phy.ops.acquire(hw);\n-\tif (ret_val)\n-\t\treturn ret_val;\n-\n-\tret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);\n-\tif (ret_val)\n-\t\tgoto release;\n-\tret_val = igb_read_phy_reg_mdic(hw, offset, data);\n-\n-release:\n-\thw->phy.ops.release(hw);\n-\treturn ret_val;\n-}\n-\n-/**\n * igb_set_master_slave_mode - Setup PHY for Master/slave mode\n * @hw: pointer to the HW structure\n *\ndiff --git a/drivers/net/ethernet/intel/igb/e1000_phy.h b/drivers/net/ethernet/intel/igb/e1000_phy.h\nindex 24d55ed..581172a 100644\n--- a/drivers/net/ethernet/intel/igb/e1000_phy.h\n+++ b/drivers/net/ethernet/intel/igb/e1000_phy.h\n@@ -71,8 +71,8 @@ s32 igb_copper_link_setup_82580(struct e1000_hw *hw);\n s32 igb_get_phy_info_82580(struct e1000_hw *hw);\n s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw);\n s32 igb_get_cable_length_82580(struct e1000_hw *hw);\n-s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);\n-s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);\n+s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data);\n+s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data);\n s32 igb_check_polarity_m88(struct e1000_hw *hw);\n \n /* IGP01E1000 Specific Registers */\n@@ -143,17 +143,6 @@ s32 igb_check_polarity_m88(struct e1000_hw *hw);\n \n #define E1000_CABLE_LENGTH_UNDEFINED 0xFF\n \n-/* GS40G - I210 PHY defines */\n-#define GS40G_PAGE_SELECT\t\t0x16\n-#define GS40G_PAGE_SHIFT\t\t16\n-#define GS40G_OFFSET_MASK\t\t0xFFFF\n-#define GS40G_PAGE_2\t\t\t0x20000\n-#define GS40G_MAC_REG2\t\t\t0x15\n-#define GS40G_MAC_LB\t\t\t0x4140\n-#define GS40G_MAC_SPEED_1G\t\t0X0006\n-#define GS40G_COPPER_SPEC\t\t0x0010\n-#define GS40G_LINE_LB\t\t\t0x4000\n-\n /* SFP modules ID memory locations */\n #define E1000_SFF_IDENTIFIER_OFFSET\t0x00\n #define E1000_SFF_IDENTIFIER_SFF\t0x02\n", "prefixes": [ "1/5" ] }