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GET /api/patches/536383/?format=api
{ "id": 536383, "url": "http://patchwork.ozlabs.org/api/patches/536383/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1445903081-155893-4-git-send-email-catherine.sullivan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1445903081-155893-4-git-send-email-catherine.sullivan@intel.com>", "list_archive_url": null, "date": "2015-10-26T23:44:29", "name": "[next,S20,03/15] i40e/i40evf: Fix RS bit update in Tx path and disable force WB workaround", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "b747cf7a61626a0052ed9269d6dbe354ce800c9b", "submitter": { "id": 13931, "url": "http://patchwork.ozlabs.org/api/people/13931/?format=api", "name": "Catherine Sullivan", "email": "catherine.sullivan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1445903081-155893-4-git-send-email-catherine.sullivan@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/536383/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/536383/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ozlabs.org (Postfix) with ESMTP id A683514030E\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 27 Oct 2015 10:45:40 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id E8FDC329CA;\n\tMon, 26 Oct 2015 23:45:39 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id bMAjB0EIDAr5; Mon, 26 Oct 2015 23:45:34 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby silver.osuosl.org (Postfix) with ESMTP id 40B5E26F27;\n\tMon, 26 Oct 2015 23:45:34 +0000 (UTC)", "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id 3BD291CEEC7\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 26 Oct 2015 23:45:32 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 35BBD87287\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 26 Oct 2015 23:45:32 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id xic-CWBm5Jsl for <intel-wired-lan@lists.osuosl.org>;\n\tMon, 26 Oct 2015 23:45:31 +0000 (UTC)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 9EECF87354\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 26 Oct 2015 23:45:31 +0000 (UTC)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby orsmga102.jf.intel.com with ESMTP; 26 Oct 2015 16:45:31 -0700", "from catheri1-tigger.jf.intel.com ([134.134.176.92])\n\tby FMSMGA003.fm.intel.com with ESMTP; 26 Oct 2015 16:45:32 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.20,202,1444719600\"; d=\"scan'208\";a=\"588532620\"", "From": "Catherine Sullivan <catherine.sullivan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Mon, 26 Oct 2015 19:44:29 -0400", "Message-Id": "<1445903081-155893-4-git-send-email-catherine.sullivan@intel.com>", "X-Mailer": "git-send-email 1.9.3", "In-Reply-To": "<1445903081-155893-1-git-send-email-catherine.sullivan@intel.com>", "References": "<1445903081-155893-1-git-send-email-catherine.sullivan@intel.com>", "Subject": "[Intel-wired-lan] [next PATCH S20 03/15] i40e/i40evf: Fix RS bit\n\tupdate in Tx path and disable force WB workaround", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "From: Anjali Singhai Jain <anjali.singhai@intel.com>\n\nThis patch fixes the issue of forcing WB too often causing us to not\nbenefit from NAPI.\n\nWithout this patch we were forcing WB/arming interrupt too often taking\naway the benefits of NAPI and causing a performance impact.\n\nWith this patch we disable force WB in the clean routine for X710\nand XL710 adapters. X722 adapters do not enable interrupt to force\na WB and benefit from WB_ON_ITR and hence force WB is left enabled\nfor those adapters.\nFor XL710 and X710 adapters if we have less than 4 packets pending\na software Interrupt triggered from service task will force a WB.\n\nThis patch also changes the conditions for setting RS bit as described\nin code comments. This optimizes when the HW does a tail bump amd when\nit does a WB. It also optimizes when we do a wmb.\n\nSigned-off-by: Anjali Singhai Jain <anjali.singhai@intel.com>\nChange-ID: Id831e1ae7d3e2ec3f52cd0917b41ce1d22d75d9d\n\n---\nTesting-hints: Test with heavy receive side traffic and you should see a\nlower interrupt rate, lower CPU utilization, lower packet latency, and\nhigher transmit throughput.\n drivers/net/ethernet/intel/i40evf/i40e_txrx.c | 118 ++++++++++++++++----------\n drivers/net/ethernet/intel/i40evf/i40e_txrx.h | 2 +\n 2 files changed, 77 insertions(+), 43 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\nindex f82c64a..a7f9840 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\n@@ -245,16 +245,6 @@ static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)\n \ttx_ring->q_vector->tx.total_bytes += total_bytes;\n \ttx_ring->q_vector->tx.total_packets += total_packets;\n \n-\t/* check to see if there are any non-cache aligned descriptors\n-\t * waiting to be written back, and kick the hardware to force\n-\t * them to be written back in case of napi polling\n-\t */\n-\tif (budget &&\n-\t !((i & WB_STRIDE) == WB_STRIDE) &&\n-\t !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&\n-\t (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))\n-\t\ttx_ring->arm_wb = true;\n-\n \tnetdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,\n \t\t\t\t\t\t tx_ring->queue_index),\n \t\t\t\t total_packets, total_bytes);\n@@ -1771,6 +1761,9 @@ static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,\n \tu32 td_tag = 0;\n \tdma_addr_t dma;\n \tu16 gso_segs;\n+\tu16 desc_count = 0;\n+\tbool tail_bump = true;\n+\tbool do_rs = false;\n \n \tif (tx_flags & I40E_TX_FLAGS_HW_VLAN) {\n \t\ttd_cmd |= I40E_TX_DESC_CMD_IL2TAG1;\n@@ -1811,6 +1804,8 @@ static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,\n \n \t\t\ttx_desc++;\n \t\t\ti++;\n+\t\t\tdesc_count++;\n+\n \t\t\tif (i == tx_ring->count) {\n \t\t\t\ttx_desc = I40E_TX_DESC(tx_ring, 0);\n \t\t\t\ti = 0;\n@@ -1830,6 +1825,8 @@ static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,\n \n \t\ttx_desc++;\n \t\ti++;\n+\t\tdesc_count++;\n+\n \t\tif (i == tx_ring->count) {\n \t\t\ttx_desc = I40E_TX_DESC(tx_ring, 0);\n \t\t\ti = 0;\n@@ -1844,35 +1841,7 @@ static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,\n \t\ttx_bi = &tx_ring->tx_bi[i];\n \t}\n \n-\t/* Place RS bit on last descriptor of any packet that spans across the\n-\t * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.\n-\t */\n #define WB_STRIDE 0x3\n-\tif (((i & WB_STRIDE) != WB_STRIDE) &&\n-\t (first <= &tx_ring->tx_bi[i]) &&\n-\t (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) {\n-\t\ttx_desc->cmd_type_offset_bsz =\n-\t\t\tbuild_ctob(td_cmd, td_offset, size, td_tag) |\n-\t\t\tcpu_to_le64((u64)I40E_TX_DESC_CMD_EOP <<\n-\t\t\t\t\t I40E_TXD_QW1_CMD_SHIFT);\n-\t} else {\n-\t\ttx_desc->cmd_type_offset_bsz =\n-\t\t\tbuild_ctob(td_cmd, td_offset, size, td_tag) |\n-\t\t\tcpu_to_le64((u64)I40E_TXD_CMD <<\n-\t\t\t\t\t I40E_TXD_QW1_CMD_SHIFT);\n-\t}\n-\n-\tnetdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,\n-\t\t\t\t\t\t tx_ring->queue_index),\n-\t\t\t first->bytecount);\n-\n-\t/* Force memory writes to complete before letting h/w\n-\t * know there are new descriptors to fetch. (Only\n-\t * applicable for weak-ordered memory model archs,\n-\t * such as IA-64).\n-\t */\n-\twmb();\n-\n \t/* set next_to_watch value indicating a packet is present */\n \tfirst->next_to_watch = tx_desc;\n \n@@ -1882,15 +1851,78 @@ static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,\n \n \ttx_ring->next_to_use = i;\n \n+\tnetdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,\n+\t\t\t\t\t\t tx_ring->queue_index),\n+\t\t\t\t\t\t first->bytecount);\n \ti40evf_maybe_stop_tx(tx_ring, DESC_NEEDED);\n+\n+\t/* Algorithm to optimize tail and RS bit setting:\n+\t * if xmit_more is supported\n+\t *\tif xmit_more is true\n+\t *\t\tdo not update tail and do not mark RS bit.\n+\t *\tif xmit_more is false and last xmit_more was false\n+\t *\t\tif every packet spanned less than 4 desc\n+\t *\t\t\tthen set RS bit on 4th packet and update tail\n+\t *\t\t\ton every packet\n+\t *\t\telse\n+\t *\t\t\tupdate tail and set RS bit on every packet.\n+\t *\tif xmit_more is false and last_xmit_more was true\n+\t *\t\tupdate tail and set RS bit.\n+\t * else (kernel < 3.18)\n+\t *\tif every packet spanned less than 4 desc\n+\t *\t\tthen set RS bit on 4th packet and update tail\n+\t *\t\ton every packet\n+\t *\telse\n+\t *\t\tset RS bit on EOP for every packet and update tail\n+\t *\n+\t * Optimization: wmb to be issued only in case of tail update.\n+\t * Also optimize the Descriptor WB path for RS bit with the same\n+\t * algorithm.\n+\t *\n+\t * Note: If there are less than 4 packets\n+\t * pending and interrupts were disabled the service task will\n+\t * trigger a force WB.\n+\t */\n+\tif (skb->xmit_more &&\n+\t !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,\n+\t\t\t\t\t\t tx_ring->queue_index))) {\n+\t\ttx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;\n+\t\ttail_bump = false;\n+\t} else if (!skb->xmit_more &&\n+\t\t !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,\n+\t\t\t\t\t\t tx_ring->queue_index)) &&\n+\t\t (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) &&\n+\t\t (tx_ring->packet_stride < WB_STRIDE) &&\n+\t\t (desc_count < WB_STRIDE)) {\n+\t\ttx_ring->packet_stride++;\n+\t} else {\n+\t\ttx_ring->packet_stride = 0;\n+\t\ttx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;\n+\t\tdo_rs = true;\n+\t}\n+\tif (do_rs)\n+\t\ttx_ring->packet_stride = 0;\n+\n+\ttx_desc->cmd_type_offset_bsz =\n+\t\t\tbuild_ctob(td_cmd, td_offset, size, td_tag) |\n+\t\t\tcpu_to_le64((u64)(do_rs ? I40E_TXD_CMD :\n+\t\t\t\t\t\t I40E_TX_DESC_CMD_EOP) <<\n+\t\t\t\t\t\t I40E_TXD_QW1_CMD_SHIFT);\n+\n \t/* notify HW of packet */\n-\tif (!skb->xmit_more ||\n-\t netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,\n-\t\t\t\t\t\t tx_ring->queue_index)))\n-\t\twritel(i, tx_ring->tail);\n-\telse\n+\tif (!tail_bump)\n \t\tprefetchw(tx_desc + 1);\n \n+\tif (tail_bump) {\n+\t\t/* Force memory writes to complete before letting h/w\n+\t\t * know there are new descriptors to fetch. (Only\n+\t\t * applicable for weak-ordered memory model archs,\n+\t\t * such as IA-64).\n+\t\t */\n+\t\twmb();\n+\t\twritel(i, tx_ring->tail);\n+\t}\n+\n \treturn;\n \n dma_error:\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.h b/drivers/net/ethernet/intel/i40evf/i40e_txrx.h\nindex 997b374..929ddd9 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_txrx.h\n@@ -268,6 +268,8 @@ struct i40e_ring {\n \n \tbool ring_active;\t\t/* is ring online or not */\n \tbool arm_wb;\t\t/* do something to arm write back */\n+\tu8 packet_stride;\n+#define I40E_TXR_FLAGS_LAST_XMIT_MORE_SET BIT(2)\n \n \tu16 flags;\n #define I40E_TXR_FLAGS_WB_ON_ITR\tBIT(0)\n", "prefixes": [ "next", "S20", "03/15" ] }