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GET /api/patches/523617/?format=api
{ "id": 523617, "url": "http://patchwork.ozlabs.org/api/patches/523617/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/5609B886.6050306@gmail.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<5609B886.6050306@gmail.com>", "list_archive_url": null, "date": "2015-09-28T22:00:38", "name": "e1000_hw.c_Elementary checkpatch warnings and checks removed", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "279cc70255fd7f97ad3d03d0f292e2803a464cd6", "submitter": { "id": 67266, "url": "http://patchwork.ozlabs.org/api/people/67266/?format=api", "name": "Janusz Wolak", "email": "januszvdm@gmail.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/5609B886.6050306@gmail.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/523617/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/523617/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ozlabs.org (Postfix) with ESMTP id A0B84140180\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 29 Sep 2015 08:00:57 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id B6354273B6;\n\tMon, 28 Sep 2015 22:00:56 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id dIHFNIns+l-V; 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a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113;\n\th=subject:references:to:from:message-id:date:user-agent:mime-version\n\t:in-reply-to:content-type;\n\tbh=KdbHtkfqCxljTT6yFHiJp0COJA0Ag6KQIpjTO6Ia4n0=;\n\tb=iolYZnOXfiZTAZ9OER31Ki3+kNs+bnM9VRxSaf13vezTa4aNZuK2cpqIf/IaNx3L2A\n\tzCbo5m84YZd/BJ4nFyJNinDOnpXEAvKlgWefqAzR5W5gRQA34smmlAm/MN4JE5VhFWl+\n\tS/mnVkxyNfJRsp6rs+vv2A0II3nwr4Yk4IznH6GX7SdlUf+3g8DoRzZ+iTb6oP1Q/oLU\n\trc2T9B4F9tSUF4KbDEMPp9MPtbRxxCd7nQPfiofMy2kapacwsnI+LUIghvBSyjCGWnDd\n\tFaLiilD1UAFqHfiT+SRrDbbkhH/t6HaO4h9o9anezdhBbEYL7RuwLja/Bhi8aY1YtCk1\n\t+MDg==", "X-Received": "by 10.152.5.233 with SMTP id v9mr6301987lav.65.1443477640073;\n\tMon, 28 Sep 2015 15:00:40 -0700 (PDT)", "References": "<5609B848.4020505@gmail.com>", "To": "john.ronciak@intel.com, mitch.a.williams@intel.com,\n\tintel-wired-lan@lists.osuosl.org", "From": "Janusz Wolak <januszvdm@gmail.com>", "X-Forwarded-Message-Id": "<5609B848.4020505@gmail.com>", "Message-ID": "<5609B886.6050306@gmail.com>", "Date": "Tue, 29 Sep 2015 00:00:38 +0200", "User-Agent": "Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101\n\tThunderbird/38.2.0", "MIME-Version": "1.0", "In-Reply-To": "<5609B848.4020505@gmail.com>", "Content-Type": "multipart/mixed;\n\tboundary=\"------------040305040206090903010303\"", "Subject": "[Intel-wired-lan] e1000_hw.c_Elementary checkpatch warnings and\n\tchecks removed", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "", "diff": "From 83ef6e8f4eeaf13dfa100e6e08c12d94931e1f20 Mon Sep 17 00:00:00 2001\nFrom: Janusz Wolak <januszvdm@gmail.com>\nDate: Mon, 28 Sep 2015 23:40:19 +0200\nSubject: [PATCH 2/2] Elementary checkpatch warnings and checks removed.\n\nSigned-off-by: Janusz Wolak <januszvdm@gmail.com>\n---\n drivers/net/ethernet/intel/e1000/e1000_hw.c | 181 ++++++++++++++--------------\n 1 file changed, 90 insertions(+), 91 deletions(-)\n\ndiff --git a/drivers/net/ethernet/intel/e1000/e1000_hw.c b/drivers/net/ethernet/intel/e1000/e1000_hw.c\nindex cc1fe40..fb316a7 100644\n--- a/drivers/net/ethernet/intel/e1000/e1000_hw.c\n+++ b/drivers/net/ethernet/intel/e1000/e1000_hw.c\n@@ -1,5 +1,5 @@\n /*******************************************************************************\n-\n+*\n Intel PRO/1000 Linux driver\n Copyright(c) 1999 - 2006 Intel Corporation.\n \n@@ -624,8 +624,8 @@ s32 e1000_init_hw(struct e1000_hw *hw)\n \t\t/* Workaround for PCI-X problem when BIOS sets MMRBC\n \t\t * incorrectly.\n \t\t */\n-\t\tif (hw->bus_type == e1000_bus_type_pcix\n-\t\t && e1000_pcix_get_mmrbc(hw) > 2048)\n+\t\tif (hw->bus_type == e1000_bus_type_pcix &&\n+\t\t e1000_pcix_get_mmrbc(hw) > 2048)\n \t\t\te1000_pcix_set_mmrbc(hw, 2048);\n \t\tbreak;\n \t}\n@@ -684,9 +684,8 @@ static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)\n \n \tret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,\n \t\t\t\t &eeprom_data);\n-\tif (ret_val) {\n+\tif (ret_val)\n \t\treturn ret_val;\n-\t}\n \n \tif (eeprom_data != EEPROM_RESERVED_WORD) {\n \t\t/* Adjust SERDES output amplitude only. */\n@@ -1074,8 +1073,8 @@ static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)\n \n \tif (hw->mac_type <= e1000_82543 ||\n \t hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||\n-\t hw->mac_type == e1000_82541_rev_2\n-\t || hw->mac_type == e1000_82547_rev_2)\n+\t hw->mac_type == e1000_82541_rev_2 ||\n+\t hw->mac_type == e1000_82547_rev_2)\n \t\thw->phy_reset_disable = false;\n \n \treturn E1000_SUCCESS;\n@@ -1881,10 +1880,11 @@ static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)\n \t\tif (ret_val)\n \t\t\treturn ret_val;\n \n-\t\tif ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543)\n-\t\t && (!hw->autoneg)\n-\t\t && (hw->forced_speed_duplex == e1000_10_full\n-\t\t\t|| hw->forced_speed_duplex == e1000_10_half)) {\n+\t\tif ((hw->mac_type == e1000_82544 ||\n+\t\t hw->mac_type == e1000_82543) &&\n+\t\t (!hw->autoneg) &&\n+\t\t (hw->forced_speed_duplex == e1000_10_full ||\n+\t\t hw->forced_speed_duplex == e1000_10_half)) {\n \t\t\tret_val = e1000_polarity_reversal_workaround(hw);\n \t\t\tif (ret_val)\n \t\t\t\treturn ret_val;\n@@ -2084,11 +2084,12 @@ static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)\n \t * so we had to force link. In this case, we need to force the\n \t * configuration of the MAC to match the \"fc\" parameter.\n \t */\n-\tif (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))\n-\t || ((hw->media_type == e1000_media_type_internal_serdes)\n-\t\t&& (hw->autoneg_failed))\n-\t || ((hw->media_type == e1000_media_type_copper)\n-\t\t&& (!hw->autoneg))) {\n+\tif (((hw->media_type == e1000_media_type_fiber) &&\n+\t (hw->autoneg_failed)) ||\n+\t ((hw->media_type == e1000_media_type_internal_serdes) &&\n+\t (hw->autoneg_failed)) ||\n+\t ((hw->media_type == e1000_media_type_copper) &&\n+\t (!hw->autoneg))) {\n \t\tret_val = e1000_force_mac_fc(hw);\n \t\tif (ret_val) {\n \t\t\te_dbg(\"Error forcing flow control settings\\n\");\n@@ -2458,10 +2459,11 @@ s32 e1000_check_for_link(struct e1000_hw *hw)\n \t\t\t * happen due to the execution of this workaround.\n \t\t\t */\n \n-\t\t\tif ((hw->mac_type == e1000_82544\n-\t\t\t || hw->mac_type == e1000_82543) && (!hw->autoneg)\n-\t\t\t && (hw->forced_speed_duplex == e1000_10_full\n-\t\t\t\t|| hw->forced_speed_duplex == e1000_10_half)) {\n+\t\t\tif ((hw->mac_type == e1000_82544 ||\n+\t\t\t hw->mac_type == e1000_82543) &&\n+\t\t\t (!hw->autoneg) &&\n+\t\t\t (hw->forced_speed_duplex == e1000_10_full ||\n+\t\t\t hw->forced_speed_duplex == e1000_10_half)) {\n \t\t\t\tew32(IMC, 0xffffffff);\n \t\t\t\tret_val =\n \t\t\t\t e1000_polarity_reversal_workaround(hw);\n@@ -2526,8 +2528,10 @@ s32 e1000_check_for_link(struct e1000_hw *hw)\n \t\t */\n \t\tif (hw->tbi_compatibility_en) {\n \t\t\tu16 speed, duplex;\n+\n \t\t\tret_val =\n \t\t\t e1000_get_speed_and_duplex(hw, &speed, &duplex);\n+\n \t\t\tif (ret_val) {\n \t\t\t\te_dbg\n \t\t\t\t (\"Error getting link speed and duplex\\n\");\n@@ -2626,10 +2630,10 @@ s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)\n \t\t\t e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);\n \t\t\tif (ret_val)\n \t\t\t\treturn ret_val;\n-\t\t\tif ((*speed == SPEED_100\n-\t\t\t && !(phy_data & NWAY_LPAR_100TX_FD_CAPS))\n-\t\t\t || (*speed == SPEED_10\n-\t\t\t\t&& !(phy_data & NWAY_LPAR_10T_FD_CAPS)))\n+\t\t\tif ((*speed == SPEED_100 &&\n+\t\t\t !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||\n+\t\t\t (*speed == SPEED_10 &&\n+\t\t\t !(phy_data & NWAY_LPAR_10T_FD_CAPS)))\n \t\t\t\t*duplex = HALF_DUPLEX;\n \t\t}\n \t}\n@@ -2662,9 +2666,9 @@ static s32 e1000_wait_autoneg(struct e1000_hw *hw)\n \t\tret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);\n \t\tif (ret_val)\n \t\t\treturn ret_val;\n-\t\tif (phy_data & MII_SR_AUTONEG_COMPLETE) {\n+\t\tif (phy_data & MII_SR_AUTONEG_COMPLETE)\n \t\t\treturn E1000_SUCCESS;\n-\t\t}\n+\n \t\tmsleep(100);\n \t}\n \treturn E1000_SUCCESS;\n@@ -2801,7 +2805,6 @@ static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)\n \treturn data;\n }\n \n-\n /**\n * e1000_read_phy_reg - read a phy register\n * @hw: Struct containing variables accessed by shared code\n@@ -2820,7 +2823,7 @@ s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)\n \tif ((hw->phy_type == e1000_phy_igp) &&\n \t (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {\n \t\tret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,\n-\t\t\t\t\t\t (u16) reg_addr);\n+\t\t\t\t\t\t (u16)reg_addr);\n \t\tif (ret_val) {\n \t\t\tspin_unlock_irqrestore(&e1000_phy_lock, flags);\n \t\t\treturn ret_val;\n@@ -2879,7 +2882,7 @@ static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,\n \t\t\t\te_dbg(\"MDI Read Error\\n\");\n \t\t\t\treturn -E1000_ERR_PHY;\n \t\t\t}\n-\t\t\t*phy_data = (u16) mdic;\n+\t\t\t*phy_data = (u16)mdic;\n \t\t} else {\n \t\t\tmdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |\n \t\t\t\t(phy_addr << E1000_MDIC_PHY_SHIFT) |\n@@ -2904,7 +2907,7 @@ static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,\n \t\t\t\te_dbg(\"MDI Error\\n\");\n \t\t\t\treturn -E1000_ERR_PHY;\n \t\t\t}\n-\t\t\t*phy_data = (u16) mdic;\n+\t\t\t*phy_data = (u16)mdic;\n \t\t}\n \t} else {\n \t\t/* We must first send a preamble through the MDIO pin to signal\n@@ -2958,7 +2961,7 @@ s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)\n \tif ((hw->phy_type == e1000_phy_igp) &&\n \t (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {\n \t\tret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,\n-\t\t\t\t\t\t (u16) reg_addr);\n+\t\t\t\t\t\t (u16)reg_addr);\n \t\tif (ret_val) {\n \t\t\tspin_unlock_irqrestore(&e1000_phy_lock, flags);\n \t\t\treturn ret_val;\n@@ -2991,7 +2994,7 @@ static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,\n \t\t * the desired data.\n \t\t */\n \t\tif (hw->mac_type == e1000_ce4100) {\n-\t\t\tmdic = (((u32) phy_data) |\n+\t\t\tmdic = (((u32)phy_data) |\n \t\t\t\t(reg_addr << E1000_MDIC_REG_SHIFT) |\n \t\t\t\t(phy_addr << E1000_MDIC_PHY_SHIFT) |\n \t\t\t\t(INTEL_CE_GBE_MDIC_OP_WRITE) |\n@@ -3013,7 +3016,7 @@ static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,\n \t\t\t\treturn -E1000_ERR_PHY;\n \t\t\t}\n \t\t} else {\n-\t\t\tmdic = (((u32) phy_data) |\n+\t\t\tmdic = (((u32)phy_data) |\n \t\t\t\t(reg_addr << E1000_MDIC_REG_SHIFT) |\n \t\t\t\t(phy_addr << E1000_MDIC_PHY_SHIFT) |\n \t\t\t\t(E1000_MDIC_OP_WRITE));\n@@ -3051,7 +3054,7 @@ static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,\n \t\tmdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |\n \t\t\t(PHY_OP_WRITE << 12) | (PHY_SOF << 14));\n \t\tmdic <<= 16;\n-\t\tmdic |= (u32) phy_data;\n+\t\tmdic |= (u32)phy_data;\n \n \t\te1000_shift_out_mdi_bits(hw, mdic, 32);\n \t}\n@@ -3174,14 +3177,14 @@ static s32 e1000_detect_gig_phy(struct e1000_hw *hw)\n \tif (ret_val)\n \t\treturn ret_val;\n \n-\thw->phy_id = (u32) (phy_id_high << 16);\n+\thw->phy_id = (u32)(phy_id_high << 16);\n \tudelay(20);\n \tret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);\n \tif (ret_val)\n \t\treturn ret_val;\n \n-\thw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK);\n-\thw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK;\n+\thw->phy_id |= (u32)(phy_id_low & PHY_REVISION_MASK);\n+\thw->phy_revision = (u32)phy_id_low & ~PHY_REVISION_MASK;\n \n \tswitch (hw->mac_type) {\n \tcase e1000_82543:\n@@ -3399,7 +3402,6 @@ static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,\n \t\tphy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>\n \t\t\t\t SR_1000T_REMOTE_RX_STATUS_SHIFT) ?\n \t\t e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;\n-\n \t}\n \n \treturn E1000_SUCCESS;\n@@ -3609,11 +3611,11 @@ static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)\n \t */\n \tmask = 0x01 << (count - 1);\n \teecd = er32(EECD);\n-\tif (eeprom->type == e1000_eeprom_microwire) {\n+\tif (eeprom->type == e1000_eeprom_microwire)\n \t\teecd &= ~E1000_EECD_DO;\n-\t} else if (eeprom->type == e1000_eeprom_spi) {\n+\telse if (eeprom->type == e1000_eeprom_spi)\n \t\teecd |= E1000_EECD_DO;\n-\t}\n+\n \tdo {\n \t\t/* A \"1\" is shifted out to the EEPROM by setting bit \"DI\" to a\n \t\t * \"1\", and then raising and then lowering the clock (the SK bit\n@@ -3849,7 +3851,7 @@ static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)\n \tdo {\n \t\te1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,\n \t\t\t\t\thw->eeprom.opcode_bits);\n-\t\tspi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8);\n+\t\tspi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8);\n \t\tif (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))\n \t\t\tbreak;\n \n@@ -3880,6 +3882,7 @@ static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)\n s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)\n {\n \ts32 ret;\n+\n \tspin_lock(&e1000_eeprom_lock);\n \tret = e1000_do_read_eeprom(hw, offset, words, data);\n \tspin_unlock(&e1000_eeprom_lock);\n@@ -3905,8 +3908,9 @@ static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,\n \t/* A check for invalid values: offset too large, too many words, and\n \t * not enough words.\n \t */\n-\tif ((offset >= eeprom->word_size)\n-\t || (words > eeprom->word_size - offset) || (words == 0)) {\n+\tif ((offset >= eeprom->word_size) ||\n+\t (words > eeprom->word_size - offset) ||\n+\t (words == 0)) {\n \t\te_dbg(\"\\\"words\\\" parameter out of bounds. Words = %d,\"\n \t\t \"size = %d\\n\", offset, eeprom->word_size);\n \t\treturn -E1000_ERR_EEPROM;\n@@ -3942,7 +3946,7 @@ static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,\n \n \t\t/* Send the READ command (opcode + addr) */\n \t\te1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);\n-\t\te1000_shift_out_ee_bits(hw, (u16) (offset * 2),\n+\t\te1000_shift_out_ee_bits(hw, (u16)(offset * 2),\n \t\t\t\t\teeprom->address_bits);\n \n \t\t/* Read the data. The address of the eeprom internally\n@@ -3962,7 +3966,7 @@ static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,\n \t\t\te1000_shift_out_ee_bits(hw,\n \t\t\t\t\t\tEEPROM_READ_OPCODE_MICROWIRE,\n \t\t\t\t\t\teeprom->opcode_bits);\n-\t\t\te1000_shift_out_ee_bits(hw, (u16) (offset + i),\n+\t\t\te1000_shift_out_ee_bits(hw, (u16)(offset + i),\n \t\t\t\t\t\teeprom->address_bits);\n \n \t\t\t/* Read the data. For microwire, each word requires the\n@@ -4006,7 +4010,7 @@ s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)\n \t\treturn E1000_SUCCESS;\n \n #endif\n-\tif (checksum == (u16) EEPROM_SUM)\n+\tif (checksum == (u16)EEPROM_SUM)\n \t\treturn E1000_SUCCESS;\n \telse {\n \t\te_dbg(\"EEPROM Checksum Invalid\\n\");\n@@ -4033,7 +4037,7 @@ s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)\n \t\t}\n \t\tchecksum += eeprom_data;\n \t}\n-\tchecksum = (u16) EEPROM_SUM - checksum;\n+\tchecksum = (u16)EEPROM_SUM - checksum;\n \tif (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {\n \t\te_dbg(\"EEPROM Write Error\\n\");\n \t\treturn -E1000_ERR_EEPROM;\n@@ -4054,6 +4058,7 @@ s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)\n s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)\n {\n \ts32 ret;\n+\n \tspin_lock(&e1000_eeprom_lock);\n \tret = e1000_do_write_eeprom(hw, offset, words, data);\n \tspin_unlock(&e1000_eeprom_lock);\n@@ -4079,8 +4084,9 @@ static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,\n \t/* A check for invalid values: offset too large, too many words, and\n \t * not enough words.\n \t */\n-\tif ((offset >= eeprom->word_size)\n-\t || (words > eeprom->word_size - offset) || (words == 0)) {\n+\tif ((offset >= eeprom->word_size) ||\n+\t (words > eeprom->word_size - offset) ||\n+\t (words == 0)) {\n \t\te_dbg(\"\\\"words\\\" parameter out of bounds\\n\");\n \t\treturn -E1000_ERR_EEPROM;\n \t}\n@@ -4138,7 +4144,7 @@ static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,\n \t\t/* Send the Write command (8-bit opcode + addr) */\n \t\te1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);\n \n-\t\te1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2),\n+\t\te1000_shift_out_ee_bits(hw, (u16)((offset + widx) * 2),\n \t\t\t\t\teeprom->address_bits);\n \n \t\t/* Send the data */\n@@ -4148,6 +4154,7 @@ static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,\n \t\t */\n \t\twhile (widx < words) {\n \t\t\tu16 word_out = data[widx];\n+\n \t\t\tword_out = (word_out >> 8) | (word_out << 8);\n \t\t\te1000_shift_out_ee_bits(hw, word_out, 16);\n \t\t\twidx++;\n@@ -4189,9 +4196,9 @@ static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,\n \t * EEPROM into write/erase mode.\n \t */\n \te1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,\n-\t\t\t\t(u16) (eeprom->opcode_bits + 2));\n+\t\t\t\t(u16)(eeprom->opcode_bits + 2));\n \n-\te1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));\n+\te1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));\n \n \t/* Prepare the EEPROM */\n \te1000_standby_eeprom(hw);\n@@ -4201,7 +4208,7 @@ static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,\n \t\te1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,\n \t\t\t\t\teeprom->opcode_bits);\n \n-\t\te1000_shift_out_ee_bits(hw, (u16) (offset + words_written),\n+\t\te1000_shift_out_ee_bits(hw, (u16)(offset + words_written),\n \t\t\t\t\teeprom->address_bits);\n \n \t\t/* Send the data */\n@@ -4241,9 +4248,9 @@ static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,\n \t * EEPROM out of write/erase mode.\n \t */\n \te1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,\n-\t\t\t\t(u16) (eeprom->opcode_bits + 2));\n+\t\t\t\t(u16)(eeprom->opcode_bits + 2));\n \n-\te1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));\n+\te1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));\n \n \treturn E1000_SUCCESS;\n }\n@@ -4266,8 +4273,8 @@ s32 e1000_read_mac_addr(struct e1000_hw *hw)\n \t\t\te_dbg(\"EEPROM Read Error\\n\");\n \t\t\treturn -E1000_ERR_EEPROM;\n \t\t}\n-\t\thw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF);\n-\t\thw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8);\n+\t\thw->perm_mac_addr[i] = (u8)(eeprom_data & 0x00FF);\n+\t\thw->perm_mac_addr[i + 1] = (u8)(eeprom_data >> 8);\n \t}\n \n \tswitch (hw->mac_type) {\n@@ -4334,19 +4341,19 @@ u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)\n \t\t */\n \tcase 0:\n \t\t/* [47:36] i.e. 0x563 for above example address */\n-\t\thash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));\n+\t\thash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));\n \t\tbreak;\n \tcase 1:\n \t\t/* [46:35] i.e. 0xAC6 for above example address */\n-\t\thash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));\n+\t\thash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));\n \t\tbreak;\n \tcase 2:\n \t\t/* [45:34] i.e. 0x5D8 for above example address */\n-\t\thash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));\n+\t\thash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));\n \t\tbreak;\n \tcase 3:\n \t\t/* [43:32] i.e. 0x634 for above example address */\n-\t\thash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));\n+\t\thash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));\n \t\tbreak;\n \t}\n \n@@ -4367,9 +4374,9 @@ void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)\n \t/* HW expects these in little endian so we reverse the byte order\n \t * from network order (big endian) to little endian\n \t */\n-\trar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |\n-\t\t ((u32) addr[2] << 16) | ((u32) addr[3] << 24));\n-\trar_high = ((u32) addr[4] | ((u32) addr[5] << 8));\n+\trar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |\n+\t\t ((u32)addr[2] << 16) | ((u32)addr[3] << 24));\n+\trar_high = ((u32)addr[4] | ((u32)addr[5] << 8));\n \n \t/* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx\n \t * unit hang.\n@@ -4543,7 +4550,7 @@ s32 e1000_setup_led(struct e1000_hw *hw)\n \t\tif (ret_val)\n \t\t\treturn ret_val;\n \t\tret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,\n-\t\t\t\t\t (u16) (hw->phy_spd_default &\n+\t\t\t\t\t (u16)(hw->phy_spd_default &\n \t\t\t\t\t\t ~IGP01E1000_GMII_SPD));\n \t\tif (ret_val)\n \t\t\treturn ret_val;\n@@ -4808,7 +4815,7 @@ void e1000_reset_adaptive(struct e1000_hw *hw)\n void e1000_update_adaptive(struct e1000_hw *hw)\n {\n \tif (hw->adaptive_ifs) {\n-\t\tif ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) {\n+\t\tif ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {\n \t\t\tif (hw->tx_packet_delta > MIN_NUM_XMITS) {\n \t\t\t\thw->in_ifs_mode = true;\n \t\t\t\tif (hw->current_ifs_val < hw->ifs_max_val) {\n@@ -4822,8 +4829,8 @@ void e1000_update_adaptive(struct e1000_hw *hw)\n \t\t\t\t}\n \t\t\t}\n \t\t} else {\n-\t\t\tif (hw->in_ifs_mode\n-\t\t\t && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {\n+\t\t\tif (hw->in_ifs_mode &&\n+\t\t\t (hw->tx_packet_delta <= MIN_NUM_XMITS)) {\n \t\t\t\thw->current_ifs_val = 0;\n \t\t\t\thw->in_ifs_mode = false;\n \t\t\t\tew32(AIT, 0);\n@@ -4928,7 +4935,6 @@ static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,\n \n \t/* Use old method for Phy older than IGP */\n \tif (hw->phy_type == e1000_phy_m88) {\n-\n \t\tret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,\n \t\t\t\t\t &phy_data);\n \t\tif (ret_val)\n@@ -4972,7 +4978,6 @@ static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,\n \t\t};\n \t\t/* Read the AGC registers for all channels */\n \t\tfor (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {\n-\n \t\t\tret_val =\n \t\t\t e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);\n \t\t\tif (ret_val)\n@@ -4982,8 +4987,8 @@ static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,\n \n \t\t\t/* Value bound check. */\n \t\t\tif ((cur_agc_value >=\n-\t\t\t IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1)\n-\t\t\t || (cur_agc_value == 0))\n+\t\t\t IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||\n+\t\t\t (cur_agc_value == 0))\n \t\t\t\treturn -E1000_ERR_PHY;\n \n \t\t\tagc_value += cur_agc_value;\n@@ -5060,7 +5065,6 @@ static s32 e1000_check_polarity(struct e1000_hw *hw,\n \t\t */\n \t\tif ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==\n \t\t IGP01E1000_PSSR_SPEED_1000MBPS) {\n-\n \t\t\t/* Read the GIG initialization PCS register (0x00B4) */\n \t\t\tret_val =\n \t\t\t e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,\n@@ -5181,8 +5185,8 @@ static s32 e1000_1000Mb_check_cable_length(struct e1000_hw *hw)\n \t\t\t\thw->ffe_config_state = e1000_ffe_config_active;\n \n \t\t\t\tret_val = e1000_write_phy_reg(hw,\n-\t\t\t\t\t IGP01E1000_PHY_DSP_FFE,\n-\t\t\t\t\t IGP01E1000_PHY_DSP_FFE_CM_CP);\n+\t\t\t\t\t\t\t IGP01E1000_PHY_DSP_FFE,\n+\t\t\t\t\t\t\t IGP01E1000_PHY_DSP_FFE_CM_CP);\n \t\t\t\tif (ret_val)\n \t\t\t\t\treturn ret_val;\n \t\t\t\tbreak;\n@@ -5249,7 +5253,7 @@ static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)\n \t\t\tmsleep(20);\n \n \t\t\tret_val = e1000_write_phy_reg(hw, 0x0000,\n-\t\t\t\t\t\t IGP01E1000_IEEE_FORCE_GIGA);\n+\t\t\t\t\t\t IGP01E1000_IEEE_FORCE_GIGA);\n \t\t\tif (ret_val)\n \t\t\t\treturn ret_val;\n \t\t\tfor (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {\n@@ -5270,7 +5274,7 @@ static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)\n \t\t\t}\n \n \t\t\tret_val = e1000_write_phy_reg(hw, 0x0000,\n-\t\t\t\t\tIGP01E1000_IEEE_RESTART_AUTONEG);\n+\t\t\t\t\t\t IGP01E1000_IEEE_RESTART_AUTONEG);\n \t\t\tif (ret_val)\n \t\t\t\treturn ret_val;\n \n@@ -5305,7 +5309,7 @@ static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)\n \t\t\tmsleep(20);\n \n \t\t\tret_val = e1000_write_phy_reg(hw, 0x0000,\n-\t\t\t\t\t\t IGP01E1000_IEEE_FORCE_GIGA);\n+\t\t\t\t\t\t IGP01E1000_IEEE_FORCE_GIGA);\n \t\t\tif (ret_val)\n \t\t\t\treturn ret_val;\n \t\t\tret_val =\n@@ -5315,7 +5319,7 @@ static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)\n \t\t\t\treturn ret_val;\n \n \t\t\tret_val = e1000_write_phy_reg(hw, 0x0000,\n-\t\t\t\t\tIGP01E1000_IEEE_RESTART_AUTONEG);\n+\t\t\t\t\t\t IGP01E1000_IEEE_RESTART_AUTONEG);\n \t\t\tif (ret_val)\n \t\t\t\treturn ret_val;\n \n@@ -5352,9 +5356,8 @@ static s32 e1000_set_phy_mode(struct e1000_hw *hw)\n \t\tret_val =\n \t\t e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,\n \t\t\t\t &eeprom_data);\n-\t\tif (ret_val) {\n+\t\tif (ret_val)\n \t\t\treturn ret_val;\n-\t\t}\n \n \t\tif ((eeprom_data != EEPROM_RESERVED_WORD) &&\n \t\t (eeprom_data & EEPROM_PHY_CLASS_A)) {\n@@ -5401,8 +5404,8 @@ static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)\n \t * from the lowest speeds starting from 10Mbps. The capability is used\n \t * for Dx transitions and states\n \t */\n-\tif (hw->mac_type == e1000_82541_rev_2\n-\t || hw->mac_type == e1000_82547_rev_2) {\n+\tif (hw->mac_type == e1000_82541_rev_2 ||\n+\t hw->mac_type == e1000_82547_rev_2) {\n \t\tret_val =\n \t\t e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);\n \t\tif (ret_val)\n@@ -5452,11 +5455,9 @@ static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)\n \t\t\tif (ret_val)\n \t\t\t\treturn ret_val;\n \t\t}\n-\t} else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)\n-\t\t || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL)\n-\t\t || (hw->autoneg_advertised ==\n-\t\t AUTONEG_ADVERTISE_10_100_ALL)) {\n-\n+\t} else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||\n+\t\t (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||\n+\t\t (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {\n \t\tif (hw->mac_type == e1000_82541_rev_2 ||\n \t\t hw->mac_type == e1000_82547_rev_2) {\n \t\t\tphy_data |= IGP01E1000_GMII_FLEX_SPD;\n@@ -5480,7 +5481,6 @@ static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)\n \t\t\t\t\tphy_data);\n \t\tif (ret_val)\n \t\t\treturn ret_val;\n-\n \t}\n \treturn E1000_SUCCESS;\n }\n@@ -5548,7 +5548,6 @@ static s32 e1000_set_vco_speed(struct e1000_hw *hw)\n \treturn E1000_SUCCESS;\n }\n \n-\n /**\n * e1000_enable_mng_pass_thru - check for bmc pass through\n * @hw: Struct containing variables accessed by shared code\n-- \n1.9.1\n\n\n\n", "prefixes": [] }