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GET /api/patches/523548/?format=api
{ "id": 523548, "url": "http://patchwork.ozlabs.org/api/patches/523548/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1443464220-148318-3-git-send-email-catherine.sullivan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1443464220-148318-3-git-send-email-catherine.sullivan@intel.com>", "list_archive_url": null, "date": "2015-09-28T18:16:51", "name": "[next,S17,02/11] i40e/i40evf: refactor irq enable function", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "0a2240b1ad70ec7ddbc4d4b23bf6041f0a50ade1", "submitter": { "id": 13931, "url": "http://patchwork.ozlabs.org/api/people/13931/?format=api", "name": "Catherine Sullivan", "email": "catherine.sullivan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1443464220-148318-3-git-send-email-catherine.sullivan@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/523548/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/523548/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\tby ozlabs.org (Postfix) with ESMTP id A52CA1400B7\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 29 Sep 2015 04:17:35 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id D571E921FA;\n\tMon, 28 Sep 2015 18:17:34 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 1TymAawmuOob; Mon, 28 Sep 2015 18:17:31 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 3605A921F3;\n\tMon, 28 Sep 2015 18:17:31 +0000 (UTC)", "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\tby ash.osuosl.org (Postfix) with ESMTP id 20D851C1591\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 28 Sep 2015 18:17:30 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 1D374921DF\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 28 Sep 2015 18:17:30 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id cLUUqMnh5OGD for <intel-wired-lan@lists.osuosl.org>;\n\tMon, 28 Sep 2015 18:17:29 +0000 (UTC)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id EFEDF921E7\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 28 Sep 2015 18:17:28 +0000 (UTC)", "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga101.jf.intel.com with ESMTP; 28 Sep 2015 11:17:03 -0700", "from catheri1-tigger.jf.intel.com ([134.134.176.92])\n\tby orsmga002.jf.intel.com with ESMTP; 28 Sep 2015 11:17:02 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.17,604,1437462000\"; d=\"scan'208\";a=\"814862554\"", "From": "Catherine Sullivan <catherine.sullivan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Mon, 28 Sep 2015 14:16:51 -0400", "Message-Id": "<1443464220-148318-3-git-send-email-catherine.sullivan@intel.com>", "X-Mailer": "git-send-email 1.9.3", "In-Reply-To": "<1443464220-148318-1-git-send-email-catherine.sullivan@intel.com>", "References": "<1443464220-148318-1-git-send-email-catherine.sullivan@intel.com>", "Subject": "[Intel-wired-lan] [next PATCH S17 02/11] i40e/i40evf: refactor irq\n\tenable function", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "From: Jesse Brandeburg <jesse.brandeburg@intel.com>\n\nThis change moves a multi-line register setting into a function\nwhich simplifies reading the flow of the enable function.\n\nThis also fixes a bug where the enable function was enabling\nthe interrupt twice while trying to update the two interrupt\nthrottle rate thresholds for rx and tx.\n\nSigned-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>\nChange-ID: Ie308f9d0d48540204590cb9d7a5a7b1196f959bb\n---\n drivers/net/ethernet/intel/i40e/i40e_txrx.c | 112 +++++++++++++++-----------\n drivers/net/ethernet/intel/i40evf/i40e_txrx.c | 108 ++++++++++++++-----------\n 2 files changed, 128 insertions(+), 92 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c\nindex 8d83af0..c023b12 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c\n@@ -814,6 +814,8 @@ void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)\n * i40e_set_new_dynamic_itr - Find new ITR level\n * @rc: structure containing ring performance data\n *\n+ * Returns true if itr changed, false if not\n+ *\n * Stores a new ITR value based on packets and byte counts during\n * the last interrupt. The advantage of per interrupt computation\n * is faster updates and more accurate ITR for the current traffic\n@@ -822,14 +824,14 @@ void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)\n * testing data as well as attempting to minimize response time\n * while increasing bulk throughput.\n **/\n-static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)\n+static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)\n {\n \tenum i40e_latency_range new_latency_range = rc->latency_range;\n \tu32 new_itr = rc->itr;\n \tint bytes_per_int;\n \n \tif (rc->total_packets == 0 || !rc->itr)\n-\t\treturn;\n+\t\treturn false;\n \n \t/* simple throttlerate management\n \t * 0-10MB/s lowest (100000 ints/s)\n@@ -873,11 +875,15 @@ static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)\n \t\tbreak;\n \t}\n \n-\tif (new_itr != rc->itr)\n-\t\trc->itr = new_itr;\n-\n \trc->total_bytes = 0;\n \trc->total_packets = 0;\n+\n+\tif (new_itr != rc->itr) {\n+\t\trc->itr = new_itr;\n+\t\treturn true;\n+\t}\n+\n+\treturn false;\n }\n \n /**\n@@ -1746,6 +1752,21 @@ static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)\n \treturn total_rx_packets;\n }\n \n+static u32 i40e_buildreg_itr(const int type, const u16 itr)\n+{\n+\tu32 val;\n+\n+\tval = I40E_PFINT_DYN_CTLN_INTENA_MASK |\n+\t I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |\n+\t (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |\n+\t (itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT);\n+\n+\treturn val;\n+}\n+\n+/* a small macro to shorten up some long lines */\n+#define INTREG I40E_PFINT_DYN_CTLN\n+\n /**\n * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt\n * @vsi: the VSI we care about\n@@ -1756,54 +1777,53 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,\n \t\t\t\t\t struct i40e_q_vector *q_vector)\n {\n \tstruct i40e_hw *hw = &vsi->back->hw;\n-\tu16 old_itr;\n+\tbool rx = false, tx = false;\n+\tu32 rxval, txval;\n \tint vector;\n-\tu32 val;\n \n \tvector = (q_vector->v_idx + vsi->base_vector);\n+\n+\trxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);\n+\n \tif (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {\n-\t\told_itr = q_vector->rx.itr;\n-\t\ti40e_set_new_dynamic_itr(&q_vector->rx);\n-\t\tif (old_itr != q_vector->rx.itr) {\n-\t\t\tval = I40E_PFINT_DYN_CTLN_INTENA_MASK |\n-\t\t\tI40E_PFINT_DYN_CTLN_CLEARPBA_MASK |\n-\t\t\t(I40E_RX_ITR <<\n-\t\t\t\tI40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |\n-\t\t\t(q_vector->rx.itr <<\n-\t\t\t\tI40E_PFINT_DYN_CTLN_INTERVAL_SHIFT);\n-\t\t} else {\n-\t\t\tval = I40E_PFINT_DYN_CTLN_INTENA_MASK |\n-\t\t\tI40E_PFINT_DYN_CTLN_CLEARPBA_MASK |\n-\t\t\t(I40E_ITR_NONE <<\n-\t\t\t\tI40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);\n-\t\t}\n-\t\tif (!test_bit(__I40E_DOWN, &vsi->state))\n-\t\t\twr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);\n-\t} else {\n-\t\ti40e_irq_dynamic_enable(vsi, q_vector->v_idx);\n+\t\trx = i40e_set_new_dynamic_itr(&q_vector->rx);\n+\t\trxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);\n \t}\n+\n \tif (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {\n-\t\told_itr = q_vector->tx.itr;\n-\t\ti40e_set_new_dynamic_itr(&q_vector->tx);\n-\t\tif (old_itr != q_vector->tx.itr) {\n-\t\t\tval = I40E_PFINT_DYN_CTLN_INTENA_MASK |\n-\t\t\t\tI40E_PFINT_DYN_CTLN_CLEARPBA_MASK |\n-\t\t\t\t(I40E_TX_ITR <<\n-\t\t\t\t I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |\n-\t\t\t\t(q_vector->tx.itr <<\n-\t\t\t\t I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT);\n-\t\t} else {\n-\t\t\tval = I40E_PFINT_DYN_CTLN_INTENA_MASK |\n-\t\t\t\tI40E_PFINT_DYN_CTLN_CLEARPBA_MASK |\n-\t\t\t\t(I40E_ITR_NONE <<\n-\t\t\t\t I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);\n-\t\t}\n-\t\tif (!test_bit(__I40E_DOWN, &vsi->state))\n-\t\t\twr32(hw, I40E_PFINT_DYN_CTLN(q_vector->v_idx +\n-\t\t\t vsi->base_vector - 1), val);\n-\t} else {\n-\t\ti40e_irq_dynamic_enable(vsi, q_vector->v_idx);\n+\t\ttx = i40e_set_new_dynamic_itr(&q_vector->tx);\n+\t\ttxval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);\n \t}\n+\n+\tif (rx || tx) {\n+\t\t/* get the higher of the two ITR adjustments and\n+\t\t * use the same value for both ITR registers\n+\t\t * when in adaptive mode (rx and/or tx)\n+\t\t */\n+\t\tu16 itr = max(q_vector->tx.itr, q_vector->rx.itr);\n+\n+\t\tq_vector->tx.itr = q_vector->rx.itr = itr;\n+\t\ttxval = i40e_buildreg_itr(I40E_TX_ITR, itr);\n+\t\ttx = true;\n+\t\trxval = i40e_buildreg_itr(I40E_RX_ITR, itr);\n+\t\trx = true;\n+\t}\n+\n+\t/* only need to enable the interrupt once, but need\n+\t * to possibly update both ITR values\n+\t */\n+\tif (rx) {\n+\t\t/* set the INTENA_MSK_MASK so that this first write\n+\t\t * won't actually enable the interrupt, instead just\n+\t\t * updating the ITR (it's bit 31 PF and VF)\n+\t\t */\n+\t\trxval |= BIT(31);\n+\t\t/* don't check _DOWN because interrupt isn't being enabled */\n+\t\twr32(hw, INTREG(vector - 1), rxval);\n+\t}\n+\n+\tif (!test_bit(__I40E_DOWN, &vsi->state))\n+\t\twr32(hw, INTREG(vector - 1), txval);\n }\n \n /**\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\nindex 97493a4..3d2646b 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\n@@ -318,6 +318,8 @@ static void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector\n * i40e_set_new_dynamic_itr - Find new ITR level\n * @rc: structure containing ring performance data\n *\n+ * Returns true if itr changed, false if not\n+ *\n * Stores a new ITR value based on packets and byte counts during\n * the last interrupt. The advantage of per interrupt computation\n * is faster updates and more accurate ITR for the current traffic\n@@ -326,14 +328,14 @@ static void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector\n * testing data as well as attempting to minimize response time\n * while increasing bulk throughput.\n **/\n-static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)\n+static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)\n {\n \tenum i40e_latency_range new_latency_range = rc->latency_range;\n \tu32 new_itr = rc->itr;\n \tint bytes_per_int;\n \n \tif (rc->total_packets == 0 || !rc->itr)\n-\t\treturn;\n+\t\treturn false;\n \n \t/* simple throttlerate management\n \t * 0-10MB/s lowest (100000 ints/s)\n@@ -377,11 +379,15 @@ static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)\n \t\tbreak;\n \t}\n \n-\tif (new_itr != rc->itr)\n-\t\trc->itr = new_itr;\n-\n \trc->total_bytes = 0;\n \trc->total_packets = 0;\n+\n+\tif (new_itr != rc->itr) {\n+\t\trc->itr = new_itr;\n+\t\treturn true;\n+\t}\n+\n+\treturn false;\n }\n \n /*\n@@ -1187,6 +1193,21 @@ static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)\n \treturn total_rx_packets;\n }\n \n+static u32 i40e_buildreg_itr(const int type, const u16 itr)\n+{\n+\tu32 val;\n+\n+\tval = I40E_VFINT_DYN_CTLN1_INTENA_MASK |\n+\t I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |\n+\t (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |\n+\t (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);\n+\n+\treturn val;\n+}\n+\n+/* a small macro to shorten up some long lines */\n+#define INTREG I40E_VFINT_DYN_CTLN1\n+\n /**\n * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt\n * @vsi: the VSI we care about\n@@ -1197,55 +1218,50 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,\n \t\t\t\t\t struct i40e_q_vector *q_vector)\n {\n \tstruct i40e_hw *hw = &vsi->back->hw;\n-\tu16 old_itr;\n+\tbool rx = false, tx = false;\n+\tu32 rxval, txval;\n \tint vector;\n-\tu32 val;\n \n \tvector = (q_vector->v_idx + vsi->base_vector);\n+\trxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);\n+\n \tif (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {\n-\t\told_itr = q_vector->rx.itr;\n-\t\ti40e_set_new_dynamic_itr(&q_vector->rx);\n-\t\tif (old_itr != q_vector->rx.itr) {\n-\t\t\tval = I40E_VFINT_DYN_CTLN1_INTENA_MASK |\n-\t\t\tI40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |\n-\t\t\t(I40E_RX_ITR <<\n-\t\t\t\tI40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |\n-\t\t\t(q_vector->rx.itr <<\n-\t\t\t\tI40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);\n-\t\t} else {\n-\t\t\tval = I40E_VFINT_DYN_CTLN1_INTENA_MASK |\n-\t\t\tI40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |\n-\t\t\t(I40E_ITR_NONE <<\n-\t\t\t\tI40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT);\n-\t\t}\n-\t\tif (!test_bit(__I40E_DOWN, &vsi->state))\n-\t\t\twr32(hw, I40E_VFINT_DYN_CTLN1(vector - 1), val);\n-\t} else {\n-\t\ti40evf_irq_enable_queues(vsi->back, 1\n-\t\t\t<< q_vector->v_idx);\n+\t\trx = i40e_set_new_dynamic_itr(&q_vector->rx);\n+\t\trxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);\n \t}\n \tif (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {\n-\t\told_itr = q_vector->tx.itr;\n-\t\ti40e_set_new_dynamic_itr(&q_vector->tx);\n-\t\tif (old_itr != q_vector->tx.itr) {\n-\t\t\tval = I40E_VFINT_DYN_CTLN1_INTENA_MASK |\n-\t\t\t\tI40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |\n-\t\t\t\t(I40E_TX_ITR <<\n-\t\t\t\t I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |\n-\t\t\t\t(q_vector->tx.itr <<\n-\t\t\t\t I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);\n+\t\ttx = i40e_set_new_dynamic_itr(&q_vector->tx);\n+\t\ttxval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);\n+\t}\n+\tif (rx || tx) {\n+\t\t/* get the higher of the two ITR adjustments and\n+\t\t * use the same value for both ITR registers\n+\t\t * when in adaptive mode (rx and/or tx)\n+\t\t */\n+\t\tu16 itr = max(q_vector->tx.itr, q_vector->rx.itr);\n \n-\t\t} else {\n-\t\t\tval = I40E_VFINT_DYN_CTLN1_INTENA_MASK |\n-\t\t\t\tI40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |\n-\t\t\t\t(I40E_ITR_NONE <<\n-\t\t\t\t I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT);\n-\t\t}\n-\t\tif (!test_bit(__I40E_DOWN, &vsi->state))\n-\t\t\twr32(hw, I40E_VFINT_DYN_CTLN1(vector - 1), val);\n-\t} else {\n-\t\ti40evf_irq_enable_queues(vsi->back, BIT(q_vector->v_idx));\n+\t\tq_vector->tx.itr = q_vector->rx.itr = itr;\n+\t\ttxval = i40e_buildreg_itr(I40E_TX_ITR, itr);\n+\t\ttx = true;\n+\t\trxval = i40e_buildreg_itr(I40E_RX_ITR, itr);\n+\t\trx = true;\n \t}\n+\n+\t/* only need to enable the interrupt once, but need\n+\t * to possibly update both ITR values\n+\t */\n+\tif (rx) {\n+\t\t/* set the INTENA_MSK_MASK so that this first write\n+\t\t * won't actually enable the interrupt, instead just\n+\t\t * updating the ITR (it's bit 31 PF and VF)\n+\t\t */\n+\t\trxval |= BIT(31);\n+\t\t/* don't check _DOWN because interrupt isn't being enabled */\n+\t\twr32(hw, INTREG(vector - 1), rxval);\n+\t}\n+\n+\tif (!test_bit(__I40E_DOWN, &vsi->state))\n+\t\twr32(hw, INTREG(vector - 1), txval);\n }\n \n /**\n", "prefixes": [ "next", "S17", "02/11" ] }