Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/523542/?format=api
{ "id": 523542, "url": "http://patchwork.ozlabs.org/api/patches/523542/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1443463964-148204-9-git-send-email-catherine.sullivan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1443463964-148204-9-git-send-email-catherine.sullivan@intel.com>", "list_archive_url": null, "date": "2015-09-28T18:12:37", "name": "[next,S16,08/15] i40e/i40evf: moderate interrupts differently", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "3ffe17f4b7b0b79851b86ab52e350189d5921191", "submitter": { "id": 13931, "url": "http://patchwork.ozlabs.org/api/people/13931/?format=api", "name": "Catherine Sullivan", "email": "catherine.sullivan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1443463964-148204-9-git-send-email-catherine.sullivan@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/523542/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/523542/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ozlabs.org (Postfix) with ESMTP id 156291400B7\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 29 Sep 2015 04:15:03 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 595BF954CA;\n\tMon, 28 Sep 2015 18:15:02 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id UNCb8IXZqo6C; Mon, 28 Sep 2015 18:15:01 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 366F9954E9;\n\tMon, 28 Sep 2015 18:15:00 +0000 (UTC)", "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ash.osuosl.org (Postfix) with ESMTP id B0D411CE9AE\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 28 Sep 2015 18:14:58 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id A7B873325E\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 28 Sep 2015 18:14:58 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id ZAEM70LvfvPO for <intel-wired-lan@lists.osuosl.org>;\n\tMon, 28 Sep 2015 18:14:54 +0000 (UTC)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby silver.osuosl.org (Postfix) with ESMTP id D3D2C33282\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 28 Sep 2015 18:14:54 +0000 (UTC)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby orsmga101.jf.intel.com with ESMTP; 28 Sep 2015 11:14:27 -0700", "from catheri1-tigger.jf.intel.com ([134.134.176.92])\n\tby FMSMGA003.fm.intel.com with ESMTP; 28 Sep 2015 11:14:27 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.17,603,1437462000\"; d=\"scan'208\";a=\"569972190\"", "From": "Catherine Sullivan <catherine.sullivan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Mon, 28 Sep 2015 14:12:37 -0400", "Message-Id": "<1443463964-148204-9-git-send-email-catherine.sullivan@intel.com>", "X-Mailer": "git-send-email 1.9.3", "In-Reply-To": "<1443463964-148204-1-git-send-email-catherine.sullivan@intel.com>", "References": "<1443463964-148204-1-git-send-email-catherine.sullivan@intel.com>", "Subject": "[Intel-wired-lan] [next PATCH S16 08/15] i40e/i40evf: moderate\n\tinterrupts differently", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "From: Jesse Brandeburg <jesse.brandeburg@intel.com>\n\nThe XL710 hardware has a different interrupt moderation design\nthat can support a limit of total interrupts per second per\nvector, in addition to the \"number of interrupts per second\"\ncontrols already established in the driver. This combination\nof hardware features allows us to set very low default latency\nsettings but minimize the total CPU utilization by not\nmaking too many interrupts, should the user desire.\n\nThe current driver implementation is still enabling the dynamic\nmoderation in the driver, and only using the rx/tx-usecs\nlimit in ethtool to limit the interrupt rate per second, by default.\n\nThe new code implemented in this patch\n2) adds init/use of the new \"Interrupt Limit\" register\n3) adds ethtool knob to control/report the limits above\n\nUsage is ethtool -C ethx rx-usecs-high <value> Where <value> is number\nof microseconds to create a rate of 1/N interrupts per second,\nregardless of rx-usecs or tx-usecs values. Since there is a credit based\nscheme in the hardware, the rx-usecs and tx-usecs can be configured for\nvery low latency for short bursts, but once the credit runs out the\nrefill rate on the credits is limited by rx-usecs-high.\n\nSigned-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>\nChange-ID: I3a1075d3296123b0f4f50623c779b027af5b188d\n---\n drivers/net/ethernet/intel/i40e/i40e.h | 1 +\n drivers/net/ethernet/intel/i40e/i40e_ethtool.c | 24 ++++++++++++++++++++++++\n drivers/net/ethernet/intel/i40e/i40e_main.c | 10 +++++++---\n drivers/net/ethernet/intel/i40e/i40e_txrx.h | 10 ++++++++++\n drivers/net/ethernet/intel/i40evf/i40e_txrx.h | 10 ++++++++++\n 5 files changed, 52 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e.h b/drivers/net/ethernet/intel/i40e/i40e.h\nindex 446d6a8..c714822 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e.h\n@@ -500,6 +500,7 @@ struct i40e_vsi {\n \t */\n \tu16 rx_itr_setting;\n \tu16 tx_itr_setting;\n+\tu16 int_rate_limit; /* value in usecs */\n \n \tu16 rss_table_size;\n \tu16 rss_size;\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c\nindex 21612d9..baec2f8 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c\n@@ -1846,6 +1846,14 @@ static int i40e_get_coalesce(struct net_device *netdev,\n \n \tec->rx_coalesce_usecs = vsi->rx_itr_setting & ~I40E_ITR_DYNAMIC;\n \tec->tx_coalesce_usecs = vsi->tx_itr_setting & ~I40E_ITR_DYNAMIC;\n+\t/* we use the _usecs_high to store/set the interrupt rate limit\n+\t * that the hardware supports, that almost but not quite\n+\t * fits the original intent of the ethtool variable,\n+\t * the rx_coalesce_usecs_high limits total interrupts\n+\t * per second from both tx/rx sources.\n+\t */\n+\tec->rx_coalesce_usecs_high = vsi->int_rate_limit;\n+\tec->tx_coalesce_usecs_high = vsi->int_rate_limit;\n \n \treturn 0;\n }\n@@ -1864,6 +1872,17 @@ static int i40e_set_coalesce(struct net_device *netdev,\n \tif (ec->tx_max_coalesced_frames_irq || ec->rx_max_coalesced_frames_irq)\n \t\tvsi->work_limit = ec->tx_max_coalesced_frames_irq;\n \n+\t/* tx_coalesce_usecs_high is ignored, use rx-usecs-high instead */\n+\tif (ec->tx_coalesce_usecs_high != vsi->int_rate_limit) {\n+\t\tnetif_info(pf, drv, netdev, \"tx-usecs-high is not used, please program rx-usecs-high\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (ec->rx_coalesce_usecs_high >= INTRL_REG_TO_USEC(I40E_MAX_INTRL)) {\n+\t\tnetif_info(pf, drv, netdev, \"Invalid value, rx-usecs-high range is 0-235\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n \tvector = vsi->base_vector;\n \tif ((ec->rx_coalesce_usecs >= (I40E_MIN_ITR << 1)) &&\n \t (ec->rx_coalesce_usecs <= (I40E_MAX_ITR << 1))) {\n@@ -1877,6 +1896,8 @@ static int i40e_set_coalesce(struct net_device *netdev,\n \t\treturn -EINVAL;\n \t}\n \n+\tvsi->int_rate_limit = ec->rx_coalesce_usecs_high;\n+\n \tif ((ec->tx_coalesce_usecs >= (I40E_MIN_ITR << 1)) &&\n \t (ec->tx_coalesce_usecs <= (I40E_MAX_ITR << 1))) {\n \t\tvsi->tx_itr_setting = ec->tx_coalesce_usecs;\n@@ -1901,11 +1922,14 @@ static int i40e_set_coalesce(struct net_device *netdev,\n \t\tvsi->tx_itr_setting &= ~I40E_ITR_DYNAMIC;\n \n \tfor (i = 0; i < vsi->num_q_vectors; i++, vector++) {\n+\t\tu16 intrl = INTRL_USEC_TO_REG(vsi->int_rate_limit);\n+\n \t\tq_vector = vsi->q_vectors[i];\n \t\tq_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);\n \t\twr32(hw, I40E_PFINT_ITRN(0, vector - 1), q_vector->rx.itr);\n \t\tq_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);\n \t\twr32(hw, I40E_PFINT_ITRN(1, vector - 1), q_vector->tx.itr);\n+\t\twr32(hw, I40E_PFINT_RATEN(vector - 1), intrl);\n \t\ti40e_flush(hw);\n \t}\n \ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c\nindex d656182..7989c2e 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_main.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_main.c\n@@ -3087,11 +3087,9 @@ static int i40e_vsi_configure(struct i40e_vsi *vsi)\n static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)\n {\n \tstruct i40e_pf *pf = vsi->back;\n-\tstruct i40e_q_vector *q_vector;\n \tstruct i40e_hw *hw = &pf->hw;\n \tu16 vector;\n \tint i, q;\n-\tu32 val;\n \tu32 qp;\n \n \t/* The interrupt indexing is offset by 1 in the PFINT_ITRn\n@@ -3101,7 +3099,8 @@ static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)\n \tqp = vsi->base_queue;\n \tvector = vsi->base_vector;\n \tfor (i = 0; i < vsi->num_q_vectors; i++, vector++) {\n-\t\tq_vector = vsi->q_vectors[i];\n+\t\tstruct i40e_q_vector *q_vector = vsi->q_vectors[i];\n+\n \t\tq_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);\n \t\tq_vector->rx.latency_range = I40E_LOW_LATENCY;\n \t\twr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),\n@@ -3110,10 +3109,14 @@ static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)\n \t\tq_vector->tx.latency_range = I40E_LOW_LATENCY;\n \t\twr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),\n \t\t q_vector->tx.itr);\n+\t\twr32(hw, I40E_PFINT_RATEN(vector - 1),\n+\t\t INTRL_USEC_TO_REG(vsi->int_rate_limit));\n \n \t\t/* Linked list for the queuepairs assigned to this vector */\n \t\twr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);\n \t\tfor (q = 0; q < q_vector->num_ringpairs; q++) {\n+\t\t\tu32 val;\n+\n \t\t\tval = I40E_QINT_RQCTL_CAUSE_ENA_MASK |\n \t\t\t (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |\n \t\t\t (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |\n@@ -7226,6 +7229,7 @@ static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)\n \tvsi->idx = vsi_idx;\n \tvsi->rx_itr_setting = pf->rx_itr_default;\n \tvsi->tx_itr_setting = pf->tx_itr_default;\n+\tvsi->int_rate_limit = 0;\n \tvsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?\n \t\t\t\tpf->rss_table_size : 64;\n \tvsi->netdev_registered = false;\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.h b/drivers/net/ethernet/intel/i40e/i40e_txrx.h\nindex 75cecfa..7c0ed84 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_txrx.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.h\n@@ -35,6 +35,7 @@\n #define I40E_ITR_20K 0x0019\n #define I40E_ITR_8K 0x003E\n #define I40E_ITR_4K 0x007A\n+#define I40E_MAX_INTRL 0x3B /* reg uses 4 usec resolution */\n #define I40E_ITR_RX_DEF I40E_ITR_8K\n #define I40E_ITR_TX_DEF I40E_ITR_4K\n #define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */\n@@ -44,6 +45,15 @@\n #define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1)\n #define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC))\n #define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1)\n+/* 0x40 is the enable bit for interrupt rate limiting, and must be set if\n+ * the value of the rate limit is non-zero\n+ */\n+#define INTRL_ENA BIT(6)\n+#define INTRL_REG_TO_USEC(intrl) ((intrl & ~INTRL_ENA) << 2)\n+#define INTRL_USEC_TO_REG(set) ((set) ? ((set) >> 2) | INTRL_ENA : 0)\n+#define I40E_INTRL_8K 125 /* 8000 ints/sec */\n+#define I40E_INTRL_62K 16 /* 62500 ints/sec */\n+#define I40E_INTRL_83K 12 /* 83333 ints/sec */\n \n #define I40E_QUEUE_END_OF_LIST 0x7FF\n \ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.h b/drivers/net/ethernet/intel/i40evf/i40e_txrx.h\nindex 0c13ece..c4f5a4e 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_txrx.h\n@@ -35,6 +35,7 @@\n #define I40E_ITR_20K 0x0019\n #define I40E_ITR_8K 0x003E\n #define I40E_ITR_4K 0x007A\n+#define I40E_MAX_INTRL 0x3B /* reg uses 4 usec resolution */\n #define I40E_ITR_RX_DEF I40E_ITR_8K\n #define I40E_ITR_TX_DEF I40E_ITR_4K\n #define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */\n@@ -44,6 +45,15 @@\n #define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1)\n #define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC))\n #define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1)\n+/* 0x40 is the enable bit for interrupt rate limiting, and must be set if\n+ * the value of the rate limit is non-zero\n+ */\n+#define INTRL_ENA BIT(6)\n+#define INTRL_REG_TO_USEC(intrl) ((intrl & ~INTRL_ENA) << 2)\n+#define INTRL_USEC_TO_REG(set) ((set) ? ((set) >> 2) | INTRL_ENA : 0)\n+#define I40E_INTRL_8K 125 /* 8000 ints/sec */\n+#define I40E_INTRL_62K 16 /* 62500 ints/sec */\n+#define I40E_INTRL_83K 12 /* 83333 ints/sec */\n \n #define I40E_QUEUE_END_OF_LIST 0x7FF\n \n", "prefixes": [ "next", "S16", "08/15" ] }