Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/514266/?format=api
{ "id": 514266, "url": "http://patchwork.ozlabs.org/api/patches/514266/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1441315142-173025-13-git-send-email-catherine.sullivan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1441315142-173025-13-git-send-email-catherine.sullivan@intel.com>", "list_archive_url": null, "date": "2015-09-03T21:18:59", "name": "[next,S15,12/15] i40e: X722 is on the IOSF bus and does not report the PCI bus info", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "aa2a90b68335727789fde53a4b4c43943fcd8ec5", "submitter": { "id": 13931, "url": "http://patchwork.ozlabs.org/api/people/13931/?format=api", "name": "Catherine Sullivan", "email": "catherine.sullivan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1441315142-173025-13-git-send-email-catherine.sullivan@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/514266/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/514266/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ozlabs.org (Postfix) with ESMTP id 618ED140771\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 4 Sep 2015 07:18:42 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 0C0839515A;\n\tThu, 3 Sep 2015 21:18:42 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id BQDR8jTbwW7y; Thu, 3 Sep 2015 21:18:41 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 80BEC952D8;\n\tThu, 3 Sep 2015 21:18:40 +0000 (UTC)", "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ash.osuosl.org (Postfix) with ESMTP id E61851C1777\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 3 Sep 2015 21:18:39 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id E22F6952C3\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 3 Sep 2015 21:18:39 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id BgSgTiruA8NG for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 3 Sep 2015 21:18:39 +0000 (UTC)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 58947952D0\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 3 Sep 2015 21:18:39 +0000 (UTC)", "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga103.jf.intel.com with ESMTP; 03 Sep 2015 14:18:26 -0700", "from catheri1-tigger.jf.intel.com ([134.134.176.92])\n\tby orsmga002.jf.intel.com with ESMTP; 03 Sep 2015 14:18:26 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.17,464,1437462000\"; d=\"scan'208\";a=\"797336068\"", "From": "Catherine Sullivan <catherine.sullivan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Thu, 3 Sep 2015 17:18:59 -0400", "Message-Id": "<1441315142-173025-13-git-send-email-catherine.sullivan@intel.com>", "X-Mailer": "git-send-email 1.9.3", "In-Reply-To": "<1441315142-173025-1-git-send-email-catherine.sullivan@intel.com>", "References": "<1441315142-173025-1-git-send-email-catherine.sullivan@intel.com>", "Subject": "[Intel-wired-lan] [next PATCH S15 12/15] i40e: X722 is on the IOSF\n\tbus and does not report the PCI bus info", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "From: Anjali Singhai Jain <anjali.singhai@intel.com>\n\nX722 will report Gen 1x1 in the PCI config space as it is on\nIOSF bus, so skip the PCI bus link/speed check.\n\nSigned-off-by: Anjali Singhai Jain <anjali.singhai@intel.com>\nChange-ID: Icd5f5751dc7fb00dccf0d5dc5a0a644948e7062e\n---\n drivers/net/ethernet/intel/i40e/i40e.h | 1 +\n drivers/net/ethernet/intel/i40e/i40e_main.c | 69 ++++++++++++++++++++---------\n 2 files changed, 50 insertions(+), 20 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e.h b/drivers/net/ethernet/intel/i40e/i40e.h\nindex a2a1d22..a404036 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e.h\n@@ -336,6 +336,7 @@ struct i40e_pf {\n #define I40E_FLAG_LINK_POLLING_ENABLED\t\tBIT_ULL(39)\n #define I40E_FLAG_VEB_MODE_ENABLED\t\tBIT_ULL(40)\n #define I40E_FLAG_GENEVE_OFFLOAD_CAPABLE\tBIT_ULL(41)\n+#define I40E_FLAG_NO_PCI_LINK_CHECK\t\tBIT_ULL(42)\n \n \t/* tracks features that get auto disabled by errors */\n \tu64 auto_disable_flags;\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c\nindex 6a28c04..4bcf4a1 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_main.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_main.c\n@@ -10555,26 +10555,55 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)\n \ti40e_fcoe_vsi_setup(pf);\n \n #endif\n-\t/* Get the negotiated link width and speed from PCI config space */\n-\tpcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, &link_status);\n-\n-\ti40e_set_pci_config_data(hw, link_status);\n-\n-\tdev_info(&pdev->dev, \"PCI-Express: %s %s\\n\",\n-\t\t(hw->bus.speed == i40e_bus_speed_8000 ? \"Speed 8.0GT/s\" :\n-\t\t hw->bus.speed == i40e_bus_speed_5000 ? \"Speed 5.0GT/s\" :\n-\t\t hw->bus.speed == i40e_bus_speed_2500 ? \"Speed 2.5GT/s\" :\n-\t\t \"Unknown\"),\n-\t\t(hw->bus.width == i40e_bus_width_pcie_x8 ? \"Width x8\" :\n-\t\t hw->bus.width == i40e_bus_width_pcie_x4 ? \"Width x4\" :\n-\t\t hw->bus.width == i40e_bus_width_pcie_x2 ? \"Width x2\" :\n-\t\t hw->bus.width == i40e_bus_width_pcie_x1 ? \"Width x1\" :\n-\t\t \"Unknown\"));\n-\n-\tif (hw->bus.width < i40e_bus_width_pcie_x8 ||\n-\t hw->bus.speed < i40e_bus_speed_8000) {\n-\t\tdev_warn(&pdev->dev, \"PCI-Express bandwidth available for this device may be insufficient for optimal performance.\\n\");\n-\t\tdev_warn(&pdev->dev, \"Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\\n\");\n+#define PCI_SPEED_SIZE 8\n+#define PCI_WIDTH_SIZE 8\n+\t/* Devices on the IOSF bus do not have this information\n+\t * and will report PCI Gen 1 x 1 by default so don't bother\n+\t * checking them.\n+\t */\n+\tif (!(pf->flags & I40E_FLAG_NO_PCI_LINK_CHECK)) {\n+\t\tchar speed[PCI_SPEED_SIZE] = \"Unknown\";\n+\t\tchar width[PCI_WIDTH_SIZE] = \"Unknown\";\n+\n+\t\t/* Get the negotiated link width and speed from PCI config\n+\t\t * space\n+\t\t */\n+\t\tpcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA,\n+\t\t\t\t\t &link_status);\n+\n+\t\ti40e_set_pci_config_data(hw, link_status);\n+\n+\t\tswitch (hw->bus.speed) {\n+\t\tcase i40e_bus_speed_8000:\n+\t\t\tstrncpy(speed, \"8.0\", PCI_SPEED_SIZE); break;\n+\t\tcase i40e_bus_speed_5000:\n+\t\t\tstrncpy(speed, \"5.0\", PCI_SPEED_SIZE); break;\n+\t\tcase i40e_bus_speed_2500:\n+\t\t\tstrncpy(speed, \"2.5\", PCI_SPEED_SIZE); break;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t\tswitch (hw->bus.width) {\n+\t\tcase i40e_bus_width_pcie_x8:\n+\t\t\tstrncpy(width, \"8\", PCI_WIDTH_SIZE); break;\n+\t\tcase i40e_bus_width_pcie_x4:\n+\t\t\tstrncpy(width, \"4\", PCI_WIDTH_SIZE); break;\n+\t\tcase i40e_bus_width_pcie_x2:\n+\t\t\tstrncpy(width, \"2\", PCI_WIDTH_SIZE); break;\n+\t\tcase i40e_bus_width_pcie_x1:\n+\t\t\tstrncpy(width, \"1\", PCI_WIDTH_SIZE); break;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tdev_info(&pdev->dev, \"PCI-Express: Speed %sGT/s Width x%s\\n\",\n+\t\t\t speed, width);\n+\n+\t\tif (hw->bus.width < i40e_bus_width_pcie_x8 ||\n+\t\t hw->bus.speed < i40e_bus_speed_8000) {\n+\t\t\tdev_warn(&pdev->dev, \"PCI-Express bandwidth available for this device may be insufficient for optimal performance.\\n\");\n+\t\t\tdev_warn(&pdev->dev, \"Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\\n\");\n+\t\t}\n \t}\n \n \t/* get the requested speeds from the fw */\n", "prefixes": [ "next", "S15", "12/15" ] }