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GET /api/patches/511343/?format=api
{ "id": 511343, "url": "http://patchwork.ozlabs.org/api/patches/511343/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1440690163-128213-9-git-send-email-catherine.sullivan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1440690163-128213-9-git-send-email-catherine.sullivan@intel.com>", "list_archive_url": null, "date": "2015-08-27T15:42:36", "name": "[next,S12,08/15] i40e: Add parsing for CEE DCBX TLVs", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "8fc4bfcf8625ac7bc4793a2685a34f0bb81f17b7", "submitter": { "id": 13931, "url": "http://patchwork.ozlabs.org/api/people/13931/?format=api", "name": "Catherine Sullivan", "email": "catherine.sullivan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1440690163-128213-9-git-send-email-catherine.sullivan@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/511343/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/511343/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ozlabs.org (Postfix) with ESMTP id C677A1401F0\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 28 Aug 2015 01:41:52 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id ECC5394FF4;\n\tThu, 27 Aug 2015 15:41:51 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id svTdvcYIcVv3; Thu, 27 Aug 2015 15:41:50 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id B41BB94FFB;\n\tThu, 27 Aug 2015 15:41:50 +0000 (UTC)", "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id E470C1C11E9\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 27 Aug 2015 15:41:47 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id DF42BA3C9C\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 27 Aug 2015 15:41:47 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id NkVD8vysmFjn for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 27 Aug 2015 15:41:47 +0000 (UTC)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 3B446A3C89\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 27 Aug 2015 15:41:47 +0000 (UTC)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby fmsmga102.fm.intel.com with ESMTP; 27 Aug 2015 08:41:47 -0700", "from catheri1-tigger.jf.intel.com ([134.134.176.92])\n\tby orsmga003.jf.intel.com with ESMTP; 27 Aug 2015 08:41:47 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.17,422,1437462000\"; d=\"scan'208\";a=\"633370245\"", "From": "Catherine Sullivan <catherine.sullivan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Thu, 27 Aug 2015 11:42:36 -0400", "Message-Id": "<1440690163-128213-9-git-send-email-catherine.sullivan@intel.com>", "X-Mailer": "git-send-email 1.9.3", "In-Reply-To": "<1440690163-128213-1-git-send-email-catherine.sullivan@intel.com>", "References": "<1440690163-128213-1-git-send-email-catherine.sullivan@intel.com>", "Subject": "[Intel-wired-lan] [next PATCH S12 08/15] i40e: Add parsing for CEE\n\tDCBX TLVs", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "From: Neerav Parikh <neerav.parikh@intel.com>\n\nThis patch adds parsing for CEE DCBX TLVs from the LLDP MIB.\n\nWhile the driver gets the DCB CEE operational configuration from Firmware\nusing the \"Get CEE DCBX Oper Config\" AQ command there is a need to get\nthe CEE DesiredCfg Tx by firmware and DCB configuration Rx from peer; for\ndebug and other application purposes.\n\nSigned-off-by: Neerav Parikh <neerav.parikh@intel.com>\nChange-ID: I9140edf1a25a2852c7eff805d81e5eff6266178d\n---\n drivers/net/ethernet/intel/i40e/i40e_dcb.c | 179 +++++++++++++++++++++++++++++\n drivers/net/ethernet/intel/i40e/i40e_dcb.h | 39 +++++++\n 2 files changed, 218 insertions(+)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_dcb.c b/drivers/net/ethernet/intel/i40e/i40e_dcb.c\nindex 9aee35d..89e60e3 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_dcb.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_dcb.c\n@@ -292,6 +292,182 @@ static void i40e_parse_ieee_tlv(struct i40e_lldp_org_tlv *tlv,\n }\n \n /**\n+ * i40e_parse_cee_pgcfg_tlv\n+ * @tlv: CEE DCBX PG CFG TLV\n+ * @dcbcfg: Local store to update ETS CFG data\n+ *\n+ * Parses CEE DCBX PG CFG TLV\n+ **/\n+static void i40e_parse_cee_pgcfg_tlv(struct i40e_cee_feat_tlv *tlv,\n+\t\t\t\t struct i40e_dcbx_config *dcbcfg)\n+{\n+\tstruct i40e_dcb_ets_config *etscfg;\n+\tu8 *buf = tlv->tlvinfo;\n+\tu16 offset = 0;\n+\tu8 priority;\n+\tint i;\n+\n+\tetscfg = &dcbcfg->etscfg;\n+\n+\tif (tlv->en_will_err & I40E_CEE_FEAT_TLV_WILLING_MASK)\n+\t\tetscfg->willing = 1;\n+\n+\tetscfg->cbs = 0;\n+\t/* Priority Group Table (4 octets)\n+\t * Octets:| 1 | 2 | 3 | 4 |\n+\t * -----------------------------------------\n+\t * |pri0|pri1|pri2|pri3|pri4|pri5|pri6|pri7|\n+\t * -----------------------------------------\n+\t * Bits:|7 4|3 0|7 4|3 0|7 4|3 0|7 4|3 0|\n+\t * -----------------------------------------\n+\t */\n+\tfor (i = 0; i < 4; i++) {\n+\t\tpriority = (u8)((buf[offset] & I40E_CEE_PGID_PRIO_1_MASK) >>\n+\t\t\t\t I40E_CEE_PGID_PRIO_1_SHIFT);\n+\t\tetscfg->prioritytable[i * 2] = priority;\n+\t\tpriority = (u8)((buf[offset] & I40E_CEE_PGID_PRIO_0_MASK) >>\n+\t\t\t\t I40E_CEE_PGID_PRIO_0_SHIFT);\n+\t\tetscfg->prioritytable[i * 2 + 1] = priority;\n+\t\toffset++;\n+\t}\n+\n+\t/* PG Percentage Table (8 octets)\n+\t * Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |\n+\t * ---------------------------------\n+\t * |pg0|pg1|pg2|pg3|pg4|pg5|pg6|pg7|\n+\t * ---------------------------------\n+\t */\n+\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)\n+\t\tetscfg->tcbwtable[i] = buf[offset++];\n+\n+\t/* Number of TCs supported (1 octet) */\n+\tetscfg->maxtcs = buf[offset];\n+}\n+\n+/**\n+ * i40e_parse_cee_pfccfg_tlv\n+ * @tlv: CEE DCBX PFC CFG TLV\n+ * @dcbcfg: Local store to update PFC CFG data\n+ *\n+ * Parses CEE DCBX PFC CFG TLV\n+ **/\n+static void i40e_parse_cee_pfccfg_tlv(struct i40e_cee_feat_tlv *tlv,\n+\t\t\t\t struct i40e_dcbx_config *dcbcfg)\n+{\n+\tu8 *buf = tlv->tlvinfo;\n+\n+\tif (tlv->en_will_err & I40E_CEE_FEAT_TLV_WILLING_MASK)\n+\t\tdcbcfg->pfc.willing = 1;\n+\n+\t/* ------------------------\n+\t * | PFC Enable | PFC TCs |\n+\t * ------------------------\n+\t * | 1 octet | 1 octet |\n+\t */\n+\tdcbcfg->pfc.pfcenable = buf[0];\n+\tdcbcfg->pfc.pfccap = buf[1];\n+}\n+\n+/**\n+ * i40e_parse_cee_app_tlv\n+ * @tlv: CEE DCBX APP TLV\n+ * @dcbcfg: Local store to update APP PRIO data\n+ *\n+ * Parses CEE DCBX APP PRIO TLV\n+ **/\n+static void i40e_parse_cee_app_tlv(struct i40e_cee_feat_tlv *tlv,\n+\t\t\t\t struct i40e_dcbx_config *dcbcfg)\n+{\n+\tu16 length, typelength, offset = 0;\n+\tstruct i40e_cee_app_prio *app;\n+\tu8 i, up;\n+\n+\ttypelength = ntohs(tlv->hdr.typelen);\n+\tlength = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>\n+\t\t I40E_LLDP_TLV_LEN_SHIFT);\n+\n+\tdcbcfg->numapps = length / sizeof(*app);\n+\tif (!dcbcfg->numapps)\n+\t\treturn;\n+\n+\tfor (i = 0; i < dcbcfg->numapps; i++) {\n+\t\tapp = (struct i40e_cee_app_prio *)(tlv->tlvinfo + offset);\n+\t\tfor (up = 0; up < I40E_MAX_USER_PRIORITY; up++) {\n+\t\t\tif (app->prio_map & (1 << up))\n+\t\t\t\tbreak;\n+\t\t}\n+\t\tdcbcfg->app[i].priority = up;\n+\t\t/* Get Selector from lower 2 bits */\n+\t\tdcbcfg->app[i].selector = (app->upper_oui_sel &\n+\t\t\t\t\t I40E_CEE_APP_SELECTOR_MASK);\n+\t\tdcbcfg->app[i].protocolid = ntohs(app->protocol);\n+\t\t/* Move to next app */\n+\t\toffset += sizeof(*app);\n+\t}\n+}\n+\n+/**\n+ * i40e_parse_cee_tlv\n+ * @tlv: CEE DCBX TLV\n+ * @dcbcfg: Local store to update DCBX config data\n+ *\n+ * Get the TLV subtype and send it to parsing function\n+ * based on the subtype value\n+ **/\n+static void i40e_parse_cee_tlv(struct i40e_lldp_org_tlv *tlv,\n+\t\t\t struct i40e_dcbx_config *dcbcfg)\n+{\n+\tu16 len, tlvlen, sublen, typelength;\n+\tstruct i40e_cee_feat_tlv *sub_tlv;\n+\tu8 subtype, feat_tlv_count = 0;\n+\tu32 ouisubtype;\n+\n+\touisubtype = ntohl(tlv->ouisubtype);\n+\tsubtype = (u8)((ouisubtype & I40E_LLDP_TLV_SUBTYPE_MASK) >>\n+\t\t I40E_LLDP_TLV_SUBTYPE_SHIFT);\n+\t/* Return if not CEE DCBX */\n+\tif (subtype != I40E_CEE_DCBX_TYPE)\n+\t\treturn;\n+\n+\ttypelength = ntohs(tlv->typelength);\n+\ttlvlen = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>\n+\t\t\tI40E_LLDP_TLV_LEN_SHIFT);\n+\tlen = sizeof(tlv->typelength) + sizeof(ouisubtype) +\n+\t sizeof(struct i40e_cee_ctrl_tlv);\n+\t/* Return if no CEE DCBX Feature TLVs */\n+\tif (tlvlen <= len)\n+\t\treturn;\n+\n+\tsub_tlv = (struct i40e_cee_feat_tlv *)((char *)tlv + len);\n+\twhile (feat_tlv_count < I40E_CEE_MAX_FEAT_TYPE) {\n+\t\ttypelength = ntohs(sub_tlv->hdr.typelen);\n+\t\tsublen = (u16)((typelength &\n+\t\t\t\tI40E_LLDP_TLV_LEN_MASK) >>\n+\t\t\t\tI40E_LLDP_TLV_LEN_SHIFT);\n+\t\tsubtype = (u8)((typelength & I40E_LLDP_TLV_TYPE_MASK) >>\n+\t\t\t\tI40E_LLDP_TLV_TYPE_SHIFT);\n+\t\tswitch (subtype) {\n+\t\tcase I40E_CEE_SUBTYPE_PG_CFG:\n+\t\t\ti40e_parse_cee_pgcfg_tlv(sub_tlv, dcbcfg);\n+\t\t\tbreak;\n+\t\tcase I40E_CEE_SUBTYPE_PFC_CFG:\n+\t\t\ti40e_parse_cee_pfccfg_tlv(sub_tlv, dcbcfg);\n+\t\t\tbreak;\n+\t\tcase I40E_CEE_SUBTYPE_APP_PRI:\n+\t\t\ti40e_parse_cee_app_tlv(sub_tlv, dcbcfg);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn; /* Invalid Sub-type return */\n+\t\t}\n+\t\tfeat_tlv_count++;\n+\t\t/* Move to next sub TLV */\n+\t\tsub_tlv = (struct i40e_cee_feat_tlv *)((char *)sub_tlv +\n+\t\t\t\t\t\tsizeof(sub_tlv->hdr.typelen) +\n+\t\t\t\t\t\tsublen);\n+\t}\n+}\n+\n+/**\n * i40e_parse_org_tlv\n * @tlv: Organization specific TLV\n * @dcbcfg: Local store to update ETS REC data\n@@ -312,6 +488,9 @@ static void i40e_parse_org_tlv(struct i40e_lldp_org_tlv *tlv,\n \tcase I40E_IEEE_8021QAZ_OUI:\n \t\ti40e_parse_ieee_tlv(tlv, dcbcfg);\n \t\tbreak;\n+\tcase I40E_CEE_DCBX_OUI:\n+\t\ti40e_parse_cee_tlv(tlv, dcbcfg);\n+\t\tbreak;\n \tdefault:\n \t\tbreak;\n \t}\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_dcb.h b/drivers/net/ethernet/intel/i40e/i40e_dcb.h\nindex 50fc894..92d0104 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_dcb.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_dcb.h\n@@ -44,6 +44,15 @@\n #define I40E_IEEE_SUBTYPE_PFC_CFG\t11\n #define I40E_IEEE_SUBTYPE_APP_PRI\t12\n \n+#define I40E_CEE_DCBX_OUI\t\t0x001b21\n+#define I40E_CEE_DCBX_TYPE\t\t2\n+\n+#define I40E_CEE_SUBTYPE_CTRL\t\t1\n+#define I40E_CEE_SUBTYPE_PG_CFG\t\t2\n+#define I40E_CEE_SUBTYPE_PFC_CFG\t3\n+#define I40E_CEE_SUBTYPE_APP_PRI\t4\n+\n+#define I40E_CEE_MAX_FEAT_TYPE\t\t3\n /* Defines for LLDP TLV header */\n #define I40E_LLDP_TLV_LEN_SHIFT\t\t0\n #define I40E_LLDP_TLV_LEN_MASK\t\t(0x01FF << I40E_LLDP_TLV_LEN_SHIFT)\n@@ -98,6 +107,36 @@ struct i40e_lldp_org_tlv {\n \t__be32 ouisubtype;\n \tu8 tlvinfo[1];\n };\n+\n+struct i40e_cee_tlv_hdr {\n+\t__be16 typelen;\n+\tu8 operver;\n+\tu8 maxver;\n+};\n+\n+struct i40e_cee_ctrl_tlv {\n+\tstruct i40e_cee_tlv_hdr hdr;\n+\t__be32 seqno;\n+\t__be32 ackno;\n+};\n+\n+struct i40e_cee_feat_tlv {\n+\tstruct i40e_cee_tlv_hdr hdr;\n+\tu8 en_will_err; /* Bits: |En|Will|Err|Reserved(5)| */\n+#define I40E_CEE_FEAT_TLV_ENABLE_MASK\t0x80\n+#define I40E_CEE_FEAT_TLV_WILLING_MASK\t0x40\n+#define I40E_CEE_FEAT_TLV_ERR_MASK\t0x20\n+\tu8 subtype;\n+\tu8 tlvinfo[1];\n+};\n+\n+struct i40e_cee_app_prio {\n+\t__be16 protocol;\n+\tu8 upper_oui_sel; /* Bits: |Upper OUI(6)|Selector(2)| */\n+#define I40E_CEE_APP_SELECTOR_MASK\t0x03\n+\t__be16 lower_oui;\n+\tu8 prio_map;\n+};\n #pragma pack()\n \n i40e_status i40e_get_dcbx_status(struct i40e_hw *hw,\n", "prefixes": [ "next", "S12", "08/15" ] }