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GET /api/patches/501736/?format=api
{ "id": 501736, "url": "http://patchwork.ozlabs.org/api/patches/501736/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20150729143119.19466.3645.stgit@htfujina-fc.jf.intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20150729143119.19466.3645.stgit@htfujina-fc.jf.intel.com>", "list_archive_url": null, "date": "2015-07-29T14:32:06", "name": "[v2] igb: add support for 1512 PHY", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "69dc8f8717280935d08aaf492eb6524d3e45fc83", "submitter": { "id": 29211, "url": "http://patchwork.ozlabs.org/api/people/29211/?format=api", "name": "Fujinaka, Todd", "email": "todd.fujinaka@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20150729143119.19466.3645.stgit@htfujina-fc.jf.intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/501736/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/501736/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\tby ozlabs.org (Postfix) with ESMTP id 600C21402C8\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 30 Jul 2015 00:35:45 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 5A08E920CE;\n\tWed, 29 Jul 2015 14:35:44 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id rPMwQ0rNNZfm; Wed, 29 Jul 2015 14:35:43 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 8C18B91BBD;\n\tWed, 29 Jul 2015 14:35:43 +0000 (UTC)", "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id 8F7211CE851\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 29 Jul 2015 14:35:42 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 70CC0A3E53\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 29 Jul 2015 14:35:42 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id UTSH1UyafiwC for <intel-wired-lan@lists.osuosl.org>;\n\tWed, 29 Jul 2015 14:35:41 +0000 (UTC)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 3BC1AA428F\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 29 Jul 2015 14:35:41 +0000 (UTC)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga101.jf.intel.com with ESMTP; 29 Jul 2015 07:35:40 -0700", "from htfujina-fc.jf.intel.com ([134.134.145.128])\n\tby fmsmga002.fm.intel.com with ESMTP; 29 Jul 2015 07:35:40 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.15,571,1432623600\"; d=\"scan'208\";a=\"772264403\"", "From": "Todd Fujinaka <todd.fujinaka@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Wed, 29 Jul 2015 07:32:06 -0700", "Message-ID": "<20150729143119.19466.3645.stgit@htfujina-fc.jf.intel.com>", "User-Agent": "StGit/0.17.1-dirty", "MIME-Version": "1.0", "Subject": "[Intel-wired-lan] [PATCH v2] igb: add support for 1512 PHY", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "This patch adds support for Marvell PHY 1512 (required for I354).\n\nSubmitted by: Maciej Szwed <maciej.szwed@intel.com>\nSigned-off-by: Todd Fujinaka <todd.fujinaka@intel.com>\n---\n drivers/net/ethernet/intel/igb/e1000_82575.c | 20 ++++-\n drivers/net/ethernet/intel/igb/e1000_defines.h | 5 +\n drivers/net/ethernet/intel/igb/e1000_phy.c | 93 +++++++++++++++++++++++-\n drivers/net/ethernet/intel/igb/e1000_phy.h | 1 \n 4 files changed, 114 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/igb/e1000_82575.c b/drivers/net/ethernet/intel/igb/e1000_82575.c\nindex 6e59d0e..cb7b78c 100644\n--- a/drivers/net/ethernet/intel/igb/e1000_82575.c\n+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c\n@@ -231,6 +231,7 @@ static s32 igb_init_phy_params_82575(struct e1000_hw *hw)\n \t/* Verify phy id and set remaining function pointers */\n \tswitch (phy->id) {\n \tcase M88E1543_E_PHY_ID:\n+\tcase M88E1512_E_PHY_ID:\n \tcase I347AT4_E_PHY_ID:\n \tcase M88E1112_E_PHY_ID:\n \tcase M88E1111_I_PHY_ID:\n@@ -243,7 +244,7 @@ static s32 igb_init_phy_params_82575(struct e1000_hw *hw)\n \t\telse\n \t\t\tphy->ops.get_cable_length = igb_get_cable_length_m88;\n \t\tphy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;\n-\t\t/* Check if this PHY is confgured for media swap. */\n+\t\t/* Check if this PHY is configured for media swap. */\n \t\tif (phy->id == M88E1112_E_PHY_ID) {\n \t\t\tu16 data;\n \n@@ -266,6 +267,11 @@ static s32 igb_init_phy_params_82575(struct e1000_hw *hw)\n \t\t\t\thw->mac.ops.check_for_link =\n \t\t\t\t\t\tigb_check_for_link_media_swap;\n \t\t}\n+\t\tif (phy->id == M88E1512_E_PHY_ID) {\n+\t\t\tret_val = igb_initialize_M88E1512_phy(hw);\n+\t\t\tif (ret_val)\n+\t\t\t\tgoto out;\n+\t\t}\n \t\tbreak;\n \tcase IGP03E1000_E_PHY_ID:\n \t\tphy->type = e1000_phy_igp_3;\n@@ -900,6 +906,7 @@ out:\n **/\n static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)\n {\n+\tstruct e1000_phy_info *phy = &hw->phy;\n \ts32 ret_val;\n \n \t/* This isn't a true \"hard\" reset, but is the only reset\n@@ -916,7 +923,11 @@ static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)\n \t\tgoto out;\n \n \tret_val = igb_phy_sw_reset(hw);\n+\tif (ret_val)\n+\t\tgoto out;\n \n+\tif (phy->id == M88E1512_E_PHY_ID)\n+\t\tret_val = igb_initialize_M88E1512_phy(hw);\n out:\n \treturn ret_val;\n }\n@@ -1590,6 +1601,7 @@ static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)\n \t\tcase I347AT4_E_PHY_ID:\n \t\tcase M88E1112_E_PHY_ID:\n \t\tcase M88E1543_E_PHY_ID:\n+\t\tcase M88E1512_E_PHY_ID:\n \t\tcase I210_I_PHY_ID:\n \t\t\tret_val = igb_copper_link_setup_m88_gen2(hw);\n \t\t\tbreak;\n@@ -2634,7 +2646,8 @@ s32 igb_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)\n \tu16 phy_data;\n \n \tif ((hw->phy.media_type != e1000_media_type_copper) ||\n-\t (phy->id != M88E1543_E_PHY_ID))\n+\t ((phy->id != M88E1543_E_PHY_ID) &&\n+\t (phy->id != M88E1512_E_PHY_ID)))\n \t\tgoto out;\n \n \tif (!hw->dev_spec._82575.eee_disable) {\n@@ -2714,7 +2727,8 @@ s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)\n \n \t/* Check if EEE is supported on this device. */\n \tif ((hw->phy.media_type != e1000_media_type_copper) ||\n-\t (phy->id != M88E1543_E_PHY_ID))\n+\t ((phy->id != M88E1543_E_PHY_ID) &&\n+\t (phy->id != M88E1512_E_PHY_ID)))\n \t\tgoto out;\n \n \tret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,\ndiff --git a/drivers/net/ethernet/intel/igb/e1000_defines.h b/drivers/net/ethernet/intel/igb/e1000_defines.h\nindex 1c87d74..0032517 100644\n--- a/drivers/net/ethernet/intel/igb/e1000_defines.h\n+++ b/drivers/net/ethernet/intel/igb/e1000_defines.h\n@@ -604,6 +604,10 @@\n #define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT\t7\n #define E1000_M88E1112_PAGE_ADDR\t\t0x16\n #define E1000_M88E1112_STATUS\t\t\t0x01\n+#define E1000_M88E1512_CFG_REG_1 0x0010\n+#define E1000_M88E1512_CFG_REG_2 0x0011\n+#define E1000_M88E1512_CFG_REG_3 0x0007\n+#define E1000_M88E1512_MODE 0x0014\n \n /* PCI Express Control */\n #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000\n@@ -861,6 +865,7 @@\n #define M88_VENDOR 0x0141\n #define I210_I_PHY_ID 0x01410C00\n #define M88E1543_E_PHY_ID 0x01410EA0\n+#define M88E1512_E_PHY_ID 0x01410DD0\n #define BCM54616_E_PHY_ID 0x03625D10\n \n /* M88E1000 Specific Registers */\ndiff --git a/drivers/net/ethernet/intel/igb/e1000_phy.c b/drivers/net/ethernet/intel/igb/e1000_phy.c\nindex 987c9de..23ec28f 100644\n--- a/drivers/net/ethernet/intel/igb/e1000_phy.c\n+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c\n@@ -1262,6 +1262,8 @@ s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)\n \t\t\tswitch (hw->phy.id) {\n \t\t\tcase I347AT4_E_PHY_ID:\n \t\t\tcase M88E1112_E_PHY_ID:\n+\t\t\tcase M88E1543_E_PHY_ID:\n+\t\t\tcase M88E1512_E_PHY_ID:\n \t\t\tcase I210_I_PHY_ID:\n \t\t\t\treset_dsp = false;\n \t\t\t\tbreak;\n@@ -1270,9 +1272,9 @@ s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)\n \t\t\t\t\treset_dsp = false;\n \t\t\t\tbreak;\n \t\t\t}\n-\t\t\tif (!reset_dsp)\n+\t\t\tif (!reset_dsp) {\n \t\t\t\thw_dbg(\"Link taking longer than expected.\\n\");\n-\t\t\telse {\n+\t\t\t} else {\n \t\t\t\t/* We didn't get link.\n \t\t\t\t * Reset the DSP and cross our fingers.\n \t\t\t\t */\n@@ -1297,6 +1299,8 @@ s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)\n \tif (hw->phy.type != e1000_phy_m88 ||\n \t hw->phy.id == I347AT4_E_PHY_ID ||\n \t hw->phy.id == M88E1112_E_PHY_ID ||\n+\t hw->phy.id == M88E1543_E_PHY_ID ||\n+\t hw->phy.id == M88E1512_E_PHY_ID ||\n \t hw->phy.id == I210_I_PHY_ID)\n \t\tgoto out;\n \n@@ -1737,6 +1741,7 @@ s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw)\n \t\tphy->cable_length = phy_data / (is_cm ? 100 : 1);\n \t\tbreak;\n \tcase M88E1543_E_PHY_ID:\n+\tcase M88E1512_E_PHY_ID:\n \tcase I347AT4_E_PHY_ID:\n \t\t/* Remember the original page select and set it to 7 */\n \t\tret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,\n@@ -2189,6 +2194,90 @@ s32 igb_phy_init_script_igp3(struct e1000_hw *hw)\n }\n \n /**\n+ * igb_initialize_M88E1512_phy - Initialize M88E1512 PHY\n+ * @hw: pointer to the HW structure\n+ *\n+ * Initialize Marvel 1512 to work correctly with Avoton.\n+ **/\n+s32 igb_initialize_M88E1512_phy(struct e1000_hw *hw)\n+{\n+\tstruct e1000_phy_info *phy = &hw->phy;\n+\ts32 ret_val = 0;\n+\n+\t/* Switch to PHY page 0xFF. */\n+\tret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);\n+\tif (ret_val)\n+\t\tgoto out;\n+\n+\tret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);\n+\tif (ret_val)\n+\t\tgoto out;\n+\n+\tret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);\n+\tif (ret_val)\n+\t\tgoto out;\n+\n+\tret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);\n+\tif (ret_val)\n+\t\tgoto out;\n+\n+\tret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);\n+\tif (ret_val)\n+\t\tgoto out;\n+\n+\tret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);\n+\tif (ret_val)\n+\t\tgoto out;\n+\n+\tret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);\n+\tif (ret_val)\n+\t\tgoto out;\n+\n+\tret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);\n+\tif (ret_val)\n+\t\tgoto out;\n+\n+\tret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);\n+\tif (ret_val)\n+\t\tgoto out;\n+\n+\t/* Switch to PHY page 0xFB. */\n+\tret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);\n+\tif (ret_val)\n+\t\tgoto out;\n+\n+\tret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);\n+\tif (ret_val)\n+\t\tgoto out;\n+\n+\t/* Switch to PHY page 0x12. */\n+\tret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);\n+\tif (ret_val)\n+\t\tgoto out;\n+\n+\t/* Change mode to SGMII-to-Copper */\n+\tret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);\n+\tif (ret_val)\n+\t\tgoto out;\n+\n+\t/* Return the PHY to page 0. */\n+\tret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);\n+\tif (ret_val)\n+\t\tgoto out;\n+\n+\tret_val = igb_phy_sw_reset(hw);\n+\tif (ret_val) {\n+\t\thw_dbg(\"Error committing the PHY changes\\n\");\n+\t\treturn ret_val;\n+\t}\n+\n+\t/* msec_delay(1000); */\n+\tusleep_range(1000, 2000);\n+out:\n+\treturn ret_val;\n+}\n+\n+/**\n * igb_power_up_phy_copper - Restore copper link in case of PHY power down\n * @hw: pointer to the HW structure\n *\ndiff --git a/drivers/net/ethernet/intel/igb/e1000_phy.h b/drivers/net/ethernet/intel/igb/e1000_phy.h\nindex 7af4ffa..24d55ed 100644\n--- a/drivers/net/ethernet/intel/igb/e1000_phy.h\n+++ b/drivers/net/ethernet/intel/igb/e1000_phy.h\n@@ -61,6 +61,7 @@ s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,\n void igb_power_up_phy_copper(struct e1000_hw *hw);\n void igb_power_down_phy_copper(struct e1000_hw *hw);\n s32 igb_phy_init_script_igp3(struct e1000_hw *hw);\n+s32 igb_initialize_M88E1512_phy(struct e1000_hw *hw);\n s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);\n s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);\n s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);\n", "prefixes": [ "v2" ] }