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GET /api/patches/493924/?format=api
{ "id": 493924, "url": "http://patchwork.ozlabs.org/api/patches/493924/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1436571370-103673-10-git-send-email-catherine.sullivan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1436571370-103673-10-git-send-email-catherine.sullivan@intel.com>", "list_archive_url": null, "date": "2015-07-10T23:36:05", "name": "[next,S8,10/15] i40evf: Use the correct defines to match the VF registers", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "1c925ab14e86a6e633c690cdea20a44dd2853e39", "submitter": { "id": 13931, "url": "http://patchwork.ozlabs.org/api/people/13931/?format=api", "name": "Catherine Sullivan", "email": "catherine.sullivan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1436571370-103673-10-git-send-email-catherine.sullivan@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/493924/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/493924/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\tby ozlabs.org (Postfix) with ESMTP id 951951402B4\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 11 Jul 2015 09:34:03 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id E26128C564;\n\tFri, 10 Jul 2015 23:34:02 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 0Q2xzkfVrreQ; Fri, 10 Jul 2015 23:34:01 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 58C9D8B9C2;\n\tFri, 10 Jul 2015 23:34:00 +0000 (UTC)", "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ash.osuosl.org (Postfix) with ESMTP id C9B201C21C5\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 10 Jul 2015 23:33:58 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id C60F3938FE\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 10 Jul 2015 23:33:58 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id HgIqV+ZXWeqX for <intel-wired-lan@lists.osuosl.org>;\n\tFri, 10 Jul 2015 23:33:58 +0000 (UTC)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id A3A4F938FF\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 10 Jul 2015 23:33:57 +0000 (UTC)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga101.jf.intel.com with ESMTP; 10 Jul 2015 16:33:45 -0700", "from catheri1-tigger.jf.intel.com ([134.134.176.92])\n\tby orsmga001.jf.intel.com with ESMTP; 10 Jul 2015 16:33:45 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.15,450,1432623600\"; d=\"scan'208\";a=\"726728108\"", "From": "Catherine Sullivan <catherine.sullivan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Fri, 10 Jul 2015 19:36:05 -0400", "Message-Id": "<1436571370-103673-10-git-send-email-catherine.sullivan@intel.com>", "X-Mailer": "git-send-email 1.9.3", "In-Reply-To": "<1436571370-103673-1-git-send-email-catherine.sullivan@intel.com>", "References": "<1436571370-103673-1-git-send-email-catherine.sullivan@intel.com>", "Cc": "Anjali Singhai Jain <anjali.singhai@intel.com>", "Subject": "[Intel-wired-lan] [intel-wired-lan][next PATCH S8 10/15] i40evf:\n\tUse the correct defines to match the VF registers", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "From: Anjali Singhai Jain <anjali.singhai@intel.com>\n\nUse CTLN1 instead of CTLN for the VF relative register space.\n\nSigned-off-by: Anjali Singhai Jain <anjali.singhai@intel.com>\nChange-ID: Iefba63faf0307af55fec8dbb64f26059f7d91318\n---\n drivers/net/ethernet/intel/i40evf/i40e_txrx.c | 28 +++++++++---------\n drivers/net/ethernet/intel/i40evf/i40evf_main.c | 38 ++++++++++++-------------\n 2 files changed, 33 insertions(+), 33 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\nindex 7309479..7e91d82 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\n@@ -1293,17 +1293,17 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,\n \t\told_itr = q_vector->rx.itr;\n \t\ti40e_set_new_dynamic_itr(&q_vector->rx);\n \t\tif (old_itr != q_vector->rx.itr) {\n-\t\t\tval = I40E_VFINT_DYN_CTLN_INTENA_MASK |\n-\t\t\tI40E_VFINT_DYN_CTLN_CLEARPBA_MASK |\n+\t\t\tval = I40E_VFINT_DYN_CTLN1_INTENA_MASK |\n+\t\t\tI40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |\n \t\t\t(I40E_RX_ITR <<\n-\t\t\t\tI40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT) |\n+\t\t\t\tI40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |\n \t\t\t(q_vector->rx.itr <<\n-\t\t\t\tI40E_VFINT_DYN_CTLN_INTERVAL_SHIFT);\n+\t\t\t\tI40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);\n \t\t} else {\n-\t\t\tval = I40E_VFINT_DYN_CTLN_INTENA_MASK |\n-\t\t\tI40E_VFINT_DYN_CTLN_CLEARPBA_MASK |\n+\t\t\tval = I40E_VFINT_DYN_CTLN1_INTENA_MASK |\n+\t\t\tI40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |\n \t\t\t(I40E_ITR_NONE <<\n-\t\t\t\tI40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT);\n+\t\t\t\tI40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT);\n \t\t}\n \t\tif (!test_bit(__I40E_DOWN, &vsi->state))\n \t\t\twr32(hw, I40E_VFINT_DYN_CTLN1(vector - 1), val);\n@@ -1315,18 +1315,18 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,\n \t\told_itr = q_vector->tx.itr;\n \t\ti40e_set_new_dynamic_itr(&q_vector->tx);\n \t\tif (old_itr != q_vector->tx.itr) {\n-\t\t\tval = I40E_VFINT_DYN_CTLN_INTENA_MASK |\n-\t\t\t\tI40E_VFINT_DYN_CTLN_CLEARPBA_MASK |\n+\t\t\tval = I40E_VFINT_DYN_CTLN1_INTENA_MASK |\n+\t\t\t\tI40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |\n \t\t\t\t(I40E_TX_ITR <<\n-\t\t\t\t I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT) |\n+\t\t\t\t I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |\n \t\t\t\t(q_vector->tx.itr <<\n-\t\t\t\t I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT);\n+\t\t\t\t I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);\n \n \t\t} else {\n-\t\t\tval = I40E_VFINT_DYN_CTLN_INTENA_MASK |\n-\t\t\t\tI40E_VFINT_DYN_CTLN_CLEARPBA_MASK |\n+\t\t\tval = I40E_VFINT_DYN_CTLN1_INTENA_MASK |\n+\t\t\t\tI40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |\n \t\t\t\t(I40E_ITR_NONE <<\n-\t\t\t\t I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT);\n+\t\t\t\t I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT);\n \t\t}\n \t\tif (!test_bit(__I40E_DOWN, &vsi->state))\n \t\t\twr32(hw, I40E_VFINT_DYN_CTLN1(vector - 1), val);\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40evf_main.c b/drivers/net/ethernet/intel/i40evf/i40evf_main.c\nindex fc9e7fa..57e2224 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40evf_main.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40evf_main.c\n@@ -126,7 +126,7 @@ static void i40evf_misc_irq_enable(struct i40evf_adapter *adapter)\n \n \twr32(hw, I40E_VFINT_DYN_CTL01, I40E_VFINT_DYN_CTL01_INTENA_MASK |\n \t\t\t\t I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);\n-\twr32(hw, I40E_VFINT_ICR0_ENA1, I40E_VFINT_ICR0_ENA_ADMINQ_MASK);\n+\twr32(hw, I40E_VFINT_ICR0_ENA1, I40E_VFINT_ICR0_ENA1_ADMINQ_MASK);\n \n \t/* read flush */\n \trd32(hw, I40E_VFGEN_RSTAT);\n@@ -167,7 +167,7 @@ void i40evf_irq_enable_queues(struct i40evf_adapter *adapter, u32 mask)\n \t\t\twr32(hw, I40E_VFINT_DYN_CTLN1(i - 1),\n \t\t\t I40E_VFINT_DYN_CTLN1_INTENA_MASK |\n \t\t\t I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK |\n-\t\t\t I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);\n+\t\t\t I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK);\n \t\t}\n \t}\n }\n@@ -185,17 +185,17 @@ static void i40evf_fire_sw_int(struct i40evf_adapter *adapter, u32 mask)\n \n \tif (mask & 1) {\n \t\tdyn_ctl = rd32(hw, I40E_VFINT_DYN_CTL01);\n-\t\tdyn_ctl |= I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK |\n+\t\tdyn_ctl |= I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |\n \t\t\t I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK |\n-\t\t\t I40E_VFINT_DYN_CTLN_CLEARPBA_MASK;\n+\t\t\t I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK;\n \t\twr32(hw, I40E_VFINT_DYN_CTL01, dyn_ctl);\n \t}\n \tfor (i = 1; i < adapter->num_msix_vectors; i++) {\n \t\tif (mask & BIT(i)) {\n \t\t\tdyn_ctl = rd32(hw, I40E_VFINT_DYN_CTLN1(i - 1));\n-\t\t\tdyn_ctl |= I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK |\n+\t\t\tdyn_ctl |= I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |\n \t\t\t\t I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK |\n-\t\t\t\t I40E_VFINT_DYN_CTLN_CLEARPBA_MASK;\n+\t\t\t\t I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK;\n \t\t\twr32(hw, I40E_VFINT_DYN_CTLN1(i - 1), dyn_ctl);\n \t\t}\n \t}\n@@ -235,7 +235,7 @@ static irqreturn_t i40evf_msix_aq(int irq, void *data)\n \n \n \tval = rd32(hw, I40E_VFINT_DYN_CTL01);\n-\tval = val | I40E_PFINT_DYN_CTL0_CLEARPBA_MASK;\n+\tval = val | I40E_VFINT_DYN_CTL01_CLEARPBA_MASK;\n \twr32(hw, I40E_VFINT_DYN_CTL01, val);\n \n \t/* schedule work on the private workqueue */\n@@ -1701,34 +1701,34 @@ static void i40evf_adminq_task(struct work_struct *work)\n \t/* check for error indications */\n \tval = rd32(hw, hw->aq.arq.len);\n \toldval = val;\n-\tif (val & I40E_VF_ARQLEN_ARQVFE_MASK) {\n+\tif (val & I40E_VF_ARQLEN1_ARQVFE_MASK) {\n \t\tdev_info(&adapter->pdev->dev, \"ARQ VF Error detected\\n\");\n-\t\tval &= ~I40E_VF_ARQLEN_ARQVFE_MASK;\n+\t\tval &= ~I40E_VF_ARQLEN1_ARQVFE_MASK;\n \t}\n-\tif (val & I40E_VF_ARQLEN_ARQOVFL_MASK) {\n+\tif (val & I40E_VF_ARQLEN1_ARQOVFL_MASK) {\n \t\tdev_info(&adapter->pdev->dev, \"ARQ Overflow Error detected\\n\");\n-\t\tval &= ~I40E_VF_ARQLEN_ARQOVFL_MASK;\n+\t\tval &= ~I40E_VF_ARQLEN1_ARQOVFL_MASK;\n \t}\n-\tif (val & I40E_VF_ARQLEN_ARQCRIT_MASK) {\n+\tif (val & I40E_VF_ARQLEN1_ARQCRIT_MASK) {\n \t\tdev_info(&adapter->pdev->dev, \"ARQ Critical Error detected\\n\");\n-\t\tval &= ~I40E_VF_ARQLEN_ARQCRIT_MASK;\n+\t\tval &= ~I40E_VF_ARQLEN1_ARQCRIT_MASK;\n \t}\n \tif (oldval != val)\n \t\twr32(hw, hw->aq.arq.len, val);\n \n \tval = rd32(hw, hw->aq.asq.len);\n \toldval = val;\n-\tif (val & I40E_VF_ATQLEN_ATQVFE_MASK) {\n+\tif (val & I40E_VF_ATQLEN1_ATQVFE_MASK) {\n \t\tdev_info(&adapter->pdev->dev, \"ASQ VF Error detected\\n\");\n-\t\tval &= ~I40E_VF_ATQLEN_ATQVFE_MASK;\n+\t\tval &= ~I40E_VF_ATQLEN1_ATQVFE_MASK;\n \t}\n-\tif (val & I40E_VF_ATQLEN_ATQOVFL_MASK) {\n+\tif (val & I40E_VF_ATQLEN1_ATQOVFL_MASK) {\n \t\tdev_info(&adapter->pdev->dev, \"ASQ Overflow Error detected\\n\");\n-\t\tval &= ~I40E_VF_ATQLEN_ATQOVFL_MASK;\n+\t\tval &= ~I40E_VF_ATQLEN1_ATQOVFL_MASK;\n \t}\n-\tif (val & I40E_VF_ATQLEN_ATQCRIT_MASK) {\n+\tif (val & I40E_VF_ATQLEN1_ATQCRIT_MASK) {\n \t\tdev_info(&adapter->pdev->dev, \"ASQ Critical Error detected\\n\");\n-\t\tval &= ~I40E_VF_ATQLEN_ATQCRIT_MASK;\n+\t\tval &= ~I40E_VF_ATQLEN1_ATQCRIT_MASK;\n \t}\n \tif (oldval != val)\n \t\twr32(hw, hw->aq.asq.len, val);\n", "prefixes": [ "next", "S8", "10/15" ] }