Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/481470/?format=api
{ "id": 481470, "url": "http://patchwork.ozlabs.org/api/patches/481470/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1433521234-33355-6-git-send-email-catherine.sullivan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1433521234-33355-6-git-send-email-catherine.sullivan@intel.com>", "list_archive_url": null, "date": "2015-06-05T16:20:29", "name": "[net-next,S07,05/10] i40e/i40evf: RSS changes for X722", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "82f31ea5e4f5fd7076ef05fa6d6b1fbe8d30f883", "submitter": { "id": 13931, "url": "http://patchwork.ozlabs.org/api/people/13931/?format=api", "name": "Catherine Sullivan", "email": "catherine.sullivan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1433521234-33355-6-git-send-email-catherine.sullivan@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/481470/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/481470/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from fraxinus.osuosl.org (fraxinus.osuosl.org [140.211.166.137])\n\tby ozlabs.org (Postfix) with ESMTP id 594F41402AC\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 6 Jun 2015 02:19:36 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id AE5A5A395C;\n\tFri, 5 Jun 2015 16:19:35 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id m_i5IuKzG1lD; Fri, 5 Jun 2015 16:19:32 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 830BDA398A;\n\tFri, 5 Jun 2015 16:19:31 +0000 (UTC)", "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\tby ash.osuosl.org (Postfix) with ESMTP id B7C291C1FC8\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 5 Jun 2015 16:19:30 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id B463A9181A\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 5 Jun 2015 16:19:30 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 9S9udqIEhzK0 for <intel-wired-lan@lists.osuosl.org>;\n\tFri, 5 Jun 2015 16:19:27 +0000 (UTC)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id B798991821\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 5 Jun 2015 16:19:27 +0000 (UTC)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga101.jf.intel.com with ESMTP; 05 Jun 2015 09:18:57 -0700", "from catheri1-tigger.jf.intel.com ([134.134.176.92])\n\tby orsmga001.jf.intel.com with ESMTP; 05 Jun 2015 09:18:58 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.13,559,1427785200\"; d=\"scan'208\";a=\"705993652\"", "From": "Catherine Sullivan <catherine.sullivan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Fri, 5 Jun 2015 12:20:29 -0400", "Message-Id": "<1433521234-33355-6-git-send-email-catherine.sullivan@intel.com>", "X-Mailer": "git-send-email 1.9.3", "In-Reply-To": "<1433521234-33355-1-git-send-email-catherine.sullivan@intel.com>", "References": "<1433521234-33355-1-git-send-email-catherine.sullivan@intel.com>", "Cc": "Anjali Singhai Jain <anjali.singhai@intel.com>", "Subject": "[Intel-wired-lan] [intel-wired-lan][net-next PATCH S07 05/10]\n\ti40e/i40evf: RSS changes for X722", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "From: Anjali Singhai Jain <anjali.singhai@intel.com>\n\nX722 uses the admin queue to configure RSS. This patch adds the necessary\nflow changes to configure RSS through AQ. It also adds the separate VMDQ2\nlookup tables and hash key programming for X722.\n\nX722 also exposes a different set of PCTYPES for RSS, this patch\naccommodates those changes.\n\nSigned-off-by: Anjali Singhai Jain <anjali.singhai@intel.com>\nSigned-off-by: Catherine Sullivan <catherine.sullivan@intel.com>\n---\n drivers/net/ethernet/intel/i40e/i40e.h | 7 +-\n drivers/net/ethernet/intel/i40e/i40e_main.c | 156 ++++++++++++++-----\n drivers/net/ethernet/intel/i40e/i40e_txrx.h | 12 ++\n drivers/net/ethernet/intel/i40e/i40e_type.h | 15 +-\n drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c | 11 +-\n drivers/net/ethernet/intel/i40evf/i40e_txrx.h | 12 ++\n drivers/net/ethernet/intel/i40evf/i40e_type.h | 15 +-\n drivers/net/ethernet/intel/i40evf/i40evf.h | 2 +\n drivers/net/ethernet/intel/i40evf/i40evf_main.c | 166 ++++++++++++++++-----\n 9 files changed, 307 insertions(+), 89 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e.h b/drivers/net/ethernet/intel/i40e/i40e.h\nindex 7bfb471..756c382 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e.h\n@@ -79,10 +79,13 @@\n #define I40E_MIN_MSIX 2\n #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */\n #define I40E_MIN_VSI_ALLOC 51 /* LAN, ATR, FCOE, 32 VF, 16 VMDQ */\n-#define I40E_DEFAULT_QUEUES_PER_VMDQ 2 /* max 16 qps */\n+/* max 16 qps */\n+#define i40e_default_queues_per_vmdq(pf) \\\n+\t (((pf)->flags & I40E_FLAG_RSS_AQ_CAPABLE) ? 4 : 1)\n #define I40E_DEFAULT_QUEUES_PER_VF 4\n #define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */\n-#define I40E_MAX_QUEUES_PER_TC 64 /* should be a power of 2 */\n+#define i40e_pf_get_max_q_per_tc(pf) \\\n+\t\t(((pf)->flags & I40E_FLAG_128_QP_RSS_CAPABLE) ? 128 : 64)\n #define I40E_FDIR_RING 0\n #define I40E_FDIR_RING_COUNT 32\n #ifdef I40E_FCOE\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c\nindex bb454cc..2959fdc 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_main.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_main.c\n@@ -1550,7 +1550,7 @@ static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,\n \t */\n \tqcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);\n \tnum_tc_qps = qcount / numtc;\n-\tnum_tc_qps = min_t(int, num_tc_qps, I40E_MAX_QUEUES_PER_TC);\n+\tnum_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf));\n \n \t/* Setup queue offset/count for all TCs for given VSI */\n \tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {\n@@ -7465,62 +7465,139 @@ static int i40e_setup_misc_vector(struct i40e_pf *pf)\n }\n \n /**\n- * i40e_config_rss - Prepare for RSS if used\n+ * i40e_config_rss_aq - Prepare for RSS using AQ commands\n+ * @vsi: vsi structure\n+ * @seed: RSS hash seed\n+ **/\n+static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed)\n+{\n+\tstruct i40e_aqc_get_set_rss_key_data rss_key;\n+\tstruct i40e_pf *pf = vsi->back;\n+\tstruct i40e_hw *hw = &pf->hw;\n+\tbool pf_lut = false;\n+\tu8 *rss_lut;\n+\tint ret, i;\n+\n+\tmemset(&rss_key, 0, sizeof(rss_key));\n+\tmemcpy(&rss_key, seed, sizeof(rss_key));\n+\n+\trss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL);\n+\tif (!rss_lut)\n+\t\treturn -ENOMEM;\n+\n+\t/* Populate the LUT with max no. of queues in round robin fashion */\n+\tfor (i = 0; i < vsi->rss_table_size; i++)\n+\t\trss_lut[i] = i % vsi->rss_size;\n+\n+\tret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key);\n+\tif (ret) {\n+\t\tdev_info(&pf->pdev->dev,\n+\t\t\t \"Cannot set RSS key, err %s aq_err %s\\n\",\n+\t\t\t i40e_stat_str(&pf->hw, ret),\n+\t\t\t i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));\n+\t\treturn ret;\n+\t}\n+\n+\tif (vsi->type == I40E_VSI_MAIN)\n+\t\tpf_lut = true;\n+\n+\tret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut,\n+\t\t\t\t vsi->rss_table_size);\n+\tif (ret)\n+\t\tdev_info(&pf->pdev->dev,\n+\t\t\t \"Cannot set RSS lut, err %s aq_err %s\\n\",\n+\t\t\t i40e_stat_str(&pf->hw, ret),\n+\t\t\t i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));\n+\n+\treturn ret;\n+}\n+\n+/**\n+ * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used\n+ * @vsi: VSI structure\n+ **/\n+static int i40e_vsi_config_rss(struct i40e_vsi *vsi)\n+{\n+\tu8 seed[I40E_HKEY_ARRAY_SIZE];\n+\tstruct i40e_pf *pf = vsi->back;\n+\n+\tnetdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);\n+\tvsi->rss_size = min_t(int, pf->rss_size, vsi->num_queue_pairs);\n+\n+\tif (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)\n+\t\treturn i40e_config_rss_aq(vsi, seed);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * i40e_config_rss_reg - Prepare for RSS if used\n * @pf: board private structure\n+ * @seed: RSS hash seed\n **/\n-static int i40e_config_rss(struct i40e_pf *pf)\n+static int i40e_config_rss_reg(struct i40e_pf *pf, const u8 *seed)\n {\n-\tu32 rss_key[I40E_PFQF_HKEY_MAX_INDEX + 1];\n \tstruct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];\n \tstruct i40e_hw *hw = &pf->hw;\n+\tu32 *seed_dw = (u32 *)seed;\n+\tu32 current_queue = 0;\n \tu32 lut = 0;\n \tint i, j;\n-\tu64 hena;\n-\tu32 reg_val;\n \n-\tnetdev_rss_key_fill(rss_key, sizeof(rss_key));\n+\t/* Fill out hash function seed */\n \tfor (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)\n-\t\twr32(hw, I40E_PFQF_HKEY(i), rss_key[i]);\n+\t\twr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]);\n+\n+\tfor (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) {\n+\t\tlut = 0;\n+\t\tfor (j = 0; j < 4; j++) {\n+\t\t\tif (current_queue == vsi->rss_size)\n+\t\t\t\tcurrent_queue = 0;\n+\t\t\tlut |= ((current_queue) << (8 * j));\n+\t\t\tcurrent_queue++;\n+\t\t}\n+\t\twr32(&pf->hw, I40E_PFQF_HLUT(i), lut);\n+\t}\n+\ti40e_flush(hw);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * i40e_config_rss - Prepare for RSS if used\n+ * @pf: board private structure\n+ **/\n+static int i40e_config_rss(struct i40e_pf *pf)\n+{\n+\tstruct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];\n+\tu8 seed[I40E_HKEY_ARRAY_SIZE];\n+\tstruct i40e_hw *hw = &pf->hw;\n+\tu32 reg_val;\n+\tu64 hena;\n+\n+\tnetdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);\n \n \t/* By default we enable TCP/UDP with IPv4/IPv6 ptypes */\n \thena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |\n \t\t((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);\n-\thena |= I40E_DEFAULT_RSS_HENA;\n+\thena |= i40e_pf_get_default_rss_hena(pf);\n+\n \twr32(hw, I40E_PFQF_HENA(0), (u32)hena);\n \twr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));\n \n \tvsi->rss_size = min_t(int, pf->rss_size, vsi->num_queue_pairs);\n \n-\t/* Check capability and Set table size and register per hw expectation*/\n+\t/* Determine the RSS table size based on the hardware capabilities */\n \treg_val = rd32(hw, I40E_PFQF_CTL_0);\n-\tif (pf->rss_table_size == 512)\n-\t\treg_val |= I40E_PFQF_CTL_0_HASHLUTSIZE_512;\n-\telse\n-\t\treg_val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_512;\n+\treg_val = (pf->rss_table_size == 512) ?\n+\t\t\t(reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :\n+\t\t\t(reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);\n \twr32(hw, I40E_PFQF_CTL_0, reg_val);\n \n-\t/* Populate the LUT with max no. of queues in round robin fashion */\n-\tfor (i = 0, j = 0; i < pf->rss_table_size; i++, j++) {\n-\n-\t\t/* The assumption is that lan qp count will be the highest\n-\t\t * qp count for any PF VSI that needs RSS.\n-\t\t * If multiple VSIs need RSS support, all the qp counts\n-\t\t * for those VSIs should be a power of 2 for RSS to work.\n-\t\t * If LAN VSI is the only consumer for RSS then this requirement\n-\t\t * is not necessary.\n-\t\t */\n-\t\tif (j == vsi->rss_size)\n-\t\t\tj = 0;\n-\t\t/* lut = 4-byte sliding window of 4 lut entries */\n-\t\tlut = (lut << 8) | (j &\n-\t\t\t (BIT(pf->hw.func_caps.rss_table_entry_width) - 1));\n-\t\t/* On i = 3, we have 4 entries in lut; write to the register */\n-\t\tif ((i & 3) == 3)\n-\t\t\twr32(hw, I40E_PFQF_HLUT(i >> 2), lut);\n-\t}\n-\ti40e_flush(hw);\n-\n-\treturn 0;\n+\tif (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)\n+\t\treturn i40e_config_rss_aq(pf->vsi[pf->lan_vsi], seed);\n+\telse\n+\t\treturn i40e_config_rss_reg(pf, seed);\n }\n \n /**\n@@ -7761,9 +7838,8 @@ static int i40e_sw_init(struct i40e_pf *pf)\n \t}\n \n \tif (pf->hw.func_caps.vmdq) {\n-\t\tpf->flags |= I40E_FLAG_VMDQ_ENABLED;\n \t\tpf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;\n-\t\tpf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;\n+\t\tpf->flags |= I40E_FLAG_VMDQ_ENABLED;\n \t}\n \n #ifdef I40E_FCOE\n@@ -8930,6 +9006,10 @@ struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,\n \t\tbreak;\n \t}\n \n+\tif ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&\n+\t (vsi->type == I40E_VSI_VMDQ2)) {\n+\t\tret = i40e_vsi_config_rss(vsi);\n+\t}\n \treturn vsi;\n \n err_rings:\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.h b/drivers/net/ethernet/intel/i40e/i40e_txrx.h\nindex 429833c..8b618d0 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_txrx.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.h\n@@ -78,6 +78,18 @@ enum i40e_dyn_idx_t {\n \tBIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \\\n \tBIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD))\n \n+#define I40E_DEFAULT_RSS_HENA_EXPANDED (I40E_DEFAULT_RSS_HENA | \\\n+\tBIT(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \\\n+\tBIT(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \\\n+\tBIT(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \\\n+\tBIT(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \\\n+\tBIT(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \\\n+\tBIT(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))\n+\n+#define i40e_pf_get_default_rss_hena(pf) \\\n+\t(((pf)->flags & I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE) ? \\\n+\t I40E_DEFAULT_RSS_HENA_EXPANDED : I40E_DEFAULT_RSS_HENA)\n+\n /* Supported Rx Buffer Sizes */\n #define I40E_RXBUFFER_512 512 /* Used for packet split */\n #define I40E_RXBUFFER_2048 2048\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_type.h b/drivers/net/ethernet/intel/i40e/i40e_type.h\nindex 778266f..1ffd271 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_type.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_type.h\n@@ -973,15 +973,24 @@ struct i40e_filter_program_desc {\n \n /* Packet Classifier Types for filters */\n enum i40e_filter_pctype {\n-\t/* Note: Values 0-30 are reserved for future use */\n+\t/* Note: Values 0-28 are reserved for future use.\n+\t * Value 29, 30, 32 are not supported on XL710 and X710.\n+\t */\n+\tI40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP\t= 29,\n+\tI40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP\t= 30,\n \tI40E_FILTER_PCTYPE_NONF_IPV4_UDP\t\t= 31,\n-\t/* Note: Value 32 is reserved for future use */\n+\tI40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK\t= 32,\n \tI40E_FILTER_PCTYPE_NONF_IPV4_TCP\t\t= 33,\n \tI40E_FILTER_PCTYPE_NONF_IPV4_SCTP\t\t= 34,\n \tI40E_FILTER_PCTYPE_NONF_IPV4_OTHER\t\t= 35,\n \tI40E_FILTER_PCTYPE_FRAG_IPV4\t\t\t= 36,\n-\t/* Note: Values 37-40 are reserved for future use */\n+\t/* Note: Values 37-38 are reserved for future use.\n+\t * Value 39, 40, 42 are not supported on XL710 and X710.\n+\t */\n+\tI40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP\t= 39,\n+\tI40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP\t= 40,\n \tI40E_FILTER_PCTYPE_NONF_IPV6_UDP\t\t= 41,\n+\tI40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK\t= 42,\n \tI40E_FILTER_PCTYPE_NONF_IPV6_TCP\t\t= 43,\n \tI40E_FILTER_PCTYPE_NONF_IPV6_SCTP\t\t= 44,\n \tI40E_FILTER_PCTYPE_NONF_IPV6_OTHER\t\t= 45,\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c\nindex 8c14ef6..4a84808 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c\n@@ -1169,9 +1169,14 @@ static int i40e_vc_get_vf_resources_msg(struct i40e_vf *vf, u8 *msg)\n \tvfres->vf_offload_flags = I40E_VIRTCHNL_VF_OFFLOAD_L2;\n \tvsi = pf->vsi[vf->lan_vsi_idx];\n \tif (!vsi->info.pvid)\n-\t\tvfres->vf_offload_flags |= I40E_VIRTCHNL_VF_OFFLOAD_VLAN |\n-\t\t\t\t\t I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG;\n-\n+\t\tvfres->vf_offload_flags |= I40E_VIRTCHNL_VF_OFFLOAD_VLAN;\n+\tif (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {\n+\t\tif (vf->driver_caps & I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ)\n+\t\t\tvfres->vf_offload_flags |=\n+\t\t\t\tI40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ;\n+\t} else {\n+\t\tvfres->vf_offload_flags |= I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG;\n+\t}\n \tvfres->num_vsis = num_vsis;\n \tvfres->num_queue_pairs = vf->num_queue_pairs;\n \tvfres->max_vectors = pf->hw.func_caps.num_msix_vectors_vf;\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.h b/drivers/net/ethernet/intel/i40evf/i40e_txrx.h\nindex 6b47c81..b2f9b82 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_txrx.h\n@@ -78,6 +78,18 @@ enum i40e_dyn_idx_t {\n \tBIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \\\n \tBIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD))\n \n+#define I40E_DEFAULT_RSS_HENA_EXPANDED (I40E_DEFAULT_RSS_HENA | \\\n+\t\tBIT(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \\\n+\t\tBIT(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \\\n+\t\tBIT(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \\\n+\t\tBIT(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \\\n+\t\tBIT(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \\\n+\t\tBIT(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))\n+\n+#define i40e_pf_get_default_rss_hena(pf) \\\n+\t(((pf)->flags & I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE) ? \\\n+\t\tI40E_DEFAULT_RSS_HENA_EXPANDED : I40E_DEFAULT_RSS_HENA)\n+\n /* Supported Rx Buffer Sizes */\n #define I40E_RXBUFFER_512 512 /* Used for packet split */\n #define I40E_RXBUFFER_2048 2048\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_type.h b/drivers/net/ethernet/intel/i40evf/i40e_type.h\nindex c50536b..627bf76 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_type.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_type.h\n@@ -967,15 +967,24 @@ struct i40e_filter_program_desc {\n \n /* Packet Classifier Types for filters */\n enum i40e_filter_pctype {\n-\t/* Note: Values 0-30 are reserved for future use */\n+\t/* Note: Values 0-28 are reserved for future use.\n+\t * Value 29, 30, 32 are not supported on XL710 and X710.\n+\t */\n+\tI40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP\t= 29,\n+\tI40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP\t= 30,\n \tI40E_FILTER_PCTYPE_NONF_IPV4_UDP\t\t= 31,\n-\t/* Note: Value 32 is reserved for future use */\n+\tI40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK\t= 32,\n \tI40E_FILTER_PCTYPE_NONF_IPV4_TCP\t\t= 33,\n \tI40E_FILTER_PCTYPE_NONF_IPV4_SCTP\t\t= 34,\n \tI40E_FILTER_PCTYPE_NONF_IPV4_OTHER\t\t= 35,\n \tI40E_FILTER_PCTYPE_FRAG_IPV4\t\t\t= 36,\n-\t/* Note: Values 37-40 are reserved for future use */\n+\t/* Note: Values 37-38 are reserved for future use.\n+\t * Value 39, 40, 42 are not supported on XL710 and X710.\n+\t */\n+\tI40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP\t= 39,\n+\tI40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP\t= 40,\n \tI40E_FILTER_PCTYPE_NONF_IPV6_UDP\t\t= 41,\n+\tI40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK\t= 42,\n \tI40E_FILTER_PCTYPE_NONF_IPV6_TCP\t\t= 43,\n \tI40E_FILTER_PCTYPE_NONF_IPV6_SCTP\t\t= 44,\n \tI40E_FILTER_PCTYPE_NONF_IPV6_OTHER\t\t= 45,\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40evf.h b/drivers/net/ethernet/intel/i40evf/i40evf.h\nindex a12f80e2..ef7a86d 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40evf.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40evf.h\n@@ -101,6 +101,8 @@ struct i40e_vsi {\n #define MAX_RX_QUEUES 8\n #define MAX_TX_QUEUES MAX_RX_QUEUES\n \n+#define I40EVF_HKEY_ARRAY_SIZE ((I40E_VFQF_HKEY_MAX_INDEX + 1) * 4)\n+\n /* MAX_MSIX_Q_VECTORS of these are allocated,\n * but we only use one per queue-specific vector.\n */\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40evf_main.c b/drivers/net/ethernet/intel/i40evf/i40evf_main.c\nindex ecb7f90..ce8626b 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40evf_main.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40evf_main.c\n@@ -1172,6 +1172,113 @@ out:\n }\n \n /**\n+ * i40e_configure_rss_aq - Prepare for RSS using AQ commands\n+ * @vsi: vsi structure\n+ * @seed: RSS hash seed\n+ **/\n+static void i40evf_configure_rss_aq(struct i40e_vsi *vsi, const u8 *seed)\n+{\n+\tstruct i40e_aqc_get_set_rss_key_data rss_key;\n+\tstruct i40evf_adapter *adapter = vsi->back;\n+\tstruct i40e_hw *hw = &adapter->hw;\n+\tint ret = 0, i;\n+\tu8 *rss_lut;\n+\n+\tif (!vsi->id)\n+\t\treturn;\n+\n+\tif (adapter->current_op != I40E_VIRTCHNL_OP_UNKNOWN) {\n+\t\t/* bail because we already have a command pending */\n+\t\tdev_err(&adapter->pdev->dev, \"Cannot confiure RSS, command %d pending\\n\",\n+\t\t\tadapter->current_op);\n+\t\treturn;\n+\t}\n+\n+\tmemset(&rss_key, 0, sizeof(rss_key));\n+\tmemcpy(&rss_key, seed, sizeof(rss_key));\n+\n+\trss_lut = kzalloc(((I40E_VFQF_HLUT_MAX_INDEX + 1) * 4), GFP_KERNEL);\n+\tif (!rss_lut)\n+\t\treturn;\n+\n+\t/* Populate the LUT with max no. of queues in round robin fashion */\n+\tfor (i = 0; i <= (I40E_VFQF_HLUT_MAX_INDEX * 4); i++)\n+\t\trss_lut[i] = i % adapter->vsi_res->num_queue_pairs;\n+\n+\tret = i40evf_aq_set_rss_key(hw, vsi->id, &rss_key);\n+\tif (ret) {\n+\t\tdev_err(&adapter->pdev->dev,\n+\t\t\t\"Cannot set RSS key, err %s aq_err %s\\n\",\n+\t\t\ti40evf_stat_str(hw, ret),\n+\t\t\ti40evf_aq_str(hw, hw->aq.asq_last_status));\n+\t\treturn;\n+\t}\n+\n+\tret = i40evf_aq_set_rss_lut(hw, vsi->id, false, rss_lut,\n+\t\t\t\t (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4);\n+\tif (ret)\n+\t\tdev_err(&adapter->pdev->dev,\n+\t\t\t\"Cannot set RSS lut, err %s aq_err %s\\n\",\n+\t\t\ti40evf_stat_str(hw, ret),\n+\t\t\ti40evf_aq_str(hw, hw->aq.asq_last_status));\n+}\n+\n+/**\n+ * i40e_configure_rss_reg - Prepare for RSS if used\n+ * @adapter: board private structure\n+ * @seed: RSS hash seed\n+ **/\n+static void i40evf_configure_rss_reg(struct i40evf_adapter *adapter,\n+\t\t\t\t const u8 *seed)\n+{\n+\tstruct i40e_hw *hw = &adapter->hw;\n+\tu32 *seed_dw = (u32 *)seed;\n+\tu32 cqueue = 0;\n+\tu32 lut = 0;\n+\tint i, j;\n+\n+\t/* Fill out hash function seed */\n+\tfor (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)\n+\t\twr32(hw, I40E_VFQF_HKEY(i), seed_dw[i]);\n+\n+\t/* Populate the LUT with max no. of queues in round robin fashion */\n+\tfor (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++) {\n+\t\tlut = 0;\n+\t\tfor (j = 0; j < 4; j++) {\n+\t\t\tif (cqueue == adapter->vsi_res->num_queue_pairs)\n+\t\t\t\tcqueue = 0;\n+\t\t\tlut |= ((cqueue) << (8 * j));\n+\t\t\tcqueue++;\n+\t\t}\n+\t\twr32(hw, I40E_VFQF_HLUT(i), lut);\n+\t}\n+\ti40e_flush(hw);\n+}\n+\n+/**\n+ * i40evf_configure_rss - Prepare for RSS\n+ * @adapter: board private structure\n+ **/\n+static void i40evf_configure_rss(struct i40evf_adapter *adapter)\n+{\n+\tstruct i40e_hw *hw = &adapter->hw;\n+\tu8 seed[I40EVF_HKEY_ARRAY_SIZE];\n+\tu64 hena;\n+\n+\tnetdev_rss_key_fill((void *)seed, I40EVF_HKEY_ARRAY_SIZE);\n+\n+\t/* Enable PCTYPES for RSS, TCP/UDP with IPv4/IPv6 */\n+\thena = I40E_DEFAULT_RSS_HENA;\n+\twr32(hw, I40E_VFQF_HENA(0), (u32)hena);\n+\twr32(hw, I40E_VFQF_HENA(1), (u32)(hena >> 32));\n+\n+\tif (RSS_AQ(adapter))\n+\t\ti40evf_configure_rss_aq(&adapter->vsi, seed);\n+\telse\n+\t\ti40evf_configure_rss_reg(adapter, seed);\n+}\n+\n+/**\n * i40evf_alloc_q_vectors - Allocate memory for interrupt vectors\n * @adapter: board private structure to initialize\n *\n@@ -1416,6 +1523,16 @@ static void i40evf_watchdog_task(struct work_struct *work)\n \t\tgoto watchdog_done;\n \t}\n \n+\tif (adapter->aq_required & I40EVF_FLAG_AQ_CONFIGURE_RSS) {\n+\t\t/* This message goes straight to the firmware, not the\n+\t\t * PF, so we don't have to set current_op as we will\n+\t\t * not get a response through the ARQ.\n+\t\t */\n+\t\ti40evf_configure_rss(adapter);\n+\t\tadapter->aq_required &= ~I40EVF_FLAG_AQ_CONFIGURE_RSS;\n+\t\tgoto watchdog_done;\n+\t}\n+\n \tif (adapter->state == __I40EVF_RUNNING)\n \t\ti40evf_request_stats(adapter);\n watchdog_done:\n@@ -1438,45 +1555,6 @@ restart_watchdog:\n \tschedule_work(&adapter->adminq_task);\n }\n \n-/**\n- * i40evf_configure_rss - Prepare for RSS\n- * @adapter: board private structure\n- **/\n-static void i40evf_configure_rss(struct i40evf_adapter *adapter)\n-{\n-\tu32 rss_key[I40E_VFQF_HKEY_MAX_INDEX + 1];\n-\tstruct i40e_hw *hw = &adapter->hw;\n-\tu32 cqueue = 0;\n-\tu32 lut = 0;\n-\tint i, j;\n-\tu64 hena;\n-\n-\t/* Hash type is configured by the PF - we just supply the key */\n-\tnetdev_rss_key_fill(rss_key, sizeof(rss_key));\n-\n-\t/* Fill out hash function seed */\n-\tfor (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)\n-\t\twr32(hw, I40E_VFQF_HKEY(i), rss_key[i]);\n-\n-\t/* Enable PCTYPES for RSS, TCP/UDP with IPv4/IPv6 */\n-\thena = I40E_DEFAULT_RSS_HENA;\n-\twr32(hw, I40E_VFQF_HENA(0), (u32)hena);\n-\twr32(hw, I40E_VFQF_HENA(1), (u32)(hena >> 32));\n-\n-\t/* Populate the LUT with max no. of queues in round robin fashion */\n-\tfor (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++) {\n-\t\tlut = 0;\n-\t\tfor (j = 0; j < 4; j++) {\n-\t\t\tif (cqueue == adapter->vsi_res->num_queue_pairs)\n-\t\t\t\tcqueue = 0;\n-\t\t\tlut |= ((cqueue) << (8 * j));\n-\t\t\tcqueue++;\n-\t\t}\n-\t\twr32(hw, I40E_VFQF_HLUT(i), lut);\n-\t}\n-\ti40e_flush(hw);\n-}\n-\n #define I40EVF_RESET_WAIT_MS 100\n #define I40EVF_RESET_WAIT_COUNT 200\n /**\n@@ -2204,7 +2282,8 @@ static void i40evf_init_task(struct work_struct *work)\n \tif (err)\n \t\tgoto err_sw_init;\n \ti40evf_map_rings_to_vectors(adapter);\n-\ti40evf_configure_rss(adapter);\n+\tif (!RSS_AQ(adapter))\n+\t\ti40evf_configure_rss(adapter);\n \terr = i40evf_request_misc_irq(adapter);\n \tif (err)\n \t\tgoto err_sw_init;\n@@ -2229,6 +2308,13 @@ static void i40evf_init_task(struct work_struct *work)\n \tadapter->state = __I40EVF_DOWN;\n \tset_bit(__I40E_DOWN, &adapter->vsi.state);\n \ti40evf_misc_irq_enable(adapter);\n+\n+\tif (RSS_AQ(adapter)) {\n+\t\tadapter->aq_required |= I40EVF_FLAG_AQ_CONFIGURE_RSS;\n+\t\tmod_timer_pending(&adapter->watchdog_timer, jiffies + 1);\n+\t} else {\n+\t\ti40evf_configure_rss(adapter);\n+\t}\n \treturn;\n restart:\n \tschedule_delayed_work(&adapter->init_task,\n", "prefixes": [ "net-next", "S07", "05/10" ] }