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GET /api/patches/481469/?format=api
{ "id": 481469, "url": "http://patchwork.ozlabs.org/api/patches/481469/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1433521234-33355-11-git-send-email-catherine.sullivan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1433521234-33355-11-git-send-email-catherine.sullivan@intel.com>", "list_archive_url": null, "date": "2015-06-05T16:20:34", "name": "[net-next,S07,10/10] i40e: Add AQ commands for NVM Update for X722", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "c182c64bdfe712ff9d1bbb8cd05971c39b0dcfc1", "submitter": { "id": 13931, "url": "http://patchwork.ozlabs.org/api/people/13931/?format=api", "name": "Catherine Sullivan", "email": "catherine.sullivan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1433521234-33355-11-git-send-email-catherine.sullivan@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/481469/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/481469/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from fraxinus.osuosl.org (fraxinus.osuosl.org [140.211.166.137])\n\tby ozlabs.org (Postfix) with ESMTP id 6CAA41402AD\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 6 Jun 2015 02:19:36 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id BA211A395D;\n\tFri, 5 Jun 2015 16:19:35 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 0Ijv0JyqVWqL; Fri, 5 Jun 2015 16:19:31 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 2A9B2A3954;\n\tFri, 5 Jun 2015 16:19:31 +0000 (UTC)", "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\tby ash.osuosl.org (Postfix) with ESMTP id D8CB01C1FC8\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 5 Jun 2015 16:19:29 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id D4DBD9181B\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 5 Jun 2015 16:19:29 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 1Aha7yK1uVa5 for <intel-wired-lan@lists.osuosl.org>;\n\tFri, 5 Jun 2015 16:19:29 +0000 (UTC)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 1E3F99181E\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 5 Jun 2015 16:19:29 +0000 (UTC)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga101.jf.intel.com with ESMTP; 05 Jun 2015 09:19:01 -0700", "from catheri1-tigger.jf.intel.com ([134.134.176.92])\n\tby orsmga001.jf.intel.com with ESMTP; 05 Jun 2015 09:19:01 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.13,559,1427785200\"; d=\"scan'208\";a=\"705993693\"", "From": "Catherine Sullivan <catherine.sullivan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Fri, 5 Jun 2015 12:20:34 -0400", "Message-Id": "<1433521234-33355-11-git-send-email-catherine.sullivan@intel.com>", "X-Mailer": "git-send-email 1.9.3", "In-Reply-To": "<1433521234-33355-1-git-send-email-catherine.sullivan@intel.com>", "References": "<1433521234-33355-1-git-send-email-catherine.sullivan@intel.com>", "Subject": "[Intel-wired-lan] [intel-wired-lan][net-next PATCH S07 10/10] i40e:\n\tAdd AQ commands for NVM Update for X722", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "From: Shannon Nelson <shannon.nelson@intel.com>\n\nX722 does NVM update via the adminq queue, so we need to add support for\nthat.\n\nSigned-off-by: Shannon Nelson <shannon.nelson@intel.com>\nSigned-off-by: Catherine Sullivan <catherine.sullivan@intel.com>\n---\n drivers/net/ethernet/intel/i40e/i40e_nvm.c | 129 +++++++++++++++++++++++++++++\n 1 file changed, 129 insertions(+)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_nvm.c b/drivers/net/ethernet/intel/i40e/i40e_nvm.c\nindex ce986af..9b83abc 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_nvm.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_nvm.c\n@@ -212,6 +212,74 @@ read_nvm_exit:\n }\n \n /**\n+ * i40e_read_nvm_aq - Read Shadow RAM.\n+ * @hw: pointer to the HW structure.\n+ * @module_pointer: module pointer location in words from the NVM beginning\n+ * @offset: offset in words from module start\n+ * @words: number of words to write\n+ * @data: buffer with words to write to the Shadow RAM\n+ * @last_command: tells the AdminQ that this is the last command\n+ *\n+ * Writes a 16 bit words buffer to the Shadow RAM using the admin command.\n+ **/\n+static i40e_status i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,\n+\t\t\t\t u32 offset, u16 words, void *data,\n+\t\t\t\t bool last_command)\n+{\n+\ti40e_status ret_code = I40E_ERR_NVM;\n+\tstruct i40e_asq_cmd_details cmd_details;\n+\n+\tmemset(&cmd_details, 0, sizeof(cmd_details));\n+\n+\t/* Here we are checking the SR limit only for the flat memory model.\n+\t * We cannot do it for the module-based model, as we did not acquire\n+\t * the NVM resource yet (we cannot get the module pointer value).\n+\t * Firmware will check the module-based model.\n+\t */\n+\tif ((offset + words) > hw->nvm.sr_size)\n+\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n+\t\t\t \"NVM write error: offset %d beyond Shadow RAM limit %d\\n\",\n+\t\t\t (offset + words), hw->nvm.sr_size);\n+\telse if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)\n+\t\t/* We can write only up to 4KB (one sector), in one AQ write */\n+\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n+\t\t\t \"NVM write fail error: tried to write %d words, limit is %d.\\n\",\n+\t\t\t words, I40E_SR_SECTOR_SIZE_IN_WORDS);\n+\telse if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)\n+\t\t != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))\n+\t\t/* A single write cannot spread over two sectors */\n+\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n+\t\t\t \"NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\\n\",\n+\t\t\t offset, words);\n+\telse\n+\t\tret_code = i40e_aq_read_nvm(hw, module_pointer,\n+\t\t\t\t\t 2 * offset, /*bytes*/\n+\t\t\t\t\t 2 * words, /*bytes*/\n+\t\t\t\t\t data, last_command, &cmd_details);\n+\n+\treturn ret_code;\n+}\n+\n+/**\n+ * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ\n+ * @hw: pointer to the HW structure\n+ * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n+ * @data: word read from the Shadow RAM\n+ *\n+ * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.\n+ **/\n+static i40e_status i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,\n+\t\t\t\t\t u16 *data)\n+{\n+\ti40e_status ret_code = I40E_ERR_TIMEOUT;\n+\n+\tret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, true);\n+\t*data = le16_to_cpu(*(__le16 *)data);\n+\n+\treturn ret_code;\n+}\n+\n+/**\n * i40e_read_nvm_word - Reads Shadow RAM\n * @hw: pointer to the HW structure\n * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n@@ -222,6 +290,8 @@ read_nvm_exit:\n i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,\n \t\t\t u16 *data)\n {\n+\tif (hw->mac.type == I40E_MAC_X722)\n+\t\treturn i40e_read_nvm_word_aq(hw, offset, data);\n \treturn i40e_read_nvm_word_srctl(hw, offset, data);\n }\n \n@@ -257,6 +327,63 @@ static i40e_status i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,\n }\n \n /**\n+ * i40e_read_nvm_buffer_aq - Reads Shadow RAM buffer via AQ\n+ * @hw: pointer to the HW structure\n+ * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).\n+ * @words: (in) number of words to read; (out) number of words actually read\n+ * @data: words read from the Shadow RAM\n+ *\n+ * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq()\n+ * method. The buffer read is preceded by the NVM ownership take\n+ * and followed by the release.\n+ **/\n+static i40e_status i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,\n+\t\t\t\t\t u16 *words, u16 *data)\n+{\n+\ti40e_status ret_code;\n+\tu16 read_size = *words;\n+\tbool last_cmd = false;\n+\tu16 words_read = 0;\n+\tu16 i = 0;\n+\n+\tdo {\n+\t\t/* Calculate number of bytes we should read in this step.\n+\t\t * FVL AQ do not allow to read more than one page at a time or\n+\t\t * to cross page boundaries.\n+\t\t */\n+\t\tif (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)\n+\t\t\tread_size = min(*words,\n+\t\t\t\t\t(u16)(I40E_SR_SECTOR_SIZE_IN_WORDS -\n+\t\t\t\t (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)));\n+\t\telse\n+\t\t\tread_size = min((*words - words_read),\n+\t\t\t\t\tI40E_SR_SECTOR_SIZE_IN_WORDS);\n+\n+\t\t/* Check if this is last command, if so set proper flag */\n+\t\tif ((words_read + read_size) >= *words)\n+\t\t\tlast_cmd = true;\n+\n+\t\tret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size,\n+\t\t\t\t\t data + words_read, last_cmd);\n+\t\tif (ret_code)\n+\t\t\tgoto read_nvm_buffer_aq_exit;\n+\n+\t\t/* Increment counter for words already read and move offset to\n+\t\t * new read location\n+\t\t */\n+\t\twords_read += read_size;\n+\t\toffset += read_size;\n+\t} while (words_read < *words);\n+\n+\tfor (i = 0; i < *words; i++)\n+\t\tdata[i] = le16_to_cpu(((__le16 *)data)[i]);\n+\n+read_nvm_buffer_aq_exit:\n+\t*words = words_read;\n+\treturn ret_code;\n+}\n+\n+/**\n * i40e_read_nvm_buffer - Reads Shadow RAM buffer\n * @hw: pointer to the HW structure\n * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).\n@@ -270,6 +397,8 @@ static i40e_status i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,\n i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,\n \t\t\t\t u16 *words, u16 *data)\n {\n+\tif (hw->mac.type == I40E_MAC_X722)\n+\t\treturn i40e_read_nvm_buffer_aq(hw, offset, words, data);\n \treturn i40e_read_nvm_buffer_srctl(hw, offset, words, data);\n }\n \n", "prefixes": [ "net-next", "S07", "10/10" ] }