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GET /api/patches/481464/?format=api
{ "id": 481464, "url": "http://patchwork.ozlabs.org/api/patches/481464/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1433521234-33355-4-git-send-email-catherine.sullivan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1433521234-33355-4-git-send-email-catherine.sullivan@intel.com>", "list_archive_url": null, "date": "2015-06-05T16:20:27", "name": "[net-next,S07,03/10] i40e/i40evf: Update FW API with X722 support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "691257871752847547742f6f9e83bfb1362eea4a", "submitter": { "id": 13931, "url": "http://patchwork.ozlabs.org/api/people/13931/?format=api", "name": "Catherine Sullivan", "email": "catherine.sullivan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1433521234-33355-4-git-send-email-catherine.sullivan@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/481464/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/481464/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from fraxinus.osuosl.org (fraxinus.osuosl.org [140.211.166.137])\n\tby ozlabs.org (Postfix) with ESMTP id 804BE1402A9\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 6 Jun 2015 02:19:00 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id C9EC9A38C3;\n\tFri, 5 Jun 2015 16:18:59 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id lpTKUTZzMaOW; Fri, 5 Jun 2015 16:18:58 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 6DAD9A38AD;\n\tFri, 5 Jun 2015 16:18:58 +0000 (UTC)", "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ash.osuosl.org (Postfix) with ESMTP id 2FB391C1FC8\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 5 Jun 2015 16:18:57 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 2C51B96566\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 5 Jun 2015 16:18:57 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id VuTVhGZbOBa4 for <intel-wired-lan@lists.osuosl.org>;\n\tFri, 5 Jun 2015 16:18:56 +0000 (UTC)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 181F096556\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 5 Jun 2015 16:18:56 +0000 (UTC)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga101.jf.intel.com with ESMTP; 05 Jun 2015 09:18:56 -0700", "from catheri1-tigger.jf.intel.com ([134.134.176.92])\n\tby orsmga001.jf.intel.com with ESMTP; 05 Jun 2015 09:18:56 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.13,559,1427785200\"; d=\"scan'208\";a=\"705993640\"", "From": "Catherine Sullivan <catherine.sullivan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Fri, 5 Jun 2015 12:20:27 -0400", "Message-Id": "<1433521234-33355-4-git-send-email-catherine.sullivan@intel.com>", "X-Mailer": "git-send-email 1.9.3", "In-Reply-To": "<1433521234-33355-1-git-send-email-catherine.sullivan@intel.com>", "References": "<1433521234-33355-1-git-send-email-catherine.sullivan@intel.com>", "Cc": "Anjali Singhai Jain <anjali.singhai@intel.com>", "Subject": "[Intel-wired-lan] [intel-wired-lan][net-next PATCH S07 03/10]\n\ti40e/i40evf: Update FW API with X722 support", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "From: Anjali Singhai Jain <anjali.singhai@intel.com>\n\nThis patch does the firmware API update to support the new X722 device.\n\nSigned-off-by: Anjali Singhai Jain <anjali.singhai@intel.com>\nSigned-off-by: Catherine Sullivan <catherine.sullivan@intel.com>\n---\n drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h | 48 ++++++\n drivers/net/ethernet/intel/i40e/i40e_common.c | 163 +++++++++++++++++++++\n drivers/net/ethernet/intel/i40e/i40e_prototype.h | 11 ++\n .../net/ethernet/intel/i40evf/i40e_adminq_cmd.h | 49 ++++++-\n drivers/net/ethernet/intel/i40evf/i40e_common.c | 163 +++++++++++++++++++++\n drivers/net/ethernet/intel/i40evf/i40e_prototype.h | 11 ++\n 6 files changed, 444 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h\nindex 9101f5c..95d23bf 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h\n@@ -257,6 +257,10 @@ enum i40e_admin_queue_opc {\n \t/* Tunnel commands */\n \ti40e_aqc_opc_add_udp_tunnel\t= 0x0B00,\n \ti40e_aqc_opc_del_udp_tunnel\t= 0x0B01,\n+\ti40e_aqc_opc_set_rss_key\t= 0x0B02,\n+\ti40e_aqc_opc_set_rss_lut\t= 0x0B03,\n+\ti40e_aqc_opc_get_rss_key\t= 0x0B04,\n+\ti40e_aqc_opc_get_rss_lut\t= 0x0B05,\n \n \t/* Async Events */\n \ti40e_aqc_opc_event_lan_overflow\t\t= 0x1001,\n@@ -821,8 +825,12 @@ struct i40e_aqc_vsi_properties_data {\n \t\t\t\t\t I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)\n \t/* queueing option section */\n \tu8\tqueueing_opt_flags;\n+#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA\t0x04\n+#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA\t0x08\n #define I40E_AQ_VSI_QUE_OPT_TCP_ENA\t0x10\n #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA\t0x20\n+#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF\t0x00\n+#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI\t0x40\n \tu8\tqueueing_opt_reserved[3];\n \t/* scheduler section */\n \tu8\tup_enable_bits;\n@@ -2179,6 +2187,46 @@ struct i40e_aqc_del_udp_tunnel_completion {\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);\n \n+struct i40e_aqc_get_set_rss_key {\n+#define I40E_AQC_SET_RSS_KEY_VSI_VALID\t\t(0x1 << 15)\n+#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT\t0\n+#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK\t(0x3FF << \\\n+\t\t\t\t\tI40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)\n+\t__le16\tvsi_id;\n+\tu8\treserved[6];\n+\t__le32\taddr_high;\n+\t__le32\taddr_low;\n+};\n+\n+I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);\n+\n+struct i40e_aqc_get_set_rss_key_data {\n+\tu8 standard_rss_key[0x28];\n+\tu8 extended_hash_key[0xc];\n+};\n+\n+I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);\n+\n+struct i40e_aqc_get_set_rss_lut {\n+#define I40E_AQC_SET_RSS_LUT_VSI_VALID\t\t(0x1 << 15)\n+#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT\t0\n+#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK\t(0x3FF << \\\n+\t\t\t\t\tI40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)\n+\t__le16\tvsi_id;\n+#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT\t0\n+#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK\t(0x1 << \\\n+\t\t\t\t\tI40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)\n+\n+#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI\t0\n+#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF\t1\n+\t__le16\tflags;\n+\tu8\treserved[4];\n+\t__le32\taddr_high;\n+\t__le32\taddr_low;\n+};\n+\n+I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);\n+\n /* tunnel key structure 0x0B10 */\n \n struct i40e_aqc_tunnel_key_structure {\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c\nindex 11ec264..114dc64 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_common.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_common.c\n@@ -392,6 +392,169 @@ i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,\n \treturn status;\n }\n \n+/**\n+ * i40e_aq_get_set_rss_lut\n+ * @hw: pointer to the hardware structure\n+ * @vsi_id: vsi fw index\n+ * @pf_lut: for PF table set true, for VSI table set false\n+ * @lut: pointer to the lut buffer provided by the caller\n+ * @lut_size: size of the lut buffer\n+ * @set: set true to set the table, false to get the table\n+ *\n+ * Internal function to get or set RSS look up table\n+ **/\n+static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,\n+\t\t\t\t\t u16 vsi_id, bool pf_lut,\n+\t\t\t\t\t u8 *lut, u16 lut_size,\n+\t\t\t\t\t bool set)\n+{\n+\ti40e_status status;\n+\tstruct i40e_aq_desc desc;\n+\tstruct i40e_aqc_get_set_rss_lut *cmd_resp =\n+\t\t (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;\n+\n+\tif (set)\n+\t\ti40e_fill_default_direct_cmd_desc(&desc,\n+\t\t\t\t\t\t i40e_aqc_opc_set_rss_lut);\n+\telse\n+\t\ti40e_fill_default_direct_cmd_desc(&desc,\n+\t\t\t\t\t\t i40e_aqc_opc_get_rss_lut);\n+\n+\t/* Indirect command */\n+\tdesc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);\n+\tdesc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);\n+\n+\tcmd_resp->vsi_id =\n+\t\t\tcpu_to_le16((u16)((vsi_id <<\n+\t\t\t\t\t I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &\n+\t\t\t\t\t I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));\n+\tcmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);\n+\n+\tif (pf_lut)\n+\t\tcmd_resp->flags |= cpu_to_le16((u16)\n+\t\t\t\t\t((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<\n+\t\t\t\t\tI40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &\n+\t\t\t\t\tI40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));\n+\telse\n+\t\tcmd_resp->flags |= cpu_to_le16((u16)\n+\t\t\t\t\t((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<\n+\t\t\t\t\tI40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &\n+\t\t\t\t\tI40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));\n+\n+\tcmd_resp->addr_high = cpu_to_le32(high_16_bits((u64)lut));\n+\tcmd_resp->addr_low = cpu_to_le32(lower_32_bits((u64)lut));\n+\n+\tstatus = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * i40e_aq_get_rss_lut\n+ * @hw: pointer to the hardware structure\n+ * @vsi_id: vsi fw index\n+ * @pf_lut: for PF table set true, for VSI table set false\n+ * @lut: pointer to the lut buffer provided by the caller\n+ * @lut_size: size of the lut buffer\n+ *\n+ * get the RSS lookup table, PF or VSI type\n+ **/\n+i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,\n+\t\t\t\tbool pf_lut, u8 *lut, u16 lut_size)\n+{\n+\treturn i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,\n+\t\t\t\t false);\n+}\n+\n+/**\n+ * i40e_aq_set_rss_lut\n+ * @hw: pointer to the hardware structure\n+ * @vsi_id: vsi fw index\n+ * @pf_lut: for PF table set true, for VSI table set false\n+ * @lut: pointer to the lut buffer provided by the caller\n+ * @lut_size: size of the lut buffer\n+ *\n+ * set the RSS lookup table, PF or VSI type\n+ **/\n+i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,\n+\t\t\t\tbool pf_lut, u8 *lut, u16 lut_size)\n+{\n+\treturn i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);\n+}\n+\n+/**\n+ * i40e_aq_get_set_rss_key\n+ * @hw: pointer to the hw struct\n+ * @vsi_id: vsi fw index\n+ * @key: pointer to key info struct\n+ * @set: set true to set the key, false to get the key\n+ *\n+ * get the RSS key per VSI\n+ **/\n+static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,\n+\t\t\t\t u16 vsi_id,\n+\t\t\t\t struct i40e_aqc_get_set_rss_key_data *key,\n+\t\t\t\t bool set)\n+{\n+\ti40e_status status;\n+\tstruct i40e_aq_desc desc;\n+\tstruct i40e_aqc_get_set_rss_key *cmd_resp =\n+\t\t\t(struct i40e_aqc_get_set_rss_key *)&desc.params.raw;\n+\tu16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);\n+\n+\tif (set)\n+\t\ti40e_fill_default_direct_cmd_desc(&desc,\n+\t\t\t\t\t\t i40e_aqc_opc_set_rss_key);\n+\telse\n+\t\ti40e_fill_default_direct_cmd_desc(&desc,\n+\t\t\t\t\t\t i40e_aqc_opc_get_rss_key);\n+\n+\t/* Indirect command */\n+\tdesc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);\n+\tdesc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);\n+\n+\tcmd_resp->vsi_id =\n+\t\t\tcpu_to_le16((u16)((vsi_id <<\n+\t\t\t\t\t I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &\n+\t\t\t\t\t I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));\n+\tcmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);\n+\tcmd_resp->addr_high = cpu_to_le32(high_16_bits((u64)key));\n+\tcmd_resp->addr_low = cpu_to_le32(lower_32_bits((u64)key));\n+\n+\tstatus = i40e_asq_send_command(hw, &desc, key, key_size, NULL);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * i40e_aq_get_rss_key\n+ * @hw: pointer to the hw struct\n+ * @vsi_id: vsi fw index\n+ * @key: pointer to key info struct\n+ *\n+ **/\n+i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,\n+\t\t\t\tu16 vsi_id,\n+\t\t\t\tstruct i40e_aqc_get_set_rss_key_data *key)\n+{\n+\treturn i40e_aq_get_set_rss_key(hw, vsi_id, key, false);\n+}\n+\n+/**\n+ * i40e_aq_set_rss_key\n+ * @hw: pointer to the hw struct\n+ * @vsi_id: vsi fw index\n+ * @key: pointer to key info struct\n+ *\n+ * set the RSS key per VSI\n+ **/\n+i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,\n+\t\t\t\tu16 vsi_id,\n+\t\t\t\tstruct i40e_aqc_get_set_rss_key_data *key)\n+{\n+\treturn i40e_aq_get_set_rss_key(hw, vsi_id, key, true);\n+}\n+\n /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the\n * hardware to a bit-field that can be used by SW to more easily determine the\n * packet type.\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_prototype.h b/drivers/net/ethernet/intel/i40e/i40e_prototype.h\nindex d52a9f7..dcb72a8 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_prototype.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_prototype.h\n@@ -61,6 +61,17 @@ i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw, bool unloading);\n char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err);\n char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err);\n \n+i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 seid,\n+\t\t\t\tbool pf_lut, u8 *lut, u16 lut_size);\n+i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 seid,\n+\t\t\t\tbool pf_lut, u8 *lut, u16 lut_size);\n+i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,\n+\t\t\t\tu16 seid,\n+\t\t\t\tstruct i40e_aqc_get_set_rss_key_data *key);\n+i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,\n+\t\t\t\tu16 seid,\n+\t\t\t\tstruct i40e_aqc_get_set_rss_key_data *key);\n+\n u32 i40e_led_get(struct i40e_hw *hw);\n void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink);\n \ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h\nindex d5bd6f0..c802209 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h\n@@ -35,7 +35,6 @@\n \n #define I40E_FW_API_VERSION_MAJOR\t0x0001\n #define I40E_FW_API_VERSION_MINOR\t0x0004\n-#define I40E_FW_API_VERSION_A0_MINOR 0x0000\n \n struct i40e_aq_desc {\n \t__le16 flags;\n@@ -255,6 +254,10 @@ enum i40e_admin_queue_opc {\n \t/* Tunnel commands */\n \ti40e_aqc_opc_add_udp_tunnel\t= 0x0B00,\n \ti40e_aqc_opc_del_udp_tunnel\t= 0x0B01,\n+\ti40e_aqc_opc_set_rss_key\t= 0x0B02,\n+\ti40e_aqc_opc_set_rss_lut\t= 0x0B03,\n+\ti40e_aqc_opc_get_rss_key\t= 0x0B04,\n+\ti40e_aqc_opc_get_rss_lut\t= 0x0B05,\n \n \t/* Async Events */\n \ti40e_aqc_opc_event_lan_overflow\t\t= 0x1001,\n@@ -819,8 +822,12 @@ struct i40e_aqc_vsi_properties_data {\n \t\t\t\t\t I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)\n \t/* queueing option section */\n \tu8\tqueueing_opt_flags;\n+#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA\t0x04\n+#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA\t0x08\n #define I40E_AQ_VSI_QUE_OPT_TCP_ENA\t0x10\n #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA\t0x20\n+#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF\t0x00\n+#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI\t0x40\n \tu8\tqueueing_opt_reserved[3];\n \t/* scheduler section */\n \tu8\tup_enable_bits;\n@@ -2089,6 +2096,46 @@ struct i40e_aqc_del_udp_tunnel_completion {\n \n I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);\n \n+struct i40e_aqc_get_set_rss_key {\n+#define I40E_AQC_SET_RSS_KEY_VSI_VALID\t\t(0x1 << 15)\n+#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT\t0\n+#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK\t(0x3FF << \\\n+\t\t\t\t\tI40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)\n+\t__le16\tvsi_id;\n+\tu8\treserved[6];\n+\t__le32\taddr_high;\n+\t__le32\taddr_low;\n+};\n+\n+I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);\n+\n+struct i40e_aqc_get_set_rss_key_data {\n+\tu8 standard_rss_key[0x28];\n+\tu8 extended_hash_key[0xc];\n+};\n+\n+I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);\n+\n+struct i40e_aqc_get_set_rss_lut {\n+#define I40E_AQC_SET_RSS_LUT_VSI_VALID\t\t(0x1 << 15)\n+#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT\t0\n+#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK\t(0x3FF << \\\n+\t\t\t\t\tI40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)\n+\t__le16\tvsi_id;\n+#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT\t0\n+#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK\t(0x1 << \\\n+\t\t\t\t\tI40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)\n+\n+#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI\t0\n+#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF\t1\n+\t__le16\tflags;\n+\tu8\treserved[4];\n+\t__le32\taddr_high;\n+\t__le32\taddr_low;\n+};\n+\n+I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);\n+\n /* tunnel key structure 0x0B10 */\n \n struct i40e_aqc_tunnel_key_structure_A0 {\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_common.c b/drivers/net/ethernet/intel/i40evf/i40e_common.c\nindex eb54e8d..023d32d 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_common.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_common.c\n@@ -392,6 +392,169 @@ i40e_status i40evf_aq_queue_shutdown(struct i40e_hw *hw,\n \treturn status;\n }\n \n+/**\n+ * i40e_aq_get_set_rss_lut\n+ * @hw: pointer to the hardware structure\n+ * @vsi_id: vsi fw index\n+ * @pf_lut: for PF table set true, for VSI table set false\n+ * @lut: pointer to the lut buffer provided by the caller\n+ * @lut_size: size of the lut buffer\n+ * @set: set true to set the table, false to get the table\n+ *\n+ * Internal function to get or set RSS look up table\n+ **/\n+static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,\n+\t\t\t\t\t u16 vsi_id, bool pf_lut,\n+\t\t\t\t\t u8 *lut, u16 lut_size,\n+\t\t\t\t\t bool set)\n+{\n+\ti40e_status status;\n+\tstruct i40e_aq_desc desc;\n+\tstruct i40e_aqc_get_set_rss_lut *cmd_resp =\n+\t\t (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;\n+\n+\tif (set)\n+\t\ti40evf_fill_default_direct_cmd_desc(&desc,\n+\t\t\t\t\t\t i40e_aqc_opc_set_rss_lut);\n+\telse\n+\t\ti40evf_fill_default_direct_cmd_desc(&desc,\n+\t\t\t\t\t\t i40e_aqc_opc_get_rss_lut);\n+\n+\t/* Indirect command */\n+\tdesc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);\n+\tdesc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);\n+\n+\tcmd_resp->vsi_id =\n+\t\t\tcpu_to_le16((u16)((vsi_id <<\n+\t\t\t\t\t I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &\n+\t\t\t\t\t I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));\n+\tcmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);\n+\n+\tif (pf_lut)\n+\t\tcmd_resp->flags |= cpu_to_le16((u16)\n+\t\t\t\t\t((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<\n+\t\t\t\t\tI40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &\n+\t\t\t\t\tI40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));\n+\telse\n+\t\tcmd_resp->flags |= cpu_to_le16((u16)\n+\t\t\t\t\t((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<\n+\t\t\t\t\tI40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &\n+\t\t\t\t\tI40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));\n+\n+\tcmd_resp->addr_high = cpu_to_le32(high_16_bits((u64)lut));\n+\tcmd_resp->addr_low = cpu_to_le32(lower_32_bits((u64)lut));\n+\n+\tstatus = i40evf_asq_send_command(hw, &desc, lut, lut_size, NULL);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * i40evf_aq_get_rss_lut\n+ * @hw: pointer to the hardware structure\n+ * @vsi_id: vsi fw index\n+ * @pf_lut: for PF table set true, for VSI table set false\n+ * @lut: pointer to the lut buffer provided by the caller\n+ * @lut_size: size of the lut buffer\n+ *\n+ * get the RSS lookup table, PF or VSI type\n+ **/\n+i40e_status i40evf_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,\n+\t\t\t\t bool pf_lut, u8 *lut, u16 lut_size)\n+{\n+\treturn i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,\n+\t\t\t\t false);\n+}\n+\n+/**\n+ * i40evf_aq_set_rss_lut\n+ * @hw: pointer to the hardware structure\n+ * @vsi_id: vsi fw index\n+ * @pf_lut: for PF table set true, for VSI table set false\n+ * @lut: pointer to the lut buffer provided by the caller\n+ * @lut_size: size of the lut buffer\n+ *\n+ * set the RSS lookup table, PF or VSI type\n+ **/\n+i40e_status i40evf_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,\n+\t\t\t\t bool pf_lut, u8 *lut, u16 lut_size)\n+{\n+\treturn i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);\n+}\n+\n+/**\n+ * i40e_aq_get_set_rss_key\n+ * @hw: pointer to the hw struct\n+ * @vsi_id: vsi fw index\n+ * @key: pointer to key info struct\n+ * @set: set true to set the key, false to get the key\n+ *\n+ * get the RSS key per VSI\n+ **/\n+static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,\n+\t\t\t\t u16 vsi_id,\n+\t\t\t\t struct i40e_aqc_get_set_rss_key_data *key,\n+\t\t\t\t bool set)\n+{\n+\ti40e_status status;\n+\tstruct i40e_aq_desc desc;\n+\tstruct i40e_aqc_get_set_rss_key *cmd_resp =\n+\t\t\t(struct i40e_aqc_get_set_rss_key *)&desc.params.raw;\n+\tu16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);\n+\n+\tif (set)\n+\t\ti40evf_fill_default_direct_cmd_desc(&desc,\n+\t\t\t\t\t\t i40e_aqc_opc_set_rss_key);\n+\telse\n+\t\ti40evf_fill_default_direct_cmd_desc(&desc,\n+\t\t\t\t\t\t i40e_aqc_opc_get_rss_key);\n+\n+\t/* Indirect command */\n+\tdesc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);\n+\tdesc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);\n+\n+\tcmd_resp->vsi_id =\n+\t\t\tcpu_to_le16((u16)((vsi_id <<\n+\t\t\t\t\t I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &\n+\t\t\t\t\t I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));\n+\tcmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);\n+\tcmd_resp->addr_high = cpu_to_le32(high_16_bits((u64)key));\n+\tcmd_resp->addr_low = cpu_to_le32(lower_32_bits((u64)key));\n+\n+\tstatus = i40evf_asq_send_command(hw, &desc, key, key_size, NULL);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * i40evf_aq_get_rss_key\n+ * @hw: pointer to the hw struct\n+ * @vsi_id: vsi fw index\n+ * @key: pointer to key info struct\n+ *\n+ **/\n+i40e_status i40evf_aq_get_rss_key(struct i40e_hw *hw,\n+\t\t\t\t u16 vsi_id,\n+\t\t\t\t struct i40e_aqc_get_set_rss_key_data *key)\n+{\n+\treturn i40e_aq_get_set_rss_key(hw, vsi_id, key, false);\n+}\n+\n+/**\n+ * i40evf_aq_set_rss_key\n+ * @hw: pointer to the hw struct\n+ * @vsi_id: vsi fw index\n+ * @key: pointer to key info struct\n+ *\n+ * set the RSS key per VSI\n+ **/\n+i40e_status i40evf_aq_set_rss_key(struct i40e_hw *hw,\n+\t\t\t\t u16 vsi_id,\n+\t\t\t\t struct i40e_aqc_get_set_rss_key_data *key)\n+{\n+\treturn i40e_aq_get_set_rss_key(hw, vsi_id, key, true);\n+}\n+\n \n /* The i40evf_ptype_lookup table is used to convert from the 8-bit ptype in the\n * hardware to a bit-field that can be used by SW to more easily determine the\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_prototype.h b/drivers/net/ethernet/intel/i40evf/i40e_prototype.h\nindex 856eb9d..55ae4b0 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_prototype.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_prototype.h\n@@ -63,6 +63,17 @@ i40e_status i40evf_aq_queue_shutdown(struct i40e_hw *hw, bool unloading);\n char *i40evf_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err);\n char *i40evf_stat_str(struct i40e_hw *hw, i40e_status stat_err);\n \n+i40e_status i40evf_aq_get_rss_lut(struct i40e_hw *hw, u16 seid,\n+\t\t\t\t bool pf_lut, u8 *lut, u16 lut_size);\n+i40e_status i40evf_aq_set_rss_lut(struct i40e_hw *hw, u16 seid,\n+\t\t\t\t bool pf_lut, u8 *lut, u16 lut_size);\n+i40e_status i40evf_aq_get_rss_key(struct i40e_hw *hw,\n+\t\t\t\t u16 seid,\n+\t\t\t\t struct i40e_aqc_get_set_rss_key_data *key);\n+i40e_status i40evf_aq_set_rss_key(struct i40e_hw *hw,\n+\t\t\t\t u16 seid,\n+\t\t\t\t struct i40e_aqc_get_set_rss_key_data *key);\n+\n i40e_status i40e_set_mac_type(struct i40e_hw *hw);\n \n extern struct i40e_rx_ptype_decoded i40evf_ptype_lookup[];\n", "prefixes": [ "net-next", "S07", "03/10" ] }