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GET /api/patches/480881/?format=api
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{
    "id": 480881,
    "url": "http://patchwork.ozlabs.org/api/patches/480881/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1433449442-31420-9-git-send-email-catherine.sullivan@intel.com/",
    "project": {
        "id": 46,
        "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api",
        "name": "Intel Wired Ethernet development",
        "link_name": "intel-wired-lan",
        "list_id": "intel-wired-lan.osuosl.org",
        "list_email": "intel-wired-lan@osuosl.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<1433449442-31420-9-git-send-email-catherine.sullivan@intel.com>",
    "list_archive_url": null,
    "date": "2015-06-04T20:24:02",
    "name": "[net-next,8/8] i40e: use BIT and BIT_ULL macros",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "65963b9632ca13088b37982c427c887fed2dbe1b",
    "submitter": {
        "id": 13931,
        "url": "http://patchwork.ozlabs.org/api/people/13931/?format=api",
        "name": "Catherine Sullivan",
        "email": "catherine.sullivan@intel.com"
    },
    "delegate": {
        "id": 68,
        "url": "http://patchwork.ozlabs.org/api/users/68/?format=api",
        "username": "jtkirshe",
        "first_name": "Jeff",
        "last_name": "Kirsher",
        "email": "jeffrey.t.kirsher@intel.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1433449442-31420-9-git-send-email-catherine.sullivan@intel.com/mbox/",
    "series": [],
    "comments": "http://patchwork.ozlabs.org/api/patches/480881/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/480881/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>",
        "X-Original-To": [
            "incoming@patchwork.ozlabs.org",
            "intel-wired-lan@lists.osuosl.org"
        ],
        "Delivered-To": [
            "patchwork-incoming@bilbo.ozlabs.org",
            "intel-wired-lan@lists.osuosl.org"
        ],
        "Received": [
            "from hemlock.osuosl.org (hemlock.osuosl.org [140.211.166.133])\n\tby ozlabs.org (Postfix) with ESMTP id 88A4A14018C\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri,  5 Jun 2015 06:42:47 +1000 (AEST)",
            "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 938DB964F2;\n\tThu,  4 Jun 2015 20:42:46 +0000 (UTC)",
            "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 1ddC6M6cASy1; Thu,  4 Jun 2015 20:42:43 +0000 (UTC)",
            "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 23D2B964CB;\n\tThu,  4 Jun 2015 20:42:43 +0000 (UTC)",
            "from silver.osuosl.org (silver.osuosl.org [140.211.166.136])\n\tby ash.osuosl.org (Postfix) with ESMTP id E0F631C1F3C\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu,  4 Jun 2015 20:22:33 +0000 (UTC)",
            "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id B22F532A8E\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu,  4 Jun 2015 20:22:33 +0000 (UTC)",
            "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id UyaFPxb2Wxle for <intel-wired-lan@lists.osuosl.org>;\n\tThu,  4 Jun 2015 20:22:28 +0000 (UTC)",
            "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby silver.osuosl.org (Postfix) with ESMTP id DD3F732C8A\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu,  4 Jun 2015 20:22:27 +0000 (UTC)",
            "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby fmsmga103.fm.intel.com with ESMTP; 04 Jun 2015 13:22:27 -0700",
            "from catheri1-tigger.jf.intel.com ([134.134.176.92])\n\tby orsmga001.jf.intel.com with ESMTP; 04 Jun 2015 13:22:27 -0700"
        ],
        "X-Virus-Scanned": [
            "amavisd-new at osuosl.org",
            "amavisd-new at osuosl.org"
        ],
        "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.13,554,1427785200\"; d=\"scan'208\";a=\"705514398\"",
        "From": "Catherine Sullivan <catherine.sullivan@intel.com>",
        "To": "intel-wired-lan@lists.osuosl.org",
        "Date": "Thu,  4 Jun 2015 16:24:02 -0400",
        "Message-Id": "<1433449442-31420-9-git-send-email-catherine.sullivan@intel.com>",
        "X-Mailer": "git-send-email 1.9.3",
        "In-Reply-To": "<1433449442-31420-1-git-send-email-catherine.sullivan@intel.com>",
        "References": "<1433449442-31420-1-git-send-email-catherine.sullivan@intel.com>",
        "X-Mailman-Approved-At": "Thu, 04 Jun 2015 20:42:41 +0000",
        "Subject": "[Intel-wired-lan] [intel-wired-lan][net-next PATCH 8/8] i40e: use\n\tBIT and BIT_ULL macros",
        "X-BeenThere": "intel-wired-lan@lists.osuosl.org",
        "X-Mailman-Version": "2.1.18-1",
        "Precedence": "list",
        "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>",
        "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>",
        "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>",
        "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>",
        "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>",
        "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain; charset=\"us-ascii\"",
        "Content-Transfer-Encoding": "7bit",
        "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org",
        "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>"
    },
    "content": "From: Jesse Brandeburg <jesse.brandeburg@intel.com>\n\nUse macros for abstracting (1 << foo) to BIT(foo)\nand (1ULL << foo64) to BIT_ULL(foo64) in order to match\nbetter with kernel requirements.\n\nNOTE: the adminq_cmd.h file was not modified on purpose because\nof the dependency upon firmware for that file.\n\nSigned-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>\nSigned-off-by: Catherine Sullivan <catherine.sullivan@intel.com>\nChange-ID: I73ee2e48c880d671948aad19bd53ca6b2ac558fc\n---\n drivers/net/ethernet/intel/i40e/i40e.h             | 56 ++++++++--------\n drivers/net/ethernet/intel/i40e/i40e_common.c      |  4 +-\n drivers/net/ethernet/intel/i40e/i40e_dcb.h         |  8 +--\n drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c      |  2 +-\n drivers/net/ethernet/intel/i40e/i40e_debugfs.c     | 10 +--\n drivers/net/ethernet/intel/i40e/i40e_diag.c        | 11 ++--\n drivers/net/ethernet/intel/i40e/i40e_ethtool.c     | 54 ++++++++--------\n drivers/net/ethernet/intel/i40e/i40e_fcoe.c        | 12 ++--\n drivers/net/ethernet/intel/i40e/i40e_fcoe.h        |  4 +-\n drivers/net/ethernet/intel/i40e/i40e_hmc.h         |  6 +-\n drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c     | 16 ++---\n drivers/net/ethernet/intel/i40e/i40e_main.c        | 75 +++++++++++-----------\n drivers/net/ethernet/intel/i40e/i40e_nvm.c         |  6 +-\n drivers/net/ethernet/intel/i40e/i40e_ptp.c         |  7 +-\n drivers/net/ethernet/intel/i40e/i40e_txrx.c        | 39 ++++++-----\n drivers/net/ethernet/intel/i40e/i40e_txrx.h        | 44 ++++++-------\n drivers/net/ethernet/intel/i40e/i40e_type.h        | 22 +++----\n drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c | 18 +++---\n drivers/net/ethernet/intel/i40evf/i40e_hmc.h       |  6 +-\n drivers/net/ethernet/intel/i40evf/i40e_txrx.c      | 37 ++++++-----\n drivers/net/ethernet/intel/i40evf/i40e_txrx.h      | 42 ++++++------\n drivers/net/ethernet/intel/i40evf/i40e_type.h      | 22 +++----\n drivers/net/ethernet/intel/i40evf/i40evf.h         | 42 ++++++------\n drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c | 44 ++++++-------\n drivers/net/ethernet/intel/i40evf/i40evf_main.c    |  8 +--\n .../net/ethernet/intel/i40evf/i40evf_virtchnl.c    |  4 +-\n 26 files changed, 294 insertions(+), 305 deletions(-)",
    "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e.h b/drivers/net/ethernet/intel/i40e/i40e.h\nindex aca9cef..8b4dec9 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e.h\n@@ -98,7 +98,7 @@\n #define I40E_INT_NAME_STR_LEN        (IFNAMSIZ + 9)\n \n /* Ethtool Private Flags */\n-#define I40E_PRIV_FLAGS_NPAR_FLAG\t(1 << 0)\n+#define I40E_PRIV_FLAGS_NPAR_FLAG\tBIT(0)\n \n #define I40E_NVM_VERSION_LO_SHIFT  0\n #define I40E_NVM_VERSION_LO_MASK   (0xff << I40E_NVM_VERSION_LO_SHIFT)\n@@ -289,35 +289,35 @@ struct i40e_pf {\n \tstruct work_struct service_task;\n \n \tu64 flags;\n-#define I40E_FLAG_RX_CSUM_ENABLED              (u64)(1 << 1)\n-#define I40E_FLAG_MSI_ENABLED                  (u64)(1 << 2)\n-#define I40E_FLAG_MSIX_ENABLED                 (u64)(1 << 3)\n-#define I40E_FLAG_RX_1BUF_ENABLED              (u64)(1 << 4)\n-#define I40E_FLAG_RX_PS_ENABLED                (u64)(1 << 5)\n-#define I40E_FLAG_RSS_ENABLED                  (u64)(1 << 6)\n-#define I40E_FLAG_VMDQ_ENABLED                 (u64)(1 << 7)\n-#define I40E_FLAG_FDIR_REQUIRES_REINIT         (u64)(1 << 8)\n-#define I40E_FLAG_NEED_LINK_UPDATE             (u64)(1 << 9)\n+#define I40E_FLAG_RX_CSUM_ENABLED              BIT_ULL(1)\n+#define I40E_FLAG_MSI_ENABLED                  BIT_ULL(2)\n+#define I40E_FLAG_MSIX_ENABLED                 BIT_ULL(3)\n+#define I40E_FLAG_RX_1BUF_ENABLED              BIT_ULL(4)\n+#define I40E_FLAG_RX_PS_ENABLED                BIT_ULL(5)\n+#define I40E_FLAG_RSS_ENABLED                  BIT_ULL(6)\n+#define I40E_FLAG_VMDQ_ENABLED                 BIT_ULL(7)\n+#define I40E_FLAG_FDIR_REQUIRES_REINIT         BIT_ULL(8)\n+#define I40E_FLAG_NEED_LINK_UPDATE             BIT_ULL(9)\n #ifdef I40E_FCOE\n-#define I40E_FLAG_FCOE_ENABLED                 (u64)(1 << 11)\n+#define I40E_FLAG_FCOE_ENABLED                 BIT_ULL(11)\n #endif /* I40E_FCOE */\n-#define I40E_FLAG_IN_NETPOLL                   (u64)(1 << 12)\n-#define I40E_FLAG_16BYTE_RX_DESC_ENABLED       (u64)(1 << 13)\n-#define I40E_FLAG_CLEAN_ADMINQ                 (u64)(1 << 14)\n-#define I40E_FLAG_FILTER_SYNC                  (u64)(1 << 15)\n-#define I40E_FLAG_PROCESS_MDD_EVENT            (u64)(1 << 17)\n-#define I40E_FLAG_PROCESS_VFLR_EVENT           (u64)(1 << 18)\n-#define I40E_FLAG_SRIOV_ENABLED                (u64)(1 << 19)\n-#define I40E_FLAG_DCB_ENABLED                  (u64)(1 << 20)\n-#define I40E_FLAG_FD_SB_ENABLED                (u64)(1 << 21)\n-#define I40E_FLAG_FD_ATR_ENABLED               (u64)(1 << 22)\n-#define I40E_FLAG_PTP                          (u64)(1 << 25)\n-#define I40E_FLAG_MFP_ENABLED                  (u64)(1 << 26)\n+#define I40E_FLAG_IN_NETPOLL                   BIT_ULL(12)\n+#define I40E_FLAG_16BYTE_RX_DESC_ENABLED       BIT_ULL(13)\n+#define I40E_FLAG_CLEAN_ADMINQ                 BIT_ULL(14)\n+#define I40E_FLAG_FILTER_SYNC                  BIT_ULL(15)\n+#define I40E_FLAG_PROCESS_MDD_EVENT            BIT_ULL(17)\n+#define I40E_FLAG_PROCESS_VFLR_EVENT           BIT_ULL(18)\n+#define I40E_FLAG_SRIOV_ENABLED                BIT_ULL(19)\n+#define I40E_FLAG_DCB_ENABLED                  BIT_ULL(20)\n+#define I40E_FLAG_FD_SB_ENABLED                BIT_ULL(21)\n+#define I40E_FLAG_FD_ATR_ENABLED               BIT_ULL(22)\n+#define I40E_FLAG_PTP                          BIT_ULL(25)\n+#define I40E_FLAG_MFP_ENABLED                  BIT_ULL(26)\n #ifdef CONFIG_I40E_VXLAN\n-#define I40E_FLAG_VXLAN_FILTER_SYNC            (u64)(1 << 27)\n+#define I40E_FLAG_VXLAN_FILTER_SYNC            BIT_ULL(27)\n #endif\n-#define I40E_FLAG_PORT_ID_VALID                (u64)(1 << 28)\n-#define I40E_FLAG_DCB_CAPABLE                  (u64)(1 << 29)\n+#define I40E_FLAG_PORT_ID_VALID                BIT_ULL(28)\n+#define I40E_FLAG_DCB_CAPABLE                  BIT_ULL(29)\n \n \t/* tracks features that get auto disabled by errors */\n \tu64 auto_disable_flags;\n@@ -442,8 +442,8 @@ struct i40e_vsi {\n \n \tu32 current_netdev_flags;\n \tunsigned long state;\n-#define I40E_VSI_FLAG_FILTER_CHANGED  (1<<0)\n-#define I40E_VSI_FLAG_VEB_OWNER       (1<<1)\n+#define I40E_VSI_FLAG_FILTER_CHANGED\tBIT(0)\n+#define I40E_VSI_FLAG_VEB_OWNER\t\tBIT(1)\n \tunsigned long flags;\n \n \tstruct list_head mac_filter_list;\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c\nindex 8f2ecbe..167ca0d 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_common.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_common.c\n@@ -1393,9 +1393,9 @@ void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)\n \t\t\tblink = false;\n \n \t\tif (blink)\n-\t\t\tgpio_val |= (1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);\n+\t\t\tgpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);\n \t\telse\n-\t\t\tgpio_val &= ~(1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);\n+\t\t\tgpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);\n \n \t\twr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);\n \t\tbreak;\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_dcb.h b/drivers/net/ethernet/intel/i40e/i40e_dcb.h\nindex e137e3f..50fc894 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_dcb.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_dcb.h\n@@ -58,9 +58,9 @@\n #define I40E_IEEE_ETS_MAXTC_SHIFT\t0\n #define I40E_IEEE_ETS_MAXTC_MASK\t(0x7 << I40E_IEEE_ETS_MAXTC_SHIFT)\n #define I40E_IEEE_ETS_CBS_SHIFT\t\t6\n-#define I40E_IEEE_ETS_CBS_MASK\t\t(0x1 << I40E_IEEE_ETS_CBS_SHIFT)\n+#define I40E_IEEE_ETS_CBS_MASK\t\tBIT(I40E_IEEE_ETS_CBS_SHIFT)\n #define I40E_IEEE_ETS_WILLING_SHIFT\t7\n-#define I40E_IEEE_ETS_WILLING_MASK\t(0x1 << I40E_IEEE_ETS_WILLING_SHIFT)\n+#define I40E_IEEE_ETS_WILLING_MASK\tBIT(I40E_IEEE_ETS_WILLING_SHIFT)\n #define I40E_IEEE_ETS_PRIO_0_SHIFT\t0\n #define I40E_IEEE_ETS_PRIO_0_MASK\t(0x7 << I40E_IEEE_ETS_PRIO_0_SHIFT)\n #define I40E_IEEE_ETS_PRIO_1_SHIFT\t4\n@@ -79,9 +79,9 @@\n #define I40E_IEEE_PFC_CAP_SHIFT\t\t0\n #define I40E_IEEE_PFC_CAP_MASK\t\t(0xF << I40E_IEEE_PFC_CAP_SHIFT)\n #define I40E_IEEE_PFC_MBC_SHIFT\t\t6\n-#define I40E_IEEE_PFC_MBC_MASK\t\t(0x1 << I40E_IEEE_PFC_MBC_SHIFT)\n+#define I40E_IEEE_PFC_MBC_MASK\t\tBIT(I40E_IEEE_PFC_MBC_SHIFT)\n #define I40E_IEEE_PFC_WILLING_SHIFT\t7\n-#define I40E_IEEE_PFC_WILLING_MASK\t(0x1 << I40E_IEEE_PFC_WILLING_SHIFT)\n+#define I40E_IEEE_PFC_WILLING_MASK\tBIT(I40E_IEEE_PFC_WILLING_SHIFT)\n \n /* Defines for IEEE APP TLV */\n #define I40E_IEEE_APP_SEL_SHIFT\t\t0\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c b/drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c\nindex bd5079d..1c51f73 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c\n@@ -187,7 +187,7 @@ void i40e_dcbnl_set_all(struct i40e_vsi *vsi)\n \t/* Set up all the App TLVs if DCBx is negotiated */\n \tfor (i = 0; i < dcbxcfg->numapps; i++) {\n \t\tprio = dcbxcfg->app[i].priority;\n-\t\ttc_map = (1 << dcbxcfg->etscfg.prioritytable[prio]);\n+\t\ttc_map = BIT(dcbxcfg->etscfg.prioritytable[prio]);\n \n \t\t/* Add APP only if the TC is enabled for this VSI */\n \t\tif (tc_map & vsi->tc_config.enabled_tc) {\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_debugfs.c b/drivers/net/ethernet/intel/i40e/i40e_debugfs.c\nindex 34170ea..3bf1998 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_debugfs.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_debugfs.c\n@@ -964,7 +964,7 @@ static void i40e_dbg_cmd_fd_ctrl(struct i40e_pf *pf, u64 flag, bool enable)\n \t\tpf->auto_disable_flags |= flag;\n \t}\n \tdev_info(&pf->pdev->dev, \"requesting a PF reset\\n\");\n-\ti40e_do_reset_safe(pf, (1 << __I40E_PF_RESET_REQUESTED));\n+\ti40e_do_reset_safe(pf, BIT(__I40E_PF_RESET_REQUESTED));\n }\n \n #define I40E_MAX_DEBUG_OUT_BUFFER (4096*4)\n@@ -1462,19 +1462,19 @@ static ssize_t i40e_dbg_command_write(struct file *filp,\n \t\t}\n \t} else if (strncmp(cmd_buf, \"pfr\", 3) == 0) {\n \t\tdev_info(&pf->pdev->dev, \"debugfs: forcing PFR\\n\");\n-\t\ti40e_do_reset_safe(pf, (1 << __I40E_PF_RESET_REQUESTED));\n+\t\ti40e_do_reset_safe(pf, BIT(__I40E_PF_RESET_REQUESTED));\n \n \t} else if (strncmp(cmd_buf, \"corer\", 5) == 0) {\n \t\tdev_info(&pf->pdev->dev, \"debugfs: forcing CoreR\\n\");\n-\t\ti40e_do_reset_safe(pf, (1 << __I40E_CORE_RESET_REQUESTED));\n+\t\ti40e_do_reset_safe(pf, BIT(__I40E_CORE_RESET_REQUESTED));\n \n \t} else if (strncmp(cmd_buf, \"globr\", 5) == 0) {\n \t\tdev_info(&pf->pdev->dev, \"debugfs: forcing GlobR\\n\");\n-\t\ti40e_do_reset_safe(pf, (1 << __I40E_GLOBAL_RESET_REQUESTED));\n+\t\ti40e_do_reset_safe(pf, BIT(__I40E_GLOBAL_RESET_REQUESTED));\n \n \t} else if (strncmp(cmd_buf, \"empr\", 4) == 0) {\n \t\tdev_info(&pf->pdev->dev, \"debugfs: forcing EMPR\\n\");\n-\t\ti40e_do_reset_safe(pf, (1 << __I40E_EMP_RESET_REQUESTED));\n+\t\ti40e_do_reset_safe(pf, BIT(__I40E_EMP_RESET_REQUESTED));\n \n \t} else if (strncmp(cmd_buf, \"read\", 4) == 0) {\n \t\tu32 address;\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_diag.c b/drivers/net/ethernet/intel/i40e/i40e_diag.c\nindex 56438bd..f141e78 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_diag.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_diag.c\n@@ -144,11 +144,8 @@ i40e_status i40e_diag_eeprom_test(struct i40e_hw *hw)\n \tret_code = i40e_read_nvm_word(hw, I40E_SR_NVM_CONTROL_WORD, &reg_val);\n \tif (!ret_code &&\n \t    ((reg_val & I40E_SR_CONTROL_WORD_1_MASK) ==\n-\t     (0x01 << I40E_SR_CONTROL_WORD_1_SHIFT))) {\n-\t\tret_code = i40e_validate_nvm_checksum(hw, NULL);\n-\t} else {\n-\t\tret_code = I40E_ERR_DIAG_TEST_FAILED;\n-\t}\n-\n-\treturn ret_code;\n+\t     BIT(I40E_SR_CONTROL_WORD_1_SHIFT)))\n+\t\treturn i40e_validate_nvm_checksum(hw, NULL);\n+\telse\n+\t\treturn I40E_ERR_DIAG_TEST_FAILED;\n }\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c\nindex 4b06a27..83d41c2 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c\n@@ -1017,7 +1017,7 @@ static int i40e_get_eeprom_len(struct net_device *netdev)\n \t\t& I40E_GLPCI_LBARCTRL_FL_SIZE_MASK)\n \t\t>> I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT;\n \t/* register returns value in power of 2, 64Kbyte chunks. */\n-\tval = (64 * 1024) * (1 << val);\n+\tval = (64 * 1024) * BIT(val);\n \treturn val;\n }\n \n@@ -1470,11 +1470,11 @@ static int i40e_get_ts_info(struct net_device *dev,\n \telse\n \t\tinfo->phc_index = -1;\n \n-\tinfo->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);\n+\tinfo->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON);\n \n-\tinfo->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |\n-\t\t\t   (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |\n-\t\t\t   (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);\n+\tinfo->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |\n+\t\t\t   BIT(HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |\n+\t\t\t   BIT(HWTSTAMP_FILTER_PTP_V2_EVENT);\n \n \treturn 0;\n }\n@@ -1590,7 +1590,7 @@ static void i40e_diag_test(struct net_device *netdev,\n \t\t\t/* indicate we're in test mode */\n \t\t\tdev_close(netdev);\n \t\telse\n-\t\t\ti40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));\n+\t\t\ti40e_do_reset(pf, BIT(__I40E_PF_RESET_REQUESTED));\n \n \t\t/* Link test performed before hardware reset\n \t\t * so autoneg doesn't interfere with test result\n@@ -1612,7 +1612,7 @@ static void i40e_diag_test(struct net_device *netdev,\n \t\t\teth_test->flags |= ETH_TEST_FL_FAILED;\n \n \t\tclear_bit(__I40E_TESTING, &pf->state);\n-\t\ti40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));\n+\t\ti40e_do_reset(pf, BIT(__I40E_PF_RESET_REQUESTED));\n \n \t\tif (if_running)\n \t\t\tdev_open(netdev);\n@@ -1645,7 +1645,7 @@ static void i40e_get_wol(struct net_device *netdev,\n \n \t/* NVM bit on means WoL disabled for the port */\n \ti40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);\n-\tif ((1 << hw->port) & wol_nvm_bits || hw->partition_id != 1) {\n+\tif ((BIT(hw->port) & wol_nvm_bits) || (hw->partition_id != 1)) {\n \t\twol->supported = 0;\n \t\twol->wolopts = 0;\n \t} else {\n@@ -1678,7 +1678,7 @@ static int i40e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)\n \n \t/* NVM bit on means WoL disabled for the port */\n \ti40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);\n-\tif (((1 << hw->port) & wol_nvm_bits))\n+\tif (BIT(hw->port) & wol_nvm_bits)\n \t\treturn -EOPNOTSUPP;\n \n \t/* only magic packet is supported */\n@@ -2024,10 +2024,10 @@ static int i40e_set_rss_hash_opt(struct i40e_pf *pf, struct ethtool_rxnfc *nfc)\n \tcase TCP_V4_FLOW:\n \t\tswitch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {\n \t\tcase 0:\n-\t\t\thena &= ~((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);\n+\t\t\thena &= ~BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP);\n \t\t\tbreak;\n \t\tcase (RXH_L4_B_0_1 | RXH_L4_B_2_3):\n-\t\t\thena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);\n+\t\t\thena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP);\n \t\t\tbreak;\n \t\tdefault:\n \t\t\treturn -EINVAL;\n@@ -2036,10 +2036,10 @@ static int i40e_set_rss_hash_opt(struct i40e_pf *pf, struct ethtool_rxnfc *nfc)\n \tcase TCP_V6_FLOW:\n \t\tswitch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {\n \t\tcase 0:\n-\t\t\thena &= ~((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);\n+\t\t\thena &= ~BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP);\n \t\t\tbreak;\n \t\tcase (RXH_L4_B_0_1 | RXH_L4_B_2_3):\n-\t\t\thena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);\n+\t\t\thena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP);\n \t\t\tbreak;\n \t\tdefault:\n \t\t\treturn -EINVAL;\n@@ -2048,12 +2048,12 @@ static int i40e_set_rss_hash_opt(struct i40e_pf *pf, struct ethtool_rxnfc *nfc)\n \tcase UDP_V4_FLOW:\n \t\tswitch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {\n \t\tcase 0:\n-\t\t\thena &= ~(((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |\n-\t\t\t\t  ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4));\n+\t\t\thena &= ~(BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |\n+\t\t\t\t  BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4));\n \t\t\tbreak;\n \t\tcase (RXH_L4_B_0_1 | RXH_L4_B_2_3):\n-\t\t\thena |= (((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |\n-\t\t\t\t  ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4));\n+\t\t\thena |= (BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |\n+\t\t\t\t BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4));\n \t\t\tbreak;\n \t\tdefault:\n \t\t\treturn -EINVAL;\n@@ -2062,12 +2062,12 @@ static int i40e_set_rss_hash_opt(struct i40e_pf *pf, struct ethtool_rxnfc *nfc)\n \tcase UDP_V6_FLOW:\n \t\tswitch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {\n \t\tcase 0:\n-\t\t\thena &= ~(((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |\n-\t\t\t\t  ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6));\n+\t\t\thena &= ~(BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |\n+\t\t\t\t  BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6));\n \t\t\tbreak;\n \t\tcase (RXH_L4_B_0_1 | RXH_L4_B_2_3):\n-\t\t\thena |= (((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |\n-\t\t\t\t ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6));\n+\t\t\thena |= (BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |\n+\t\t\t\t BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6));\n \t\t\tbreak;\n \t\tdefault:\n \t\t\treturn -EINVAL;\n@@ -2080,7 +2080,7 @@ static int i40e_set_rss_hash_opt(struct i40e_pf *pf, struct ethtool_rxnfc *nfc)\n \t\tif ((nfc->data & RXH_L4_B_0_1) ||\n \t\t    (nfc->data & RXH_L4_B_2_3))\n \t\t\treturn -EINVAL;\n-\t\thena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);\n+\t\thena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);\n \t\tbreak;\n \tcase AH_ESP_V6_FLOW:\n \tcase AH_V6_FLOW:\n@@ -2089,15 +2089,15 @@ static int i40e_set_rss_hash_opt(struct i40e_pf *pf, struct ethtool_rxnfc *nfc)\n \t\tif ((nfc->data & RXH_L4_B_0_1) ||\n \t\t    (nfc->data & RXH_L4_B_2_3))\n \t\t\treturn -EINVAL;\n-\t\thena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);\n+\t\thena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);\n \t\tbreak;\n \tcase IPV4_FLOW:\n-\t\thena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) |\n-\t\t\t((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4);\n+\t\thena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) |\n+\t\t\tBIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4);\n \t\tbreak;\n \tcase IPV6_FLOW:\n-\t\thena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) |\n-\t\t\t((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6);\n+\t\thena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) |\n+\t\t\tBIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6);\n \t\tbreak;\n \tdefault:\n \t\treturn -EINVAL;\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_fcoe.c b/drivers/net/ethernet/intel/i40e/i40e_fcoe.c\nindex c8b621e..5ea75dd 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_fcoe.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_fcoe.c\n@@ -298,8 +298,8 @@ int i40e_init_pf_fcoe(struct i40e_pf *pf)\n \n \t/* enable FCoE hash filter */\n \tval = rd32(hw, I40E_PFQF_HENA(1));\n-\tval |= 1 << (I40E_FILTER_PCTYPE_FCOE_OX - 32);\n-\tval |= 1 << (I40E_FILTER_PCTYPE_FCOE_RX - 32);\n+\tval |= BIT(I40E_FILTER_PCTYPE_FCOE_OX - 32);\n+\tval |= BIT(I40E_FILTER_PCTYPE_FCOE_RX - 32);\n \tval &= I40E_PFQF_HENA_PTYPE_ENA_MASK;\n \twr32(hw, I40E_PFQF_HENA(1), val);\n \n@@ -308,10 +308,10 @@ int i40e_init_pf_fcoe(struct i40e_pf *pf)\n \tpf->num_fcoe_qps = I40E_DEFAULT_FCOE;\n \n \t/* Reserve 4K DDP contexts and 20K filter size for FCoE */\n-\tpf->fcoe_hmc_cntx_num = (1 << I40E_DMA_CNTX_SIZE_4K) *\n-\t\t\t\t I40E_DMA_CNTX_BASE_SIZE;\n+\tpf->fcoe_hmc_cntx_num = BIT(I40E_DMA_CNTX_SIZE_4K) *\n+\t\t\t\tI40E_DMA_CNTX_BASE_SIZE;\n \tpf->fcoe_hmc_filt_num = pf->fcoe_hmc_cntx_num +\n-\t\t\t\t(1 << I40E_HASH_FILTER_SIZE_16K) *\n+\t\t\t\tBIT(I40E_HASH_FILTER_SIZE_16K) *\n \t\t\t\tI40E_HASH_FILTER_BASE_SIZE;\n \n \t/* FCoE object: max 16K filter buckets and 4K DMA contexts */\n@@ -348,7 +348,7 @@ u8 i40e_get_fcoe_tc_map(struct i40e_pf *pf)\n \t\tif (app.selector == IEEE_8021QAZ_APP_SEL_ETHERTYPE &&\n \t\t    app.protocolid == ETH_P_FCOE) {\n \t\t\ttc = dcbcfg->etscfg.prioritytable[app.priority];\n-\t\t\tenabled_tc |= (1 << tc);\n+\t\t\tenabled_tc |= BIT(tc);\n \t\t\tbreak;\n \t\t}\n \t}\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_fcoe.h b/drivers/net/ethernet/intel/i40e/i40e_fcoe.h\nindex 0d49e2d..a93174d 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_fcoe.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_fcoe.h\n@@ -59,9 +59,9 @@\n \t(((e) >> I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT) & 0x1)\n \n #define I40E_RX_PROG_FCOE_ERROR_TBL_FULL_BIT\t\\\n-\t(1 << I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT)\n+\tBIT(I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT)\n #define I40E_RX_PROG_FCOE_ERROR_CONFLICT_BIT\t\\\n-\t(1 << I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT)\n+\tBIT(I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT)\n \n #define I40E_RX_PROG_FCOE_ERROR_INVLFAIL(e)\t\\\n \tI40E_RX_PROG_FCOE_ERROR_CONFLICT(e)\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_hmc.h b/drivers/net/ethernet/intel/i40e/i40e_hmc.h\nindex ba0e160..b2bacce 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_hmc.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_hmc.h\n@@ -127,8 +127,8 @@ struct i40e_hmc_info {\n \t\t I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) |\t\t\\\n \t\t((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) <<\t\t\\\n \t\tI40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT) |\t\t\t\\\n-\t\t(1 << I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT);\t\t\\\n-\tval3 = (sd_index) | (1u << I40E_PFHMC_SDCMD_PMSDWR_SHIFT);\t\\\n+\t\tBIT(I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT);\t\t\\\n+\tval3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT);\t\\\n \twr32((hw), I40E_PFHMC_SDDATAHIGH, val1);\t\t\t\\\n \twr32((hw), I40E_PFHMC_SDDATALOW, val2);\t\t\t\t\\\n \twr32((hw), I40E_PFHMC_SDCMD, val3);\t\t\t\t\\\n@@ -147,7 +147,7 @@ struct i40e_hmc_info {\n \t\tI40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) |\t\t\\\n \t\t((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) <<\t\t\\\n \t\tI40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT);\t\t\t\\\n-\tval3 = (sd_index) | (1u << I40E_PFHMC_SDCMD_PMSDWR_SHIFT);\t\\\n+\tval3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT);\t\\\n \twr32((hw), I40E_PFHMC_SDDATAHIGH, 0);\t\t\t\t\\\n \twr32((hw), I40E_PFHMC_SDDATALOW, val2);\t\t\t\t\\\n \twr32((hw), I40E_PFHMC_SDCMD, val3);\t\t\t\t\\\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c b/drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c\nindex d399eaf..fa371a2 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c\n@@ -129,7 +129,7 @@ i40e_status i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,\n \tobj->cnt = txq_num;\n \tobj->base = 0;\n \tsize_exp = rd32(hw, I40E_GLHMC_LANTXOBJSZ);\n-\tobj->size = (u64)1 << size_exp;\n+\tobj->size = BIT_ULL(size_exp);\n \n \t/* validate values requested by driver don't exceed HMC capacity */\n \tif (txq_num > obj->max_cnt) {\n@@ -152,7 +152,7 @@ i40e_status i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,\n \t\t     hw->hmc.hmc_obj[I40E_HMC_LAN_TX].size);\n \tobj->base = i40e_align_l2obj_base(obj->base);\n \tsize_exp = rd32(hw, I40E_GLHMC_LANRXOBJSZ);\n-\tobj->size = (u64)1 << size_exp;\n+\tobj->size = BIT_ULL(size_exp);\n \n \t/* validate values requested by driver don't exceed HMC capacity */\n \tif (rxq_num > obj->max_cnt) {\n@@ -175,7 +175,7 @@ i40e_status i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,\n \t\t     hw->hmc.hmc_obj[I40E_HMC_LAN_RX].size);\n \tobj->base = i40e_align_l2obj_base(obj->base);\n \tsize_exp = rd32(hw, I40E_GLHMC_FCOEDDPOBJSZ);\n-\tobj->size = (u64)1 << size_exp;\n+\tobj->size = BIT_ULL(size_exp);\n \n \t/* validate values requested by driver don't exceed HMC capacity */\n \tif (fcoe_cntx_num > obj->max_cnt) {\n@@ -198,7 +198,7 @@ i40e_status i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,\n \t\t     hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX].size);\n \tobj->base = i40e_align_l2obj_base(obj->base);\n \tsize_exp = rd32(hw, I40E_GLHMC_FCOEFOBJSZ);\n-\tobj->size = (u64)1 << size_exp;\n+\tobj->size = BIT_ULL(size_exp);\n \n \t/* validate values requested by driver don't exceed HMC capacity */\n \tif (fcoe_filt_num > obj->max_cnt) {\n@@ -763,7 +763,7 @@ static void i40e_write_byte(u8 *hmc_bits,\n \n \t/* prepare the bits and mask */\n \tshift_width = ce_info->lsb % 8;\n-\tmask = ((u8)1 << ce_info->width) - 1;\n+\tmask = BIT(ce_info->width) - 1;\n \n \tsrc_byte = *from;\n \tsrc_byte &= mask;\n@@ -804,7 +804,7 @@ static void i40e_write_word(u8 *hmc_bits,\n \n \t/* prepare the bits and mask */\n \tshift_width = ce_info->lsb % 8;\n-\tmask = ((u16)1 << ce_info->width) - 1;\n+\tmask = BIT(ce_info->width) - 1;\n \n \t/* don't swizzle the bits until after the mask because the mask bits\n \t * will be in a different bit position on big endian machines\n@@ -854,7 +854,7 @@ static void i40e_write_dword(u8 *hmc_bits,\n \t * to 5 bits so the shift will do nothing\n \t */\n \tif (ce_info->width < 32)\n-\t\tmask = ((u32)1 << ce_info->width) - 1;\n+\t\tmask = BIT(ce_info->width) - 1;\n \telse\n \t\tmask = ~(u32)0;\n \n@@ -906,7 +906,7 @@ static void i40e_write_qword(u8 *hmc_bits,\n \t * to 6 bits so the shift will do nothing\n \t */\n \tif (ce_info->width < 64)\n-\t\tmask = ((u64)1 << ce_info->width) - 1;\n+\t\tmask = BIT_ULL(ce_info->width) - 1;\n \telse\n \t\tmask = ~(u64)0;\n \ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c\nindex f694fbc..b93a517 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_main.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_main.c\n@@ -520,7 +520,7 @@ static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,\n \tif (likely(new_data >= *offset))\n \t\t*stat = new_data - *offset;\n \telse\n-\t\t*stat = (new_data + ((u64)1 << 48)) - *offset;\n+\t\t*stat = (new_data + BIT_ULL(48)) - *offset;\n \t*stat &= 0xFFFFFFFFFFFFULL;\n }\n \n@@ -543,7 +543,7 @@ static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,\n \tif (likely(new_data >= *offset))\n \t\t*stat = (u32)(new_data - *offset);\n \telse\n-\t\t*stat = (u32)((new_data + ((u64)1 << 32)) - *offset);\n+\t\t*stat = (u32)((new_data + BIT_ULL(32)) - *offset);\n }\n \n /**\n@@ -1526,7 +1526,7 @@ static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,\n \tif (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {\n \t\t/* Find numtc from enabled TC bitmap */\n \t\tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {\n-\t\t\tif (enabled_tc & (1 << i)) /* TC is enabled */\n+\t\t\tif (enabled_tc & BIT_ULL(i)) /* TC is enabled */\n \t\t\t\tnumtc++;\n \t\t}\n \t\tif (!numtc) {\n@@ -1552,7 +1552,8 @@ static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,\n \t/* Setup queue offset/count for all TCs for given VSI */\n \tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {\n \t\t/* See if the given TC is enabled for the given VSI */\n-\t\tif (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */\n+\t\tif (vsi->tc_config.enabled_tc & BIT_ULL(i)) {\n+\t\t\t/* TC is enabled */\n \t\t\tint pow, num_qps;\n \n \t\t\tswitch (vsi->type) {\n@@ -1578,7 +1579,7 @@ static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,\n \t\t\t/* find the next higher power-of-2 of num queue pairs */\n \t\t\tnum_qps = qcount;\n \t\t\tpow = 0;\n-\t\t\twhile (num_qps && ((1 << pow) < qcount)) {\n+\t\t\twhile (num_qps && (BIT_ULL(pow) < qcount)) {\n \t\t\t\tpow++;\n \t\t\t\tnum_qps >>= 1;\n \t\t\t}\n@@ -2723,9 +2724,9 @@ static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)\n #endif /* I40E_FCOE */\n \t/* round up for the chip's needs */\n \tvsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,\n-\t\t\t\t(1 << I40E_RXQ_CTX_HBUFF_SHIFT));\n+\t\t\t\tBIT_ULL(I40E_RXQ_CTX_HBUFF_SHIFT));\n \tvsi->rx_buf_len = ALIGN(vsi->rx_buf_len,\n-\t\t\t\t(1 << I40E_RXQ_CTX_DBUFF_SHIFT));\n+\t\t\t\tBIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));\n \n \t/* set up individual rings */\n \tfor (i = 0; i < vsi->num_queue_pairs && !err; i++)\n@@ -2755,7 +2756,7 @@ static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)\n \t}\n \n \tfor (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {\n-\t\tif (!(vsi->tc_config.enabled_tc & (1 << n)))\n+\t\tif (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))\n \t\t\tcontinue;\n \n \t\tqoffset = vsi->tc_config.tc_info[n].qoffset;\n@@ -4100,7 +4101,7 @@ static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)\n \t\tif (app.selector == I40E_APP_SEL_TCPIP &&\n \t\t    app.protocolid == I40E_APP_PROTOID_ISCSI) {\n \t\t\ttc = dcbcfg->etscfg.prioritytable[app.priority];\n-\t\t\tenabled_tc |= (1 << tc);\n+\t\t\tenabled_tc |= BIT_ULL(tc);\n \t\t\tbreak;\n \t\t}\n \t}\n@@ -4149,7 +4150,7 @@ static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)\n \tu8 i;\n \n \tfor (i = 0; i < num_tc; i++)\n-\t\tenabled_tc |= 1 << i;\n+\t\tenabled_tc |= BIT(i);\n \n \treturn enabled_tc;\n }\n@@ -4184,7 +4185,7 @@ static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)\n \t/* At least have TC0 */\n \tenabled_tc = (enabled_tc ? enabled_tc : 0x1);\n \tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {\n-\t\tif (enabled_tc & (1 << i))\n+\t\tif (enabled_tc & BIT_ULL(i))\n \t\t\tnum_tc++;\n \t}\n \treturn num_tc;\n@@ -4206,11 +4207,11 @@ static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)\n \n \t/* Find the first enabled TC */\n \tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {\n-\t\tif (enabled_tc & (1 << i))\n+\t\tif (enabled_tc & BIT_ULL(i))\n \t\t\tbreak;\n \t}\n \n-\treturn 1 << i;\n+\treturn BIT(i);\n }\n \n /**\n@@ -4366,7 +4367,7 @@ static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)\n \t\t * will set the numtc for netdev as 2 that will be\n \t\t * referenced by the netdev layer as TC 0 and 1.\n \t\t */\n-\t\tif (vsi->tc_config.enabled_tc & (1 << i))\n+\t\tif (vsi->tc_config.enabled_tc & BIT_ULL(i))\n \t\t\tnetdev_set_tc_queue(netdev,\n \t\t\t\t\tvsi->tc_config.tc_info[i].netdev_tc,\n \t\t\t\t\tvsi->tc_config.tc_info[i].qcount,\n@@ -4428,7 +4429,7 @@ static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)\n \n \t/* Enable ETS TCs with equal BW Share for now across all VSIs */\n \tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {\n-\t\tif (enabled_tc & (1 << i))\n+\t\tif (enabled_tc & BIT_ULL(i))\n \t\t\tbw_share[i] = 1;\n \t}\n \n@@ -4502,7 +4503,7 @@ int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)\n \n \t/* Enable ETS TCs with equal BW Share for now */\n \tfor (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {\n-\t\tif (enabled_tc & (1 << i))\n+\t\tif (enabled_tc & BIT_ULL(i))\n \t\t\tbw_data.tc_bw_share_credits[i] = 1;\n \t}\n \n@@ -4896,7 +4897,7 @@ static int i40e_setup_tc(struct net_device *netdev, u8 tc)\n \n \t/* Generate TC map for number of tc requested */\n \tfor (i = 0; i < tc; i++)\n-\t\tenabled_tc |= (1 << i);\n+\t\tenabled_tc |= BIT_ULL(i);\n \n \t/* Requesting same TC configuration as already enabled */\n \tif (enabled_tc == vsi->tc_config.enabled_tc)\n@@ -5035,7 +5036,7 @@ err_setup_rx:\n err_setup_tx:\n \ti40e_vsi_free_tx_resources(vsi);\n \tif (vsi == pf->vsi[pf->lan_vsi])\n-\t\ti40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));\n+\t\ti40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));\n \n \treturn err;\n }\n@@ -5103,7 +5104,7 @@ void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)\n \t\ti40e_vc_notify_reset(pf);\n \n \t/* do the biggest reset indicated */\n-\tif (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {\n+\tif (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {\n \n \t\t/* Request a Global Reset\n \t\t *\n@@ -5118,7 +5119,7 @@ void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)\n \t\tval |= I40E_GLGEN_RTRIG_GLOBR_MASK;\n \t\twr32(&pf->hw, I40E_GLGEN_RTRIG, val);\n \n-\t} else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {\n+\t} else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {\n \n \t\t/* Request a Core Reset\n \t\t *\n@@ -5130,7 +5131,7 @@ void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)\n \t\twr32(&pf->hw, I40E_GLGEN_RTRIG, val);\n \t\ti40e_flush(&pf->hw);\n \n-\t} else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {\n+\t} else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {\n \n \t\t/* Request a PF Reset\n \t\t *\n@@ -5143,7 +5144,7 @@ void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)\n \t\tdev_dbg(&pf->pdev->dev, \"PFR requested\\n\");\n \t\ti40e_handle_reset_warning(pf);\n \n-\t} else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {\n+\t} else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {\n \t\tint v;\n \n \t\t/* Find the VSI(s) that requested a re-init */\n@@ -5160,7 +5161,7 @@ void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)\n \n \t\t/* no further action needed, so return now */\n \t\treturn;\n-\t} else if (reset_flags & (1 << __I40E_DOWN_REQUESTED)) {\n+\t} else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {\n \t\tint v;\n \n \t\t/* Find the VSI(s) that needs to be brought down */\n@@ -5801,23 +5802,23 @@ static void i40e_reset_subtask(struct i40e_pf *pf)\n \n \trtnl_lock();\n \tif (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {\n-\t\treset_flags |= (1 << __I40E_REINIT_REQUESTED);\n+\t\treset_flags |= BIT_ULL(__I40E_REINIT_REQUESTED);\n \t\tclear_bit(__I40E_REINIT_REQUESTED, &pf->state);\n \t}\n \tif (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {\n-\t\treset_flags |= (1 << __I40E_PF_RESET_REQUESTED);\n+\t\treset_flags |= BIT_ULL(__I40E_PF_RESET_REQUESTED);\n \t\tclear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);\n \t}\n \tif (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {\n-\t\treset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);\n+\t\treset_flags |= BIT_ULL(__I40E_CORE_RESET_REQUESTED);\n \t\tclear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);\n \t}\n \tif (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {\n-\t\treset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);\n+\t\treset_flags |= BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED);\n \t\tclear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);\n \t}\n \tif (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {\n-\t\treset_flags |= (1 << __I40E_DOWN_REQUESTED);\n+\t\treset_flags |= BIT_ULL(__I40E_DOWN_REQUESTED);\n \t\tclear_bit(__I40E_DOWN_REQUESTED, &pf->state);\n \t}\n \n@@ -6695,8 +6696,8 @@ static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)\n \tpf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;\n \n \tfor (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {\n-\t\tif (pf->pending_vxlan_bitmap & (1 << i)) {\n-\t\t\tpf->pending_vxlan_bitmap &= ~(1 << i);\n+\t\tif (pf->pending_vxlan_bitmap & BIT_ULL(i)) {\n+\t\t\tpf->pending_vxlan_bitmap &= ~BIT_ULL(i);\n \t\t\tport = pf->vxlan_ports[i];\n \t\t\tif (port)\n \t\t\t\tret = i40e_aq_add_udp_tunnel(hw, ntohs(port),\n@@ -7509,7 +7510,7 @@ static int i40e_config_rss(struct i40e_pf *pf)\n \t\t\tj = 0;\n \t\t/* lut = 4-byte sliding window of 4 lut entries */\n \t\tlut = (lut << 8) | (j &\n-\t\t\t ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));\n+\t\t\t (BIT(pf->hw.func_caps.rss_table_entry_width) - 1));\n \t\t/* On i = 3, we have 4 entries in lut; write to the register */\n \t\tif ((i & 3) == 3)\n \t\t\twr32(hw, I40E_PFQF_HLUT(i >> 2), lut);\n@@ -7583,7 +7584,7 @@ i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)\n \ti40e_status status;\n \n \t/* Set the valid bit for this PF */\n-\tbw_data.pf_valid_bits = cpu_to_le16(1 << pf->hw.pf_id);\n+\tbw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));\n \tbw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;\n \tbw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;\n \n@@ -7716,7 +7717,7 @@ static int i40e_sw_init(struct i40e_pf *pf)\n \t/* Depending on PF configurations, it is possible that the RSS\n \t * maximum might end up larger than the available queues\n \t */\n-\tpf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;\n+\tpf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);\n \tpf->rss_size = 1;\n \tpf->rss_table_size = pf->hw.func_caps.rss_table_size;\n \tpf->rss_size_max = min_t(int, pf->rss_size_max,\n@@ -7866,7 +7867,7 @@ static int i40e_set_features(struct net_device *netdev,\n \tneed_reset = i40e_set_ntuple(pf, features);\n \n \tif (need_reset)\n-\t\ti40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));\n+\t\ti40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));\n \n \treturn 0;\n }\n@@ -7929,7 +7930,7 @@ static void i40e_add_vxlan_port(struct net_device *netdev,\n \n \t/* New port: add it and mark its index in the bitmap */\n \tpf->vxlan_ports[next_idx] = port;\n-\tpf->pending_vxlan_bitmap |= (1 << next_idx);\n+\tpf->pending_vxlan_bitmap |= BIT_ULL(next_idx);\n \tpf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;\n \n \tdev_info(&pf->pdev->dev, \"adding vxlan port %d\\n\", ntohs(port));\n@@ -7960,7 +7961,7 @@ static void i40e_del_vxlan_port(struct net_device *netdev,\n \t\t * and make it pending\n \t\t */\n \t\tpf->vxlan_ports[idx] = 0;\n-\t\tpf->pending_vxlan_bitmap |= (1 << idx);\n+\t\tpf->pending_vxlan_bitmap |= BIT_ULL(idx);\n \t\tpf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;\n \n \t\tdev_info(&pf->pdev->dev, \"deleting vxlan port %d\\n\",\n@@ -8096,7 +8097,7 @@ static int i40e_ndo_bridge_setlink(struct net_device *dev,\n \t\t} else if (mode != veb->bridge_mode) {\n \t\t\t/* Existing HW bridge but different mode needs reset */\n \t\t\tveb->bridge_mode = mode;\n-\t\t\ti40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));\n+\t\t\ti40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));\n \t\t\tbreak;\n \t\t}\n \t}\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_nvm.c b/drivers/net/ethernet/intel/i40e/i40e_nvm.c\nindex 554e49d..ce986af 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_nvm.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_nvm.c\n@@ -50,7 +50,7 @@ i40e_status i40e_init_nvm(struct i40e_hw *hw)\n \tsr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >>\n \t\t\t   I40E_GLNVM_GENS_SR_SIZE_SHIFT);\n \t/* Switching to words (sr_size contains power of 2KB) */\n-\tnvm->sr_size = (1 << sr_size) * I40E_SR_WORDS_IN_1KB;\n+\tnvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB;\n \n \t/* Check if we are in the normal or blank NVM programming mode */\n \tfla = rd32(hw, I40E_GLNVM_FLA);\n@@ -189,8 +189,8 @@ static i40e_status i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,\n \tret_code = i40e_poll_sr_srctl_done_bit(hw);\n \tif (!ret_code) {\n \t\t/* Write the address and start reading */\n-\t\tsr_reg = (u32)(offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |\n-\t\t\t (1 << I40E_GLNVM_SRCTL_START_SHIFT);\n+\t\tsr_reg = ((u32)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |\n+\t\t\t BIT(I40E_GLNVM_SRCTL_START_SHIFT);\n \t\twr32(hw, I40E_GLNVM_SRCTL, sr_reg);\n \n \t\t/* Poll I40E_GLNVM_SRCTL until the done bit is set */\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_ptp.c b/drivers/net/ethernet/intel/i40e/i40e_ptp.c\nindex a92b772..8c40d6e 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_ptp.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_ptp.c\n@@ -43,9 +43,8 @@\n #define I40E_PTP_10GB_INCVAL 0x0333333333ULL\n #define I40E_PTP_1GB_INCVAL  0x2000000000ULL\n \n-#define I40E_PRTTSYN_CTL1_TSYNTYPE_V1  (0x1 << \\\n-\t\t\t\t\tI40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)\n-#define I40E_PRTTSYN_CTL1_TSYNTYPE_V2  (0x2 << \\\n+#define I40E_PRTTSYN_CTL1_TSYNTYPE_V1  BIT(I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)\n+#define I40E_PRTTSYN_CTL1_TSYNTYPE_V2  (2 << \\\n \t\t\t\t\tI40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)\n \n /**\n@@ -357,7 +356,7 @@ void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index)\n \n \tprttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1);\n \n-\tif (!(prttsyn_stat & (1 << index)))\n+\tif (!(prttsyn_stat & BIT(index)))\n \t\treturn;\n \n \tlo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index));\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c\nindex ecde75b..d0339b6 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c\n@@ -464,7 +464,7 @@ static void i40e_fd_handle_status(struct i40e_ring *rx_ring,\n \terror = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>\n \t\tI40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;\n \n-\tif (error == (0x1 << I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {\n+\tif (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {\n \t\tif ((rx_desc->wb.qword0.hi_dword.fd_id != 0) ||\n \t\t    (I40E_DEBUG_FD & pf->hw.debug_mask))\n \t\t\tdev_warn(&pdev->dev, \"ntuple filter loc = %d, could not be added\\n\",\n@@ -509,8 +509,7 @@ static void i40e_fd_handle_status(struct i40e_ring *rx_ring,\n \t\t\tdev_info(&pdev->dev,\n \t\t\t\t\"FD filter programming failed due to incorrect filter parameters\\n\");\n \t\t}\n-\t} else if (error ==\n-\t\t\t  (0x1 << I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {\n+\t} else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {\n \t\tif (I40E_DEBUG_FD & pf->hw.debug_mask)\n \t\t\tdev_info(&pdev->dev, \"ntuple filter fd_id = %d, could not be removed\\n\",\n \t\t\t\t rx_desc->wb.qword0.hi_dword.fd_id);\n@@ -1363,7 +1362,7 @@ static inline void i40e_rx_checksum(struct i40e_vsi *vsi,\n \t\treturn;\n \n \t/* did the hardware decode the packet and checksum? */\n-\tif (!(rx_status & (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT)))\n+\tif (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))\n \t\treturn;\n \n \t/* both known and outer_ip must be set for the below code to work */\n@@ -1378,25 +1377,25 @@ static inline void i40e_rx_checksum(struct i40e_vsi *vsi,\n \t\tipv6 = true;\n \n \tif (ipv4 &&\n-\t    (rx_error & ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT) |\n-\t\t\t (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT))))\n+\t    (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |\n+\t\t\t BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))\n \t\tgoto checksum_fail;\n \n \t/* likely incorrect csum if alternate IP extension headers found */\n \tif (ipv6 &&\n-\t    rx_status & (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))\n+\t    rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))\n \t\t/* don't increment checksum err here, non-fatal err */\n \t\treturn;\n \n \t/* there was some L4 error, count error and punt packet to the stack */\n-\tif (rx_error & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT))\n+\tif (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))\n \t\tgoto checksum_fail;\n \n \t/* handle packets that were not able to be checksummed due\n \t * to arrival speed, in this case the stack can compute\n \t * the csum.\n \t */\n-\tif (rx_error & (1 << I40E_RX_DESC_ERROR_PPRS_SHIFT))\n+\tif (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))\n \t\treturn;\n \n \t/* If VXLAN traffic has an outer UDPv4 checksum we need to check\n@@ -1520,7 +1519,7 @@ static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)\n \t\trx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>\n \t\t\tI40E_RXD_QW1_STATUS_SHIFT;\n \n-\t\tif (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))\n+\t\tif (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))\n \t\t\tbreak;\n \n \t\t/* This memory barrier is needed to keep us from reading\n@@ -1561,8 +1560,8 @@ static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)\n \n \t\trx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>\n \t\t\t   I40E_RXD_QW1_ERROR_SHIFT;\n-\t\trx_hbo = rx_error & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT);\n-\t\trx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);\n+\t\trx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);\n+\t\trx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);\n \n \t\trx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>\n \t\t\t   I40E_RXD_QW1_PTYPE_SHIFT;\n@@ -1614,7 +1613,7 @@ static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)\n \t\tI40E_RX_INCREMENT(rx_ring, i);\n \n \t\tif (unlikely(\n-\t\t    !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {\n+\t\t    !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {\n \t\t\tstruct i40e_rx_buffer *next_buffer;\n \n \t\t\tnext_buffer = &rx_ring->rx_bi[i];\n@@ -1624,7 +1623,7 @@ static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)\n \t\t}\n \n \t\t/* ERR_MASK will only have valid bits if EOP set */\n-\t\tif (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {\n+\t\tif (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {\n \t\t\tdev_kfree_skb_any(skb);\n \t\t\tcontinue;\n \t\t}\n@@ -1646,7 +1645,7 @@ static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)\n \n \t\ti40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);\n \n-\t\tvlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)\n+\t\tvlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)\n \t\t\t ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)\n \t\t\t : 0;\n #ifdef I40E_FCOE\n@@ -1707,7 +1706,7 @@ static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)\n \t\trx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>\n \t\t\tI40E_RXD_QW1_STATUS_SHIFT;\n \n-\t\tif (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))\n+\t\tif (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))\n \t\t\tbreak;\n \n \t\t/* This memory barrier is needed to keep us from reading\n@@ -1730,7 +1729,7 @@ static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)\n \n \t\trx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>\n \t\t\t   I40E_RXD_QW1_ERROR_SHIFT;\n-\t\trx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);\n+\t\trx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);\n \n \t\trx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>\n \t\t\t   I40E_RXD_QW1_PTYPE_SHIFT;\n@@ -1748,13 +1747,13 @@ static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)\n \t\tI40E_RX_INCREMENT(rx_ring, i);\n \n \t\tif (unlikely(\n-\t\t    !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {\n+\t\t    !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {\n \t\t\trx_ring->rx_stats.non_eop_descs++;\n \t\t\tcontinue;\n \t\t}\n \n \t\t/* ERR_MASK will only have valid bits if EOP set */\n-\t\tif (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {\n+\t\tif (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {\n \t\t\tdev_kfree_skb_any(skb);\n \t\t\t/* TODO: shouldn't we increment a counter indicating the\n \t\t\t * drop?\n@@ -1779,7 +1778,7 @@ static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)\n \n \t\ti40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);\n \n-\t\tvlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)\n+\t\tvlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)\n \t\t\t ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)\n \t\t\t : 0;\n #ifdef I40E_FCOE\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.h b/drivers/net/ethernet/intel/i40e/i40e_txrx.h\nindex 0dc48dc..429833c 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_txrx.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.h\n@@ -66,17 +66,17 @@ enum i40e_dyn_idx_t {\n \n /* Supported RSS offloads */\n #define I40E_DEFAULT_RSS_HENA ( \\\n-\t((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \\\n-\t((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \\\n-\t((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \\\n-\t((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \\\n-\t((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) | \\\n-\t((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \\\n-\t((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \\\n-\t((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \\\n-\t((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \\\n-\t((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) | \\\n-\t((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD))\n+\tBIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \\\n+\tBIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \\\n+\tBIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \\\n+\tBIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \\\n+\tBIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \\\n+\tBIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \\\n+\tBIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \\\n+\tBIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \\\n+\tBIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \\\n+\tBIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \\\n+\tBIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD))\n \n /* Supported Rx Buffer Sizes */\n #define I40E_RXBUFFER_512   512    /* Used for packet split */\n@@ -129,17 +129,17 @@ enum i40e_dyn_idx_t {\n #define DESC_NEEDED (MAX_SKB_FRAGS + 4)\n #define I40E_MIN_DESC_PENDING\t4\n \n-#define I40E_TX_FLAGS_CSUM\t\t(u32)(1)\n-#define I40E_TX_FLAGS_HW_VLAN\t\t(u32)(1 << 1)\n-#define I40E_TX_FLAGS_SW_VLAN\t\t(u32)(1 << 2)\n-#define I40E_TX_FLAGS_TSO\t\t(u32)(1 << 3)\n-#define I40E_TX_FLAGS_IPV4\t\t(u32)(1 << 4)\n-#define I40E_TX_FLAGS_IPV6\t\t(u32)(1 << 5)\n-#define I40E_TX_FLAGS_FCCRC\t\t(u32)(1 << 6)\n-#define I40E_TX_FLAGS_FSO\t\t(u32)(1 << 7)\n-#define I40E_TX_FLAGS_TSYN\t\t(u32)(1 << 8)\n-#define I40E_TX_FLAGS_FD_SB\t\t(u32)(1 << 9)\n-#define I40E_TX_FLAGS_VXLAN_TUNNEL\t(u32)(1 << 10)\n+#define I40E_TX_FLAGS_CSUM\t\tBIT(0)\n+#define I40E_TX_FLAGS_HW_VLAN\t\tBIT(1)\n+#define I40E_TX_FLAGS_SW_VLAN\t\tBIT(2)\n+#define I40E_TX_FLAGS_TSO\t\tBIT(3)\n+#define I40E_TX_FLAGS_IPV4\t\tBIT(4)\n+#define I40E_TX_FLAGS_IPV6\t\tBIT(5)\n+#define I40E_TX_FLAGS_FCCRC\t\tBIT(6)\n+#define I40E_TX_FLAGS_FSO\t\tBIT(7)\n+#define I40E_TX_FLAGS_TSYN\t\tBIT(8)\n+#define I40E_TX_FLAGS_FD_SB\t\tBIT(9)\n+#define I40E_TX_FLAGS_VXLAN_TUNNEL\tBIT(10)\n #define I40E_TX_FLAGS_VLAN_MASK\t\t0xffff0000\n #define I40E_TX_FLAGS_VLAN_PRIO_MASK\t0xe0000000\n #define I40E_TX_FLAGS_VLAN_PRIO_SHIFT\t29\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_type.h b/drivers/net/ethernet/intel/i40e/i40e_type.h\nindex 0cabf04..a20128b 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_type.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_type.h\n@@ -611,7 +611,7 @@ enum i40e_rx_desc_status_bits {\n };\n \n #define I40E_RXD_QW1_STATUS_SHIFT\t0\n-#define I40E_RXD_QW1_STATUS_MASK\t(((1 << I40E_RX_DESC_STATUS_LAST) - 1) \\\n+#define I40E_RXD_QW1_STATUS_MASK\t((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \\\n \t\t\t\t\t << I40E_RXD_QW1_STATUS_SHIFT)\n \n #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT\n@@ -619,8 +619,8 @@ enum i40e_rx_desc_status_bits {\n \t\t\t\t\t     I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)\n \n #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT\n-#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK\t(0x1UL << \\\n-\t\t\t\t\t I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)\n+#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \\\n+\t\t\t\t    BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)\n \n enum i40e_rx_desc_fltstat_values {\n \tI40E_RX_DESC_FLTSTAT_NO_DATA\t= 0,\n@@ -754,8 +754,7 @@ enum i40e_rx_ptype_payload_layer {\n \t\t\t\t\t I40E_RXD_QW1_LENGTH_HBUF_SHIFT)\n \n #define I40E_RXD_QW1_LENGTH_SPH_SHIFT\t63\n-#define I40E_RXD_QW1_LENGTH_SPH_MASK\t(0x1ULL << \\\n-\t\t\t\t\t I40E_RXD_QW1_LENGTH_SPH_SHIFT)\n+#define I40E_RXD_QW1_LENGTH_SPH_MASK\tBIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)\n \n enum i40e_rx_desc_ext_status_bits {\n \t/* Note: These are predefined bit offsets */\n@@ -931,12 +930,12 @@ enum i40e_tx_ctx_desc_eipt_offload {\n #define I40E_TXD_CTX_QW0_NATT_SHIFT\t9\n #define I40E_TXD_CTX_QW0_NATT_MASK\t(0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)\n \n-#define I40E_TXD_CTX_UDP_TUNNELING\t(0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)\n+#define I40E_TXD_CTX_UDP_TUNNELING\tBIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)\n #define I40E_TXD_CTX_GRE_TUNNELING\t(0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)\n \n #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT\t11\n-#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK\t(0x1ULL << \\\n-\t\t\t\t\t I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)\n+#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \\\n+\t\t\t\t       BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)\n \n #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST\tI40E_TXD_CTX_QW0_EIP_NOINC_MASK\n \n@@ -1001,8 +1000,8 @@ enum i40e_filter_program_desc_fd_status {\n };\n \n #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT\t23\n-#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK\t(0x1FFUL << \\\n-\t\t\t\t\t I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)\n+#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK \\\n+\t\t\t\t       BIT_ULL(I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)\n \n #define I40E_TXD_FLTR_QW1_CMD_SHIFT\t4\n #define I40E_TXD_FLTR_QW1_CMD_MASK\t(0xFFFFULL << \\\n@@ -1020,8 +1019,7 @@ enum i40e_filter_program_desc_pcmd {\n #define I40E_TXD_FLTR_QW1_DEST_MASK\t(0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)\n \n #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT\t(0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)\n-#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK\t(0x1ULL << \\\n-\t\t\t\t\t I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)\n+#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK\tBIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)\n \n #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT\t(0x9ULL + \\\n \t\t\t\t\t\t I40E_TXD_FLTR_QW1_CMD_SHIFT)\ndiff --git a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c\nindex 4f13619..8c14ef6 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c\n@@ -277,16 +277,14 @@ static void i40e_config_irq_link_list(struct i40e_vf *vf, u16 vsi_id,\n \t}\n \ttempmap = vecmap->rxq_map;\n \tfor_each_set_bit(vsi_queue_id, &tempmap, I40E_MAX_VSI_QP) {\n-\t\tlinklistmap |= (1 <<\n-\t\t\t\t(I40E_VIRTCHNL_SUPPORTED_QTYPES *\n-\t\t\t\t vsi_queue_id));\n+\t\tlinklistmap |= (BIT(I40E_VIRTCHNL_SUPPORTED_QTYPES *\n+\t\t\t\t    vsi_queue_id));\n \t}\n \n \ttempmap = vecmap->txq_map;\n \tfor_each_set_bit(vsi_queue_id, &tempmap, I40E_MAX_VSI_QP) {\n-\t\tlinklistmap |= (1 <<\n-\t\t\t\t(I40E_VIRTCHNL_SUPPORTED_QTYPES * vsi_queue_id\n-\t\t\t\t + 1));\n+\t\tlinklistmap |= (BIT(I40E_VIRTCHNL_SUPPORTED_QTYPES *\n+\t\t\t\t     vsi_queue_id + 1));\n \t}\n \n \tnext_q = find_first_bit(&linklistmap,\n@@ -332,7 +330,7 @@ static void i40e_config_irq_link_list(struct i40e_vf *vf, u16 vsi_id,\n \t\treg = (vector_id) |\n \t\t    (qtype << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |\n \t\t    (pf_queue_id << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |\n-\t\t    (1 << I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) |\n+\t\t    BIT(I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) |\n \t\t    (itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT);\n \t\twr32(hw, reg_idx, reg);\n \t}\n@@ -897,7 +895,7 @@ void i40e_free_vfs(struct i40e_pf *pf)\n \t\tfor (vf_id = 0; vf_id < tmp; vf_id++) {\n \t\t\treg_idx = (hw->func_caps.vf_base_id + vf_id) / 32;\n \t\t\tbit_idx = (hw->func_caps.vf_base_id + vf_id) % 32;\n-\t\t\twr32(hw, I40E_GLGEN_VFLRSTAT(reg_idx), (1 << bit_idx));\n+\t\t\twr32(hw, I40E_GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx));\n \t\t}\n \t}\n \tclear_bit(__I40E_VF_DISABLE, &pf->state);\n@@ -1975,9 +1973,9 @@ int i40e_vc_process_vflr_event(struct i40e_pf *pf)\n \t\t/* read GLGEN_VFLRSTAT register to find out the flr VFs */\n \t\tvf = &pf->vf[vf_id];\n \t\treg = rd32(hw, I40E_GLGEN_VFLRSTAT(reg_idx));\n-\t\tif (reg & (1 << bit_idx)) {\n+\t\tif (reg & BIT(bit_idx)) {\n \t\t\t/* clear the bit in GLGEN_VFLRSTAT */\n-\t\t\twr32(hw, I40E_GLGEN_VFLRSTAT(reg_idx), (1 << bit_idx));\n+\t\t\twr32(hw, I40E_GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx));\n \n \t\t\tif (!test_bit(__I40E_DOWN, &pf->state))\n \t\t\t\ti40e_reset_vf(vf, true);\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_hmc.h b/drivers/net/ethernet/intel/i40evf/i40e_hmc.h\nindex 1d27ae4..0f3ce1f 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_hmc.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_hmc.h\n@@ -127,8 +127,8 @@ struct i40e_hmc_info {\n \t\t I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) |\t\t\\\n \t\t((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) <<\t\t\\\n \t\tI40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT) |\t\t\t\\\n-\t\t(1 << I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT);\t\t\\\n-\tval3 = (sd_index) | (1u << I40E_PFHMC_SDCMD_PMSDWR_SHIFT);\t\\\n+\t\tBIT(I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT);\t\t\\\n+\tval3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT);\t\\\n \twr32((hw), I40E_PFHMC_SDDATAHIGH, val1);\t\t\t\\\n \twr32((hw), I40E_PFHMC_SDDATALOW, val2);\t\t\t\t\\\n \twr32((hw), I40E_PFHMC_SDCMD, val3);\t\t\t\t\\\n@@ -147,7 +147,7 @@ struct i40e_hmc_info {\n \t\tI40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) |\t\t\\\n \t\t((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) <<\t\t\\\n \t\tI40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT);\t\t\t\\\n-\tval3 = (sd_index) | (1u << I40E_PFHMC_SDCMD_PMSDWR_SHIFT);\t\\\n+\tval3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT);\t\\\n \twr32((hw), I40E_PFHMC_SDDATAHIGH, 0);\t\t\t\t\\\n \twr32((hw), I40E_PFHMC_SDDATALOW, val2);\t\t\t\t\\\n \twr32((hw), I40E_PFHMC_SDCMD, val3);\t\t\t\t\\\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\nindex 0e052ee..4649d45 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\n@@ -846,7 +846,7 @@ static inline void i40e_rx_checksum(struct i40e_vsi *vsi,\n \t\treturn;\n \n \t/* did the hardware decode the packet and checksum? */\n-\tif (!(rx_status & (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT)))\n+\tif (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))\n \t\treturn;\n \n \t/* both known and outer_ip must be set for the below code to work */\n@@ -861,25 +861,25 @@ static inline void i40e_rx_checksum(struct i40e_vsi *vsi,\n \t\tipv6 = true;\n \n \tif (ipv4 &&\n-\t    (rx_error & ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT) |\n-\t\t\t (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT))))\n+\t    (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |\n+\t\t\t BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))\n \t\tgoto checksum_fail;\n \n \t/* likely incorrect csum if alternate IP extension headers found */\n \tif (ipv6 &&\n-\t    rx_status & (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))\n+\t    rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))\n \t\t/* don't increment checksum err here, non-fatal err */\n \t\treturn;\n \n \t/* there was some L4 error, count error and punt packet to the stack */\n-\tif (rx_error & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT))\n+\tif (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))\n \t\tgoto checksum_fail;\n \n \t/* handle packets that were not able to be checksummed due\n \t * to arrival speed, in this case the stack can compute\n \t * the csum.\n \t */\n-\tif (rx_error & (1 << I40E_RX_DESC_ERROR_PPRS_SHIFT))\n+\tif (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))\n \t\treturn;\n \n \t/* If VXLAN traffic has an outer UDPv4 checksum we need to check\n@@ -1000,7 +1000,7 @@ static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)\n \t\trx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>\n \t\t\tI40E_RXD_QW1_STATUS_SHIFT;\n \n-\t\tif (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))\n+\t\tif (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))\n \t\t\tbreak;\n \n \t\t/* This memory barrier is needed to keep us from reading\n@@ -1036,8 +1036,8 @@ static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)\n \n \t\trx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>\n \t\t\t   I40E_RXD_QW1_ERROR_SHIFT;\n-\t\trx_hbo = rx_error & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT);\n-\t\trx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);\n+\t\trx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);\n+\t\trx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);\n \n \t\trx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>\n \t\t\t   I40E_RXD_QW1_PTYPE_SHIFT;\n@@ -1089,7 +1089,7 @@ static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)\n \t\tI40E_RX_INCREMENT(rx_ring, i);\n \n \t\tif (unlikely(\n-\t\t    !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {\n+\t\t    !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {\n \t\t\tstruct i40e_rx_buffer *next_buffer;\n \n \t\t\tnext_buffer = &rx_ring->rx_bi[i];\n@@ -1099,7 +1099,7 @@ static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)\n \t\t}\n \n \t\t/* ERR_MASK will only have valid bits if EOP set */\n-\t\tif (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {\n+\t\tif (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {\n \t\t\tdev_kfree_skb_any(skb);\n \t\t\tcontinue;\n \t\t}\n@@ -1114,7 +1114,7 @@ static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)\n \n \t\ti40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);\n \n-\t\tvlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)\n+\t\tvlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)\n \t\t\t ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)\n \t\t\t : 0;\n #ifdef I40E_FCOE\n@@ -1175,7 +1175,7 @@ static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)\n \t\trx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>\n \t\t\tI40E_RXD_QW1_STATUS_SHIFT;\n \n-\t\tif (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))\n+\t\tif (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))\n \t\t\tbreak;\n \n \t\t/* This memory barrier is needed to keep us from reading\n@@ -1193,7 +1193,7 @@ static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)\n \n \t\trx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>\n \t\t\t   I40E_RXD_QW1_ERROR_SHIFT;\n-\t\trx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);\n+\t\trx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);\n \n \t\trx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>\n \t\t\t   I40E_RXD_QW1_PTYPE_SHIFT;\n@@ -1211,13 +1211,13 @@ static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)\n \t\tI40E_RX_INCREMENT(rx_ring, i);\n \n \t\tif (unlikely(\n-\t\t    !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {\n+\t\t    !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {\n \t\t\trx_ring->rx_stats.non_eop_descs++;\n \t\t\tcontinue;\n \t\t}\n \n \t\t/* ERR_MASK will only have valid bits if EOP set */\n-\t\tif (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {\n+\t\tif (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {\n \t\t\tdev_kfree_skb_any(skb);\n \t\t\t/* TODO: shouldn't we increment a counter indicating the\n \t\t\t * drop?\n@@ -1235,7 +1235,7 @@ static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)\n \n \t\ti40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);\n \n-\t\tvlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)\n+\t\tvlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)\n \t\t\t ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)\n \t\t\t : 0;\n \t\ti40e_receive_skb(rx_ring, skb, vlan_tag);\n@@ -1310,8 +1310,7 @@ static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,\n \t\tif (!test_bit(__I40E_DOWN, &vsi->state))\n \t\t\twr32(hw, I40E_VFINT_DYN_CTLN(vector - 1), val);\n \t} else {\n-\t\ti40evf_irq_enable_queues(vsi->back,\n-\t\t\t\t\t 1 << q_vector->v_idx);\n+\t\ti40evf_irq_enable_queues(vsi->back, BIT(q_vector->v_idx));\n \t}\n }\n \ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.h b/drivers/net/ethernet/intel/i40evf/i40e_txrx.h\nindex e7a34f8..6b47c81 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_txrx.h\n@@ -66,17 +66,17 @@ enum i40e_dyn_idx_t {\n \n /* Supported RSS offloads */\n #define I40E_DEFAULT_RSS_HENA ( \\\n-\t((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \\\n-\t((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \\\n-\t((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \\\n-\t((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \\\n-\t((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) | \\\n-\t((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \\\n-\t((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \\\n-\t((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \\\n-\t((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \\\n-\t((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) | \\\n-\t((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD))\n+\tBIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \\\n+\tBIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \\\n+\tBIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \\\n+\tBIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \\\n+\tBIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \\\n+\tBIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \\\n+\tBIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \\\n+\tBIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \\\n+\tBIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \\\n+\tBIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \\\n+\tBIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD))\n \n /* Supported Rx Buffer Sizes */\n #define I40E_RXBUFFER_512   512    /* Used for packet split */\n@@ -129,16 +129,16 @@ enum i40e_dyn_idx_t {\n #define DESC_NEEDED (MAX_SKB_FRAGS + 4)\n #define I40E_MIN_DESC_PENDING\t4\n \n-#define I40E_TX_FLAGS_CSUM\t\t(u32)(1)\n-#define I40E_TX_FLAGS_HW_VLAN\t\t(u32)(1 << 1)\n-#define I40E_TX_FLAGS_SW_VLAN\t\t(u32)(1 << 2)\n-#define I40E_TX_FLAGS_TSO\t\t(u32)(1 << 3)\n-#define I40E_TX_FLAGS_IPV4\t\t(u32)(1 << 4)\n-#define I40E_TX_FLAGS_IPV6\t\t(u32)(1 << 5)\n-#define I40E_TX_FLAGS_FCCRC\t\t(u32)(1 << 6)\n-#define I40E_TX_FLAGS_FSO\t\t(u32)(1 << 7)\n-#define I40E_TX_FLAGS_FD_SB\t\t(u32)(1 << 9)\n-#define I40E_TX_FLAGS_VXLAN_TUNNEL\t(u32)(1 << 10)\n+#define I40E_TX_FLAGS_CSUM\t\tBIT(0)\n+#define I40E_TX_FLAGS_HW_VLAN\t\tBIT(1)\n+#define I40E_TX_FLAGS_SW_VLAN\t\tBIT(2)\n+#define I40E_TX_FLAGS_TSO\t\tBIT(3)\n+#define I40E_TX_FLAGS_IPV4\t\tBIT(4)\n+#define I40E_TX_FLAGS_IPV6\t\tBIT(5)\n+#define I40E_TX_FLAGS_FCCRC\t\tBIT(6)\n+#define I40E_TX_FLAGS_FSO\t\tBIT(7)\n+#define I40E_TX_FLAGS_FD_SB\t\tBIT(9)\n+#define I40E_TX_FLAGS_VXLAN_TUNNEL\tBIT(10)\n #define I40E_TX_FLAGS_VLAN_MASK\t\t0xffff0000\n #define I40E_TX_FLAGS_VLAN_PRIO_MASK\t0xe0000000\n #define I40E_TX_FLAGS_VLAN_PRIO_SHIFT\t29\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_type.h b/drivers/net/ethernet/intel/i40evf/i40e_type.h\nindex cbf94bd..4ba9a01 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_type.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_type.h\n@@ -605,7 +605,7 @@ enum i40e_rx_desc_status_bits {\n };\n \n #define I40E_RXD_QW1_STATUS_SHIFT\t0\n-#define I40E_RXD_QW1_STATUS_MASK\t(((1 << I40E_RX_DESC_STATUS_LAST) - 1) \\\n+#define I40E_RXD_QW1_STATUS_MASK\t((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \\\n \t\t\t\t\t << I40E_RXD_QW1_STATUS_SHIFT)\n \n #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT\n@@ -613,8 +613,8 @@ enum i40e_rx_desc_status_bits {\n \t\t\t\t\t     I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)\n \n #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT\n-#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK\t(0x1UL << \\\n-\t\t\t\t\t I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)\n+#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \\\n+\t\t\t\t    BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)\n \n enum i40e_rx_desc_fltstat_values {\n \tI40E_RX_DESC_FLTSTAT_NO_DATA\t= 0,\n@@ -748,8 +748,7 @@ enum i40e_rx_ptype_payload_layer {\n \t\t\t\t\t I40E_RXD_QW1_LENGTH_HBUF_SHIFT)\n \n #define I40E_RXD_QW1_LENGTH_SPH_SHIFT\t63\n-#define I40E_RXD_QW1_LENGTH_SPH_MASK\t(0x1ULL << \\\n-\t\t\t\t\t I40E_RXD_QW1_LENGTH_SPH_SHIFT)\n+#define I40E_RXD_QW1_LENGTH_SPH_MASK\tBIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)\n \n enum i40e_rx_desc_ext_status_bits {\n \t/* Note: These are predefined bit offsets */\n@@ -925,12 +924,12 @@ enum i40e_tx_ctx_desc_eipt_offload {\n #define I40E_TXD_CTX_QW0_NATT_SHIFT\t9\n #define I40E_TXD_CTX_QW0_NATT_MASK\t(0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)\n \n-#define I40E_TXD_CTX_UDP_TUNNELING\t(0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)\n+#define I40E_TXD_CTX_UDP_TUNNELING\tBIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)\n #define I40E_TXD_CTX_GRE_TUNNELING\t(0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)\n \n #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT\t11\n-#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK\t(0x1ULL << \\\n-\t\t\t\t\t I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)\n+#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \\\n+\t\t\t\t       BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)\n \n #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST\tI40E_TXD_CTX_QW0_EIP_NOINC_MASK\n \n@@ -995,8 +994,8 @@ enum i40e_filter_program_desc_fd_status {\n };\n \n #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT\t23\n-#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK\t(0x1FFUL << \\\n-\t\t\t\t\t I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)\n+#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK \\\n+\t\t\t\t       BIT_ULL(I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)\n \n #define I40E_TXD_FLTR_QW1_CMD_SHIFT\t4\n #define I40E_TXD_FLTR_QW1_CMD_MASK\t(0xFFFFULL << \\\n@@ -1014,8 +1013,7 @@ enum i40e_filter_program_desc_pcmd {\n #define I40E_TXD_FLTR_QW1_DEST_MASK\t(0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)\n \n #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT\t(0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)\n-#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK\t(0x1ULL << \\\n-\t\t\t\t\t I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)\n+#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK\tBIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)\n \n #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT\t(0x9ULL + \\\n \t\t\t\t\t\t I40E_TXD_FLTR_QW1_CMD_SHIFT)\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40evf.h b/drivers/net/ethernet/intel/i40evf/i40evf.h\nindex c741181..b2f899c 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40evf.h\n+++ b/drivers/net/ethernet/intel/i40evf/i40evf.h\n@@ -207,17 +207,17 @@ struct i40evf_adapter {\n \tstruct msix_entry *msix_entries;\n \n \tu32 flags;\n-#define I40EVF_FLAG_RX_CSUM_ENABLED              (u32)(1)\n-#define I40EVF_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 1)\n-#define I40EVF_FLAG_RX_PS_CAPABLE                (u32)(1 << 2)\n-#define I40EVF_FLAG_RX_PS_ENABLED                (u32)(1 << 3)\n-#define I40EVF_FLAG_IN_NETPOLL                   (u32)(1 << 4)\n-#define I40EVF_FLAG_IMIR_ENABLED                 (u32)(1 << 5)\n-#define I40EVF_FLAG_MQ_CAPABLE                   (u32)(1 << 6)\n-#define I40EVF_FLAG_NEED_LINK_UPDATE             (u32)(1 << 7)\n-#define I40EVF_FLAG_PF_COMMS_FAILED              (u32)(1 << 8)\n-#define I40EVF_FLAG_RESET_PENDING                (u32)(1 << 9)\n-#define I40EVF_FLAG_RESET_NEEDED                 (u32)(1 << 10)\n+#define I40EVF_FLAG_RX_CSUM_ENABLED              BIT(0)\n+#define I40EVF_FLAG_RX_1BUF_CAPABLE              BIT(1)\n+#define I40EVF_FLAG_RX_PS_CAPABLE                BIT(2)\n+#define I40EVF_FLAG_RX_PS_ENABLED                BIT(3)\n+#define I40EVF_FLAG_IN_NETPOLL                   BIT(4)\n+#define I40EVF_FLAG_IMIR_ENABLED                 BIT(5)\n+#define I40EVF_FLAG_MQ_CAPABLE                   BIT(6)\n+#define I40EVF_FLAG_NEED_LINK_UPDATE             BIT(7)\n+#define I40EVF_FLAG_PF_COMMS_FAILED              BIT(8)\n+#define I40EVF_FLAG_RESET_PENDING                BIT(9)\n+#define I40EVF_FLAG_RESET_NEEDED                 BIT(10)\n /* duplcates for common code */\n #define I40E_FLAG_FDIR_ATR_ENABLED\t\t 0\n #define I40E_FLAG_DCB_ENABLED\t\t\t 0\n@@ -225,16 +225,16 @@ struct i40evf_adapter {\n #define I40E_FLAG_RX_CSUM_ENABLED                I40EVF_FLAG_RX_CSUM_ENABLED\n \t/* flags for admin queue service task */\n \tu32 aq_required;\n-#define I40EVF_FLAG_AQ_ENABLE_QUEUES\t\t(u32)(1)\n-#define I40EVF_FLAG_AQ_DISABLE_QUEUES\t\t(u32)(1 << 1)\n-#define I40EVF_FLAG_AQ_ADD_MAC_FILTER\t\t(u32)(1 << 2)\n-#define I40EVF_FLAG_AQ_ADD_VLAN_FILTER\t\t(u32)(1 << 3)\n-#define I40EVF_FLAG_AQ_DEL_MAC_FILTER\t\t(u32)(1 << 4)\n-#define I40EVF_FLAG_AQ_DEL_VLAN_FILTER\t\t(u32)(1 << 5)\n-#define I40EVF_FLAG_AQ_CONFIGURE_QUEUES\t\t(u32)(1 << 6)\n-#define I40EVF_FLAG_AQ_MAP_VECTORS\t\t(u32)(1 << 7)\n-#define I40EVF_FLAG_AQ_HANDLE_RESET\t\t(u32)(1 << 8)\n-#define I40EVF_FLAG_AQ_GET_CONFIG\t\t(u32)(1 << 10)\n+#define I40EVF_FLAG_AQ_ENABLE_QUEUES\t\tBIT(0)\n+#define I40EVF_FLAG_AQ_DISABLE_QUEUES\t\tBIT(1)\n+#define I40EVF_FLAG_AQ_ADD_MAC_FILTER\t\tBIT(2)\n+#define I40EVF_FLAG_AQ_ADD_VLAN_FILTER\t\tBIT(3)\n+#define I40EVF_FLAG_AQ_DEL_MAC_FILTER\t\tBIT(4)\n+#define I40EVF_FLAG_AQ_DEL_VLAN_FILTER\t\tBIT(5)\n+#define I40EVF_FLAG_AQ_CONFIGURE_QUEUES\t\tBIT(6)\n+#define I40EVF_FLAG_AQ_MAP_VECTORS\t\tBIT(7)\n+#define I40EVF_FLAG_AQ_HANDLE_RESET\t\tBIT(8)\n+#define I40EVF_FLAG_AQ_GET_CONFIG\t\tBIT(10)\n \n \t/* OS defined structs */\n \tstruct net_device *netdev;\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c b/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c\nindex f4e7766..34cc90f 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c\n@@ -379,11 +379,11 @@ static int i40evf_get_rss_hash_opts(struct i40evf_adapter *adapter,\n \n \tswitch (cmd->flow_type) {\n \tcase TCP_V4_FLOW:\n-\t\tif (hena & ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))\n+\t\tif (hena & BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP))\n \t\t\tcmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;\n \t\tbreak;\n \tcase UDP_V4_FLOW:\n-\t\tif (hena & ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))\n+\t\tif (hena & BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP))\n \t\t\tcmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;\n \t\tbreak;\n \n@@ -395,11 +395,11 @@ static int i40evf_get_rss_hash_opts(struct i40evf_adapter *adapter,\n \t\tbreak;\n \n \tcase TCP_V6_FLOW:\n-\t\tif (hena & ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))\n+\t\tif (hena & BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP))\n \t\t\tcmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;\n \t\tbreak;\n \tcase UDP_V6_FLOW:\n-\t\tif (hena & ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))\n+\t\tif (hena & BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP))\n \t\t\tcmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;\n \t\tbreak;\n \n@@ -477,10 +477,10 @@ static int i40evf_set_rss_hash_opt(struct i40evf_adapter *adapter,\n \tcase TCP_V4_FLOW:\n \t\tswitch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {\n \t\tcase 0:\n-\t\t\thena &= ~((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);\n+\t\t\thena &= ~BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP);\n \t\t\tbreak;\n \t\tcase (RXH_L4_B_0_1 | RXH_L4_B_2_3):\n-\t\t\thena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);\n+\t\t\thena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP);\n \t\t\tbreak;\n \t\tdefault:\n \t\t\treturn -EINVAL;\n@@ -489,10 +489,10 @@ static int i40evf_set_rss_hash_opt(struct i40evf_adapter *adapter,\n \tcase TCP_V6_FLOW:\n \t\tswitch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {\n \t\tcase 0:\n-\t\t\thena &= ~((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);\n+\t\t\thena &= ~BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP);\n \t\t\tbreak;\n \t\tcase (RXH_L4_B_0_1 | RXH_L4_B_2_3):\n-\t\t\thena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);\n+\t\t\thena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP);\n \t\t\tbreak;\n \t\tdefault:\n \t\t\treturn -EINVAL;\n@@ -501,12 +501,12 @@ static int i40evf_set_rss_hash_opt(struct i40evf_adapter *adapter,\n \tcase UDP_V4_FLOW:\n \t\tswitch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {\n \t\tcase 0:\n-\t\t\thena &= ~(((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |\n-\t\t\t\t  ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4));\n+\t\t\thena &= ~(BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |\n+\t\t\t\t  BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4));\n \t\t\tbreak;\n \t\tcase (RXH_L4_B_0_1 | RXH_L4_B_2_3):\n-\t\t\thena |= (((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |\n-\t\t\t\t ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4));\n+\t\t\thena |= (BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |\n+\t\t\t\t BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4));\n \t\t\tbreak;\n \t\tdefault:\n \t\t\treturn -EINVAL;\n@@ -515,12 +515,12 @@ static int i40evf_set_rss_hash_opt(struct i40evf_adapter *adapter,\n \tcase UDP_V6_FLOW:\n \t\tswitch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {\n \t\tcase 0:\n-\t\t\thena &= ~(((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |\n-\t\t\t\t  ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6));\n+\t\t\thena &= ~(BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |\n+\t\t\t\t  BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6));\n \t\t\tbreak;\n \t\tcase (RXH_L4_B_0_1 | RXH_L4_B_2_3):\n-\t\t\thena |= (((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |\n-\t\t\t\t ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6));\n+\t\t\thena |= (BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |\n+\t\t\t\t BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6));\n \t\t\tbreak;\n \t\tdefault:\n \t\t\treturn -EINVAL;\n@@ -533,7 +533,7 @@ static int i40evf_set_rss_hash_opt(struct i40evf_adapter *adapter,\n \t\tif ((nfc->data & RXH_L4_B_0_1) ||\n \t\t    (nfc->data & RXH_L4_B_2_3))\n \t\t\treturn -EINVAL;\n-\t\thena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);\n+\t\thena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);\n \t\tbreak;\n \tcase AH_ESP_V6_FLOW:\n \tcase AH_V6_FLOW:\n@@ -542,15 +542,15 @@ static int i40evf_set_rss_hash_opt(struct i40evf_adapter *adapter,\n \t\tif ((nfc->data & RXH_L4_B_0_1) ||\n \t\t    (nfc->data & RXH_L4_B_2_3))\n \t\t\treturn -EINVAL;\n-\t\thena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);\n+\t\thena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);\n \t\tbreak;\n \tcase IPV4_FLOW:\n-\t\thena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) |\n-\t\t\t((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4);\n+\t\thena |= (BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) |\n+\t\t\t BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4));\n \t\tbreak;\n \tcase IPV6_FLOW:\n-\t\thena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) |\n-\t\t\t((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6);\n+\t\thena |= (BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) |\n+\t\t\t BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6));\n \t\tbreak;\n \tdefault:\n \t\treturn -EINVAL;\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40evf_main.c b/drivers/net/ethernet/intel/i40evf/i40evf_main.c\nindex 0d0ad3d..c64f6c4 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40evf_main.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40evf_main.c\n@@ -239,7 +239,7 @@ void i40evf_irq_enable_queues(struct i40evf_adapter *adapter, u32 mask)\n \tint i;\n \n \tfor (i = 1; i < adapter->num_msix_vectors; i++) {\n-\t\tif (mask & (1 << (i - 1))) {\n+\t\tif (mask & BIT(i - 1)) {\n \t\t\twr32(hw, I40E_VFINT_DYN_CTLN1(i - 1),\n \t\t\t     I40E_VFINT_DYN_CTLN1_INTENA_MASK |\n \t\t\t     I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK |\n@@ -267,7 +267,7 @@ static void i40evf_fire_sw_int(struct i40evf_adapter *adapter, u32 mask)\n \t\twr32(hw, I40E_VFINT_DYN_CTL01, dyn_ctl);\n \t}\n \tfor (i = 1; i < adapter->num_msix_vectors; i++) {\n-\t\tif (mask & (1 << i)) {\n+\t\tif (mask & BIT(i)) {\n \t\t\tdyn_ctl = rd32(hw, I40E_VFINT_DYN_CTLN1(i - 1));\n \t\t\tdyn_ctl |= I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK |\n \t\t\t\t   I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK |\n@@ -376,7 +376,7 @@ i40evf_map_vector_to_txq(struct i40evf_adapter *adapter, int v_idx, int t_idx)\n \tq_vector->tx.count++;\n \tq_vector->tx.latency_range = I40E_LOW_LATENCY;\n \tq_vector->num_ringpairs++;\n-\tq_vector->ring_mask |= (1 << t_idx);\n+\tq_vector->ring_mask |= BIT(t_idx);\n }\n \n /**\n@@ -2337,7 +2337,7 @@ static int i40evf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)\n \thw = &adapter->hw;\n \thw->back = adapter;\n \n-\tadapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;\n+\tadapter->msg_enable = BIT(DEFAULT_DEBUG_LEVEL_SHIFT) - 1;\n \tadapter->state = __I40EVF_STARTUP;\n \n \t/* Call save state here because it relies on the adapter struct. */\ndiff --git a/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c b/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c\nindex becd300..d4eb1a5 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c\n@@ -294,7 +294,7 @@ void i40evf_enable_queues(struct i40evf_adapter *adapter)\n \t}\n \tadapter->current_op = I40E_VIRTCHNL_OP_ENABLE_QUEUES;\n \tvqs.vsi_id = adapter->vsi_res->vsi_id;\n-\tvqs.tx_queues = (1 << adapter->num_active_queues) - 1;\n+\tvqs.tx_queues = BIT(adapter->num_active_queues) - 1;\n \tvqs.rx_queues = vqs.tx_queues;\n \tadapter->aq_required &= ~I40EVF_FLAG_AQ_ENABLE_QUEUES;\n \ti40evf_send_pf_msg(adapter, I40E_VIRTCHNL_OP_ENABLE_QUEUES,\n@@ -319,7 +319,7 @@ void i40evf_disable_queues(struct i40evf_adapter *adapter)\n \t}\n \tadapter->current_op = I40E_VIRTCHNL_OP_DISABLE_QUEUES;\n \tvqs.vsi_id = adapter->vsi_res->vsi_id;\n-\tvqs.tx_queues = (1 << adapter->num_active_queues) - 1;\n+\tvqs.tx_queues = BIT(adapter->num_active_queues) - 1;\n \tvqs.rx_queues = vqs.tx_queues;\n \tadapter->aq_required &= ~I40EVF_FLAG_AQ_DISABLE_QUEUES;\n \ti40evf_send_pf_msg(adapter, I40E_VIRTCHNL_OP_DISABLE_QUEUES,\n",
    "prefixes": [
        "net-next",
        "8/8"
    ]
}