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GET /api/patches/477527/?format=api
{ "id": 477527, "url": "http://patchwork.ozlabs.org/api/patches/477527/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/patch/1432863742-18427-6-git-send-email-mathieu@codeaurora.org/", "project": { "id": 7, "url": "http://patchwork.ozlabs.org/api/projects/7/?format=api", "name": "Linux network development", "link_name": "netdev", "list_id": "netdev.vger.kernel.org", "list_email": "netdev@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1432863742-18427-6-git-send-email-mathieu@codeaurora.org>", "list_archive_url": null, "date": "2015-05-29T01:42:20", "name": "[5/7] net: dsa: ar8xxx: enable QCA header support on AR8xxx", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "e520686e40aed0a5d911a58388b16b3c4f226f08", "submitter": { "id": 65737, "url": "http://patchwork.ozlabs.org/api/people/65737/?format=api", "name": "Mathieu Olivari", "email": "mathieu@codeaurora.org" }, "delegate": { "id": 34, "url": "http://patchwork.ozlabs.org/api/users/34/?format=api", "username": "davem", "first_name": "David", "last_name": "Miller", "email": "davem@davemloft.net" }, "mbox": "http://patchwork.ozlabs.org/project/netdev/patch/1432863742-18427-6-git-send-email-mathieu@codeaurora.org/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/477527/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/477527/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<netdev-owner@vger.kernel.org>", "X-Original-To": "patchwork-incoming@ozlabs.org", "Delivered-To": "patchwork-incoming@ozlabs.org", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 470F014016A\n\tfor <patchwork-incoming@ozlabs.org>;\n\tFri, 29 May 2015 11:44:42 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755310AbbE2BnF (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tThu, 28 May 2015 21:43:05 -0400", "from smtp.codeaurora.org ([198.145.29.96]:37465 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1754653AbbE2Bme (ORCPT\n\t<rfc822;netdev@vger.kernel.org>); Thu, 28 May 2015 21:42:34 -0400", "from smtp.codeaurora.org (localhost [127.0.0.1])\n\tby smtp.codeaurora.org (Postfix) with ESMTP id CA7EA140DB9;\n\tFri, 29 May 2015 01:42:33 +0000 (UTC)", "by smtp.codeaurora.org (Postfix, from userid 486)\n\tid B5DAD140DBF; Fri, 29 May 2015 01:42:33 +0000 (UTC)", "from mathieu-linux.qualcomm.com (qf-scl1nat.qualcomm.com\n\t[207.114.132.30])\n\t(using TLSv1.2 with cipher AES128-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\t(Authenticated sender: mathieu@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id C392A140DB9;\n\tFri, 29 May 2015 01:42:32 +0000 (UTC)" ], "X-Spam-Checker-Version": "SpamAssassin 3.3.1 (2010-03-16) on\n\tpdx-caf-smtp.dmz.codeaurora.org", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.9 required=2.0 tests=ALL_TRUSTED,BAYES_00\n\tautolearn=ham version=3.3.1", "From": "Mathieu Olivari <mathieu@codeaurora.org>", "To": "robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,\n\tijc+devicetree@hellion.org.uk, galak@codeaurora.org,\n\tdavem@davemloft.net, mathieu@codeaurora.org, andrew@lunn.ch,\n\tf.fainelli@gmail.com, linux@roeck-us.net, gang.chen.5i5j@gmail.com,\n\tjiri@resnulli.us, leitec@staticky.com, fabf@skynet.be,\n\talexander.h.duyck@intel.com, pavel.nakonechny@skitlab.ru,\n\tjoe@perches.com, sfeldma@gmail.com, nbd@openwrt.org, juhosg@openwrt.org", "Cc": "devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tnetdev@vger.kernel.org", "Subject": "[PATCH 5/7] net: dsa: ar8xxx: enable QCA header support on AR8xxx", "Date": "Thu, 28 May 2015 18:42:20 -0700", "Message-Id": "<1432863742-18427-6-git-send-email-mathieu@codeaurora.org>", "X-Mailer": "git-send-email 2.1.4", "In-Reply-To": "<1432863742-18427-1-git-send-email-mathieu@codeaurora.org>", "References": "<1432863742-18427-1-git-send-email-mathieu@codeaurora.org>", "X-Virus-Scanned": "ClamAV using ClamSMTP", "Sender": "netdev-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<netdev.vger.kernel.org>", "X-Mailing-List": "netdev@vger.kernel.org" }, "content": "This change enable support for the QCA headers in QCA83337 driver.\nA 2 bytes header will be added by the switch on every incoming packet\nto identify the ingress port, and the DSA tagging code will add a\nsimilar 2 bytes header to control which port is used to send a\nparticular packet.\n\nSigned-off-by: Mathieu Olivari <mathieu@codeaurora.org>\n---\n drivers/net/dsa/Kconfig | 1 +\n drivers/net/dsa/ar8xxx.c | 28 ++++++++++++++++++++++++++--\n drivers/net/dsa/ar8xxx.h | 22 ++++++++++++++++++++++\n 3 files changed, 49 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig\nindex 17fb296..fa8b484 100644\n--- a/drivers/net/dsa/Kconfig\n+++ b/drivers/net/dsa/Kconfig\n@@ -68,6 +68,7 @@ config NET_DSA_BCM_SF2\n config NET_DSA_AR8XXX\n \ttristate \"Qualcomm Atheros AR8XXX Ethernet switch family support\"\n \tdepends on NET_DSA\n+\tselect NET_DSA_TAG_QCA\n \tselect REGMAP\n \t---help---\n \t This enables support for the Qualcomm Atheros AR8XXX Ethernet\ndiff --git a/drivers/net/dsa/ar8xxx.c b/drivers/net/dsa/ar8xxx.c\nindex 327abd4..4044614 100644\n--- a/drivers/net/dsa/ar8xxx.c\n+++ b/drivers/net/dsa/ar8xxx.c\n@@ -292,15 +292,31 @@ static int ar8xxx_setup(struct dsa_switch *ds)\n \tif (ret < 0)\n \t\treturn ret;\n \n+\t/* Enable CPU Port */\n+\tar8xxx_reg_set(ds, AR8327_REG_GLOBAL_FW_CTRL0,\n+\t\t AR8327_GLOBAL_FW_CTRL0_CPU_PORT_EN);\n+\n \t/* Enable MIB counters */\n \tar8xxx_reg_set(ds, AR8327_REG_MIB, AR8327_MIB_CPU_KEEP);\n \tar8xxx_write(ds, AR8327_REG_MODULE_EN, AR8327_MODULE_EN_MIB);\n \n+\t/* Enable QCA header mode on Port 0 */\n+\tar8xxx_write(ds, AR8327_REG_PORT_HDR_CTRL(0),\n+\t\t AR8327_PORT_HDR_CTRL_ALL << AR8327_PORT_HDR_CTRL_TX_S |\n+\t\t AR8327_PORT_HDR_CTRL_ALL << AR8327_PORT_HDR_CTRL_RX_S);\n+\n \t/* Disable forwarding by default on all ports */\n \tfor (i = 0; i < AR8327_NUM_PORTS; i++)\n \t\tar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(i),\n \t\t\t AR8327_PORT_LOOKUP_MEMBER, 0);\n \n+\t/* Forward all unknown frames to CPU port for Linux processing */\n+\tar8xxx_write(ds, AR8327_REG_GLOBAL_FW_CTRL1,\n+\t\t BIT(0) << AR8327_GLOBAL_FW_CTRL1_IGMP_DP_S |\n+\t\t BIT(0) << AR8327_GLOBAL_FW_CTRL1_BC_DP_S |\n+\t\t BIT(0) << AR8327_GLOBAL_FW_CTRL1_MC_DP_S |\n+\t\t BIT(0) << AR8327_GLOBAL_FW_CTRL1_UC_DP_S);\n+\n \t/* Setup connection between CPU ports & PHYs */\n \tfor (i = 0; i < DSA_MAX_PORTS; i++) {\n \t\t/* CPU port gets connected to all PHYs in the switch */\n@@ -312,8 +328,16 @@ static int ar8xxx_setup(struct dsa_switch *ds)\n \n \t\t/* Invividual PHYs gets connected to CPU port only */\n \t\tif (ds->phys_port_mask & BIT(i)) {\n-\t\t\tar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(phy_to_port(i)),\n+\t\t\tint phy = phy_to_port(i);\n+\n+\t\t\tar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(phy),\n \t\t\t\t AR8327_PORT_LOOKUP_MEMBER, BIT(0));\n+\n+\t\t\t/* Disable Auto-learning by default so the switch\n+\t\t\t * doesn't try to forward the frame to another port\n+\t\t\t */\n+\t\t\tar8xxx_reg_clear(ds, AR8327_PORT_LOOKUP_CTRL(phy),\n+\t\t\t\t\t AR8327_PORT_LOOKUP_LEARN);\n \t\t}\n \t}\n \n@@ -423,7 +447,7 @@ static void ar8xxx_poll_link(struct dsa_switch *ds)\n }\n \n static struct dsa_switch_driver ar8xxx_switch_driver = {\n-\t.tag_protocol\t\t= DSA_TAG_PROTO_NONE,\n+\t.tag_protocol\t\t= DSA_TAG_PROTO_QCA,\n \t.priv_size\t\t= sizeof(struct ar8xxx_priv),\n \t.probe\t\t\t= ar8xxx_probe,\n \t.setup\t\t\t= ar8xxx_setup,\ndiff --git a/drivers/net/dsa/ar8xxx.h b/drivers/net/dsa/ar8xxx.h\nindex 98cc7ed..e68b92a 100644\n--- a/drivers/net/dsa/ar8xxx.h\n+++ b/drivers/net/dsa/ar8xxx.h\n@@ -62,6 +62,28 @@ struct ar8xxx_mib_desc {\n #define AR8XXX_PORT_STATUS_LINK_AUTO\tBIT(9)\n #define AR8XXX_PORT_STATUS_LINK_PAUSE\tBIT(10)\n \n+#define AR8327_REG_PORT_HDR_CTRL(_i)\t\t(0x9c + (_i * 4))\n+#define AR8327_PORT_HDR_CTRL_RX_MASK\t\tGENMASK(3, 2)\n+#define AR8327_PORT_HDR_CTRL_RX_S\t\t2\n+#define AR8327_PORT_HDR_CTRL_TX_MASK\t\tGENMASK(1, 0)\n+#define AR8327_PORT_HDR_CTRL_TX_S\t\t0\n+#define AR8327_PORT_HDR_CTRL_ALL\t\t2\n+#define AR8327_PORT_HDR_CTRL_MGMT\t\t1\n+#define AR8327_PORT_HDR_CTRL_NONE\t\t0\n+\n+#define AR8327_REG_GLOBAL_FW_CTRL0\t\t0x620\n+#define AR8327_GLOBAL_FW_CTRL0_CPU_PORT_EN\tBIT(10)\n+\n+#define AR8327_REG_GLOBAL_FW_CTRL1\t\t0x624\n+#define AR8327_GLOBAL_FW_CTRL1_IGMP_DP_MASK\tGENMASK(30, 24)\n+#define AR8327_GLOBAL_FW_CTRL1_IGMP_DP_S\t24\n+#define AR8327_GLOBAL_FW_CTRL1_BC_DP_MASK\tGENMASK(22, 16)\n+#define AR8327_GLOBAL_FW_CTRL1_BC_DP_S\t16\n+#define AR8327_GLOBAL_FW_CTRL1_MC_DP_MASK\tGENMASK(14, 8)\n+#define AR8327_GLOBAL_FW_CTRL1_MC_DP_S\t8\n+#define AR8327_GLOBAL_FW_CTRL1_UC_DP_MASK\tGENMASK(6, 0)\n+#define AR8327_GLOBAL_FW_CTRL1_UC_DP_S\t0\n+\n #define AR8327_PORT_LOOKUP_CTRL(_i)\t\t(0x660 + (_i) * 0xc)\n #define AR8327_PORT_LOOKUP_MEMBER\t\tGENMASK(6, 0)\n #define AR8327_PORT_LOOKUP_IN_MODE\t\tGENMASK(9, 8)\n", "prefixes": [ "5/7" ] }