Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/477523/?format=api
{ "id": 477523, "url": "http://patchwork.ozlabs.org/api/patches/477523/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/patch/1432863742-18427-2-git-send-email-mathieu@codeaurora.org/", "project": { "id": 7, "url": "http://patchwork.ozlabs.org/api/projects/7/?format=api", "name": "Linux network development", "link_name": "netdev", "list_id": "netdev.vger.kernel.org", "list_email": "netdev@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1432863742-18427-2-git-send-email-mathieu@codeaurora.org>", "list_archive_url": null, "date": "2015-05-29T01:42:16", "name": "[1/7] net: dsa: add new driver for ar8xxx family", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "0bd3339a67ee6dca8aa1337120482c95c21f430f", "submitter": { "id": 65737, "url": "http://patchwork.ozlabs.org/api/people/65737/?format=api", "name": "Mathieu Olivari", "email": "mathieu@codeaurora.org" }, "delegate": { "id": 34, "url": "http://patchwork.ozlabs.org/api/users/34/?format=api", "username": "davem", "first_name": "David", "last_name": "Miller", "email": "davem@davemloft.net" }, "mbox": "http://patchwork.ozlabs.org/project/netdev/patch/1432863742-18427-2-git-send-email-mathieu@codeaurora.org/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/477523/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/477523/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<netdev-owner@vger.kernel.org>", "X-Original-To": "patchwork-incoming@ozlabs.org", "Delivered-To": "patchwork-incoming@ozlabs.org", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id BA5DA140E41\n\tfor <patchwork-incoming@ozlabs.org>;\n\tFri, 29 May 2015 11:43:33 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755383AbbE2Bn1 (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tThu, 28 May 2015 21:43:27 -0400", "from smtp.codeaurora.org ([198.145.29.96]:37403 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1753320AbbE2Bmc (ORCPT\n\t<rfc822;netdev@vger.kernel.org>); Thu, 28 May 2015 21:42:32 -0400", "from smtp.codeaurora.org (localhost [127.0.0.1])\n\tby smtp.codeaurora.org (Postfix) with ESMTP id AF092140DA3;\n\tFri, 29 May 2015 01:42:31 +0000 (UTC)", "by smtp.codeaurora.org (Postfix, from userid 486)\n\tid 99D6C140DB2; Fri, 29 May 2015 01:42:31 +0000 (UTC)", "from mathieu-linux.qualcomm.com (qf-scl1nat.qualcomm.com\n\t[207.114.132.30])\n\t(using TLSv1.2 with cipher AES128-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\t(Authenticated sender: mathieu@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id 150A5140DA3;\n\tFri, 29 May 2015 01:42:30 +0000 (UTC)" ], "X-Spam-Checker-Version": "SpamAssassin 3.3.1 (2010-03-16) on\n\tpdx-caf-smtp.dmz.codeaurora.org", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.9 required=2.0 tests=ALL_TRUSTED,BAYES_00\n\tautolearn=ham version=3.3.1", "From": "Mathieu Olivari <mathieu@codeaurora.org>", "To": "robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com,\n\tijc+devicetree@hellion.org.uk, galak@codeaurora.org,\n\tdavem@davemloft.net, mathieu@codeaurora.org, andrew@lunn.ch,\n\tf.fainelli@gmail.com, linux@roeck-us.net, gang.chen.5i5j@gmail.com,\n\tjiri@resnulli.us, leitec@staticky.com, fabf@skynet.be,\n\talexander.h.duyck@intel.com, pavel.nakonechny@skitlab.ru,\n\tjoe@perches.com, sfeldma@gmail.com, nbd@openwrt.org, juhosg@openwrt.org", "Cc": "devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tnetdev@vger.kernel.org", "Subject": "[PATCH 1/7] net: dsa: add new driver for ar8xxx family", "Date": "Thu, 28 May 2015 18:42:16 -0700", "Message-Id": "<1432863742-18427-2-git-send-email-mathieu@codeaurora.org>", "X-Mailer": "git-send-email 2.1.4", "In-Reply-To": "<1432863742-18427-1-git-send-email-mathieu@codeaurora.org>", "References": "<1432863742-18427-1-git-send-email-mathieu@codeaurora.org>", "X-Virus-Scanned": "ClamAV using ClamSMTP", "Sender": "netdev-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<netdev.vger.kernel.org>", "X-Mailing-List": "netdev@vger.kernel.org" }, "content": "This patch contains initial init & registration code for QCA8337. It\nwill detect a QCA8337 switch, if present and declared in DT/platform.\n\nEach port will be represented through a standalone net_device interface,\nas for other DSA switches. CPU can communicate with any of the ports by\nsetting an IP@ on ethN interface. Ports cannot communicate with each\nother just yet.\n\nLink status will be reported through polling, and we don't use any\nencapsulation.\n\nSigned-off-by: Mathieu Olivari <mathieu@codeaurora.org>\n---\n drivers/net/dsa/Kconfig | 7 ++\n drivers/net/dsa/Makefile | 1 +\n drivers/net/dsa/ar8xxx.c | 303 +++++++++++++++++++++++++++++++++++++++++++++++\n drivers/net/dsa/ar8xxx.h | 82 +++++++++++++\n net/dsa/dsa.c | 1 +\n 5 files changed, 394 insertions(+)\n create mode 100644 drivers/net/dsa/ar8xxx.c\n create mode 100644 drivers/net/dsa/ar8xxx.h", "diff": "diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig\nindex 7ad0a4d..2aae541 100644\n--- a/drivers/net/dsa/Kconfig\n+++ b/drivers/net/dsa/Kconfig\n@@ -65,4 +65,11 @@ config NET_DSA_BCM_SF2\n \t This enables support for the Broadcom Starfighter 2 Ethernet\n \t switch chips.\n \n+config NET_DSA_AR8XXX\n+\ttristate \"Qualcomm Atheros AR8XXX Ethernet switch family support\"\n+\tdepends on NET_DSA\n+\t---help---\n+\t This enables support for the Qualcomm Atheros AR8XXX Ethernet\n+\t switch chips.\n+\n endmenu\ndiff --git a/drivers/net/dsa/Makefile b/drivers/net/dsa/Makefile\nindex e2d51c4..7647687 100644\n--- a/drivers/net/dsa/Makefile\n+++ b/drivers/net/dsa/Makefile\n@@ -14,3 +14,4 @@ ifdef CONFIG_NET_DSA_MV88E6171\n mv88e6xxx_drv-y += mv88e6171.o\n endif\n obj-$(CONFIG_NET_DSA_BCM_SF2)\t+= bcm_sf2.o\n+obj-$(CONFIG_NET_DSA_AR8XXX)\t+= ar8xxx.o\ndiff --git a/drivers/net/dsa/ar8xxx.c b/drivers/net/dsa/ar8xxx.c\nnew file mode 100644\nindex 0000000..4ce3ffc\n--- /dev/null\n+++ b/drivers/net/dsa/ar8xxx.c\n@@ -0,0 +1,303 @@\n+/*\n+ * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>\n+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>\n+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 and\n+ * only version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/phy.h>\n+#include <linux/netdevice.h>\n+#include <net/dsa.h>\n+#include <linux/phy.h>\n+#include <linux/of_net.h>\n+\n+#include \"ar8xxx.h\"\n+\n+u32\n+ar8xxx_mii_read32(struct mii_bus *bus, int phy_id, int regnum)\n+{\n+\tu16 lo, hi;\n+\n+\tlo = bus->read(bus, phy_id, regnum);\n+\thi = bus->read(bus, phy_id, regnum + 1);\n+\n+\treturn (hi << 16) | lo;\n+}\n+\n+void\n+ar8xxx_mii_write32(struct mii_bus *bus, int phy_id, int regnum, u32 val)\n+{\n+\tu16 lo, hi;\n+\n+\tlo = val & 0xffff;\n+\thi = (u16)(val >> 16);\n+\n+\tbus->write(bus, phy_id, regnum, lo);\n+\tbus->write(bus, phy_id, regnum + 1, hi);\n+}\n+\n+u32 ar8xxx_read(struct dsa_switch *ds, int reg)\n+{\n+\tstruct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);\n+\tu16 r1, r2, page;\n+\tu32 val;\n+\n+\tsplit_addr((u32)reg, &r1, &r2, &page);\n+\n+\tmutex_lock(&bus->mdio_lock);\n+\n+\tbus->write(bus, 0x18, 0, page);\n+\twait_for_page_switch();\n+\tval = ar8xxx_mii_read32(bus, 0x10 | r2, r1);\n+\n+\tmutex_unlock(&bus->mdio_lock);\n+\n+\treturn val;\n+}\n+\n+void ar8xxx_write(struct dsa_switch *ds, int reg, u32 val)\n+{\n+\tstruct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);\n+\tu16 r1, r2, page;\n+\n+\tsplit_addr((u32)reg, &r1, &r2, &page);\n+\n+\tmutex_lock(&bus->mdio_lock);\n+\n+\tbus->write(bus, 0x18, 0, page);\n+\twait_for_page_switch();\n+\tar8xxx_mii_write32(bus, 0x10 | r2, r1, val);\n+\n+\tmutex_unlock(&bus->mdio_lock);\n+}\n+\n+u32\n+ar8xxx_rmw(struct dsa_switch *ds, int reg, u32 mask, u32 val)\n+{\n+\tstruct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);\n+\tu16 r1, r2, page;\n+\tu32 ret;\n+\n+\tsplit_addr((u32)reg, &r1, &r2, &page);\n+\n+\tmutex_lock(&bus->mdio_lock);\n+\n+\tbus->write(bus, 0x18, 0, page);\n+\twait_for_page_switch();\n+\n+\tret = ar8xxx_mii_read32(bus, 0x10 | r2, r1);\n+\tret &= ~mask;\n+\tret |= val;\n+\tar8xxx_mii_write32(bus, 0x10 | r2, r1, ret);\n+\n+\tmutex_unlock(&bus->mdio_lock);\n+\n+\treturn ret;\n+}\n+\n+static char *ar8xxx_probe(struct device *host_dev, int sw_addr)\n+{\n+\tstruct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);\n+\tu32 phy_id;\n+\n+\tif (!bus)\n+\t\treturn NULL;\n+\n+\t/* sw_addr is irrelevant as the switch occupies the MDIO bus from\n+\t * addresses 0 to 4 (PHYs) and 16-23 (for MDIO 32bits protocol). So\n+\t * we'll probe address 0 to see if we see the right switch family.\n+\t */\n+\tphy_id = mdiobus_read(bus, 0, MII_PHYSID1) << 16;\n+\tphy_id |= mdiobus_read(bus, 0, MII_PHYSID2);\n+\n+\tswitch (phy_id) {\n+\tcase PHY_ID_QCA8337:\n+\t\treturn \"QCA8337\";\n+\tdefault:\n+\t\treturn NULL;\n+\t}\n+}\n+\n+static int ar8xxx_set_pad_ctrl(struct dsa_switch *ds, int port, int mode)\n+{\n+\tint reg;\n+\n+\tswitch (port) {\n+\tcase 0:\n+\t\treg = AR8327_REG_PORT0_PAD_CTRL;\n+\t\tbreak;\n+\tcase 6:\n+\t\treg = AR8327_REG_PORT6_PAD_CTRL;\n+\t\tbreak;\n+\tdefault:\n+\t\tpr_err(\"Can't set PAD_CTRL on port %d\\n\", port);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* DSA only supports 1 CPU port for now, so we'll take the assumption\n+\t * that P0 is connected to the CPU master_dev.\n+\t */\n+\tswitch (mode) {\n+\tcase PHY_INTERFACE_MODE_RGMII:\n+\t\tar8xxx_write(ds, reg,\n+\t\t\t AR8327_PORT_PAD_RGMII_EN |\n+\t\t\t AR8327_PORT_PAD_RGMII_TX_DELAY(3) |\n+\t\t\t AR8327_PORT_PAD_RGMII_RX_DELAY(3));\n+\n+\t\t/* According to the datasheet, RGMII delay is enabled through\n+\t\t * PORT5_PAD_CTRL for all ports, rather than individual port\n+\t\t * registers\n+\t\t */\n+\t\tar8xxx_write(ds, AR8327_REG_PORT5_PAD_CTRL,\n+\t\t\t AR8327_PORT_PAD_RGMII_RX_DELAY_EN);\n+\t\tbreak;\n+\tdefault:\n+\t\tpr_err(\"xMII mode %d not supported\\n\", mode);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int ar8xxx_setup(struct dsa_switch *ds)\n+{\n+\tstruct net_device *netdev = ds->dst->pd->of_netdev;\n+\tint ret, i, phy_mode;\n+\n+\t/* Initialize CPU port pad mode (xMII type, delays...) */\n+\tphy_mode = of_get_phy_mode(netdev->dev.parent->of_node);\n+\tif (phy_mode < 0) {\n+\t\tpr_err(\"Can't find phy-mode for master device\\n\");\n+\t\treturn phy_mode;\n+\t}\n+\n+\tret = ar8xxx_set_pad_ctrl(ds, 0, phy_mode);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\t/* Disable forwarding by default on all ports */\n+\tfor (i = 0; i < AR8327_NUM_PORTS; i++)\n+\t\tar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(i),\n+\t\t\t AR8327_PORT_LOOKUP_MEMBER, 0);\n+\n+\t/* Setup connection between CPU ports & PHYs */\n+\tfor (i = 0; i < DSA_MAX_PORTS; i++) {\n+\t\t/* CPU port gets connected to all PHYs in the switch */\n+\t\tif (dsa_is_cpu_port(ds, i)) {\n+\t\t\tar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(0),\n+\t\t\t\t AR8327_PORT_LOOKUP_MEMBER,\n+\t\t\t\t ds->phys_port_mask << 1);\n+\t\t}\n+\n+\t\t/* Invividual PHYs gets connected to CPU port only */\n+\t\tif (ds->phys_port_mask & BIT(i)) {\n+\t\t\tar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(phy_to_port(i)),\n+\t\t\t\t AR8327_PORT_LOOKUP_MEMBER, BIT(0));\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int ar8xxx_set_addr(struct dsa_switch *ds, u8 *addr)\n+{\n+\treturn 0;\n+}\n+\n+static int ar8xxx_phy_read(struct dsa_switch *ds, int phy, int regnum)\n+{\n+\tstruct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);\n+\n+\treturn mdiobus_read(bus, phy, regnum);\n+}\n+\n+static int\n+ar8xxx_phy_write(struct dsa_switch *ds, int phy, int regnum, u16 val)\n+{\n+\tstruct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);\n+\n+\treturn mdiobus_write(bus, phy, regnum, val);\n+}\n+\n+static void ar8xxx_poll_link(struct dsa_switch *ds)\n+{\n+\tint i = 0;\n+\tstruct net_device *dev;\n+\n+\twhile ((dev = ds->ports[i++]) != NULL) {\n+\t\tu32 status;\n+\t\tint link;\n+\t\tint speed;\n+\t\tint duplex;\n+\n+\t\tstatus = ar8xxx_read(ds, AR8327_REG_PORT_STATUS(i));\n+\t\tlink = !!(status & AR8XXX_PORT_STATUS_LINK_UP);\n+\t\tduplex = !!(status & AR8XXX_PORT_STATUS_DUPLEX);\n+\n+\t\tswitch (status & AR8XXX_PORT_STATUS_SPEED) {\n+\t\tcase AR8XXX_PORT_SPEED_10M:\n+\t\t\tspeed = 10;\n+\t\t\tbreak;\n+\t\tcase AR8XXX_PORT_SPEED_100M:\n+\t\t\tspeed = 100;\n+\t\t\tbreak;\n+\t\tcase AR8XXX_PORT_SPEED_1000M:\n+\t\t\tspeed = 1000;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tspeed = 0;\n+\t\t}\n+\n+\t\tif (!link) {\n+\t\t\t/* This poll happens every ~1s, so we don't want to\n+\t\t\t * print the status every time. Only when the device\n+\t\t\t * transitions from Link UP to Link DOWN\n+\t\t\t */\n+\t\t\tif (netif_carrier_ok(dev))\n+\t\t\t\tnetif_carrier_off(dev);\n+\t\t\tcontinue;\n+\t\t} else {\n+\t\t\t/* Same thing here. But we detect a Link UP event */\n+\t\t\tif (!netif_carrier_ok(dev))\n+\t\t\t\tnetif_carrier_on(dev);\n+\t\t\tcontinue;\n+\t\t}\n+\t}\n+}\n+\n+static struct dsa_switch_driver ar8xxx_switch_driver = {\n+\t.tag_protocol\t= DSA_TAG_PROTO_NONE,\n+\t.probe\t\t= ar8xxx_probe,\n+\t.setup\t\t= ar8xxx_setup,\n+\t.set_addr\t= ar8xxx_set_addr,\n+\t.poll_link\t= ar8xxx_poll_link,\n+\t.phy_read\t= ar8xxx_phy_read,\n+\t.phy_write\t= ar8xxx_phy_write,\n+};\n+\n+static int __init ar8xxx_init(void)\n+{\n+\tregister_switch_driver(&ar8xxx_switch_driver);\n+\treturn 0;\n+}\n+module_init(ar8xxx_init);\n+\n+static void __exit ar8xxx_cleanup(void)\n+{\n+\tunregister_switch_driver(&ar8xxx_switch_driver);\n+}\n+module_exit(ar8xxx_cleanup);\n+\n+MODULE_AUTHOR(\"Mathieu Olivari <mathieu@codeaurora.org>\");\n+MODULE_DESCRIPTION(\"Driver for AR8XXX ethernet switch family\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_ALIAS(\"platform:ar8xxx\");\ndiff --git a/drivers/net/dsa/ar8xxx.h b/drivers/net/dsa/ar8xxx.h\nnew file mode 100644\nindex 0000000..a29b6d3\n--- /dev/null\n+++ b/drivers/net/dsa/ar8xxx.h\n@@ -0,0 +1,82 @@\n+/*\n+ * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>\n+ * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>\n+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 and\n+ * only version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ */\n+\n+#ifndef __AR8XXX_H\n+#define __AR8XXX_H\n+\n+#include <linux/delay.h>\n+\n+#define AR8327_NUM_PORTS\t\t7\n+\n+#define PHY_ID_QCA8337\t\t\t0x004dd036\n+\n+#define AR8327_REG_PORT0_PAD_CTRL\t\t0x004\n+#define AR8327_REG_PORT5_PAD_CTRL\t\t0x008\n+#define AR8327_REG_PORT6_PAD_CTRL\t\t0x00c\n+#define AR8327_PORT_PAD_RGMII_EN\t\tBIT(26)\n+#define AR8327_PORT_PAD_RGMII_TX_DELAY(x)\t((0x8 + (x & 0x3)) << 22)\n+#define AR8327_PORT_PAD_RGMII_RX_DELAY(x)\t((0x10 + (x & 0x3)) << 20)\n+#define AR8327_PORT_PAD_RGMII_RX_DELAY_EN\tBIT(24)\n+#define AR8327_PORT_PAD_SGMII_EN\t\tBIT(7)\n+\n+#define AR8327_REG_PORT_STATUS(_i)\t\t(0x07c + (_i) * 4)\n+#define AR8XXX_PORT_STATUS_SPEED\tGENMASK(2, 0)\n+#define AR8XXX_PORT_STATUS_SPEED_S\t0\n+#define AR8XXX_PORT_STATUS_TXMAC\tBIT(2)\n+#define AR8XXX_PORT_STATUS_RXMAC\tBIT(3)\n+#define AR8XXX_PORT_STATUS_TXFLOW\tBIT(4)\n+#define AR8XXX_PORT_STATUS_RXFLOW\tBIT(5)\n+#define AR8XXX_PORT_STATUS_DUPLEX\tBIT(6)\n+#define AR8XXX_PORT_STATUS_LINK_UP\tBIT(8)\n+#define AR8XXX_PORT_STATUS_LINK_AUTO\tBIT(9)\n+#define AR8XXX_PORT_STATUS_LINK_PAUSE\tBIT(10)\n+\n+#define AR8327_PORT_LOOKUP_CTRL(_i)\t\t(0x660 + (_i) * 0xc)\n+#define AR8327_PORT_LOOKUP_MEMBER\t\tGENMASK(6, 0)\n+#define AR8327_PORT_LOOKUP_IN_MODE\t\tGENMASK(9, 8)\n+#define AR8327_PORT_LOOKUP_IN_MODE_S\t\t8\n+#define AR8327_PORT_LOOKUP_STATE\t\tGENMASK(18, 16)\n+#define AR8327_PORT_LOOKUP_STATE_S\t\t16\n+#define AR8327_PORT_LOOKUP_LEARN\t\tBIT(20)\n+#define AR8327_PORT_LOOKUP_ING_MIRROR_EN\tBIT(25)\n+\n+/* port speed */\n+enum {\n+\tAR8XXX_PORT_SPEED_10M = 0,\n+\tAR8XXX_PORT_SPEED_100M = 1,\n+\tAR8XXX_PORT_SPEED_1000M = 2,\n+\tAR8XXX_PORT_SPEED_ERR = 3,\n+};\n+\n+static inline void\n+split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)\n+{\n+\tregaddr >>= 1;\n+\t*r1 = regaddr & 0x1e;\n+\n+\tregaddr >>= 5;\n+\t*r2 = regaddr & 0x7;\n+\n+\tregaddr >>= 3;\n+\t*page = regaddr & 0x1ff;\n+}\n+\n+static inline void\n+wait_for_page_switch(void)\n+{\n+\tudelay(5);\n+}\n+\n+#endif /* __AR8XXX_H */\ndiff --git a/net/dsa/dsa.c b/net/dsa/dsa.c\nindex e6f6cc3..fffb9aa 100644\n--- a/net/dsa/dsa.c\n+++ b/net/dsa/dsa.c\n@@ -893,6 +893,7 @@ static SIMPLE_DEV_PM_OPS(dsa_pm_ops, dsa_suspend, dsa_resume);\n \n static const struct of_device_id dsa_of_match_table[] = {\n \t{ .compatible = \"brcm,bcm7445-switch-v4.0\" },\n+\t{ .compatible = \"qca,ar8xxx\", },\n \t{ .compatible = \"marvell,dsa\", },\n \t{}\n };\n", "prefixes": [ "1/7" ] }