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{
    "id": 476457,
    "url": "http://patchwork.ozlabs.org/api/patches/476457/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/1432644564-24746-4-git-send-email-hanjun.guo@linaro.org/",
    "project": {
        "id": 28,
        "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api",
        "name": "Linux PCI development",
        "link_name": "linux-pci",
        "list_id": "linux-pci.vger.kernel.org",
        "list_email": "linux-pci@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<1432644564-24746-4-git-send-email-hanjun.guo@linaro.org>",
    "list_archive_url": null,
    "date": "2015-05-26T12:49:16",
    "name": "[03/11] x86, pci: Abstract PCI config accessors and use AMD Fam10h workaround exclusively.",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": false,
    "hash": "c26036d3e2538007cc666be0d4a4d20cc2a3a668",
    "submitter": {
        "id": 47236,
        "url": "http://patchwork.ozlabs.org/api/people/47236/?format=api",
        "name": "Hanjun Guo",
        "email": "hanjun.guo@linaro.org"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/1432644564-24746-4-git-send-email-hanjun.guo@linaro.org/mbox/",
    "series": [],
    "comments": "http://patchwork.ozlabs.org/api/patches/476457/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/476457/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-pci-owner@vger.kernel.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
        "Received": [
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            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753261AbbEZMxW (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tTue, 26 May 2015 08:53:22 -0400",
            "from [209.85.192.182] ([209.85.192.182]:34643 \"EHLO\n\tmail-pd0-f182.google.com\" rhost-flags-FAIL-FAIL-OK-FAIL)\n\tby vger.kernel.org with ESMTP id S1753172AbbEZMxQ (ORCPT\n\t<rfc822; linux-pci@vger.kernel.org>); Tue, 26 May 2015 08:53:16 -0400",
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        ],
        "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20130820;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=ELKGEQfTf7/fqXieW359eUc9GISBd0LXeeM1CZzD69U=;\n\tb=NMwJ8O/6jOtNFymtRJBZX6UwFt/ZoIvSgg+M6YH1DA2QwgBuOhJJoJ5QMW4Zzf5dae\n\tHBKDf6dL4j8+fWNupAHLpkhn8iF1a+gnqNs4QoocI70Ss+zzm2gXfHKLc07b8MjbslBj\n\tc+ggO+vDNCfBOKs+A4Ez3ChTCe0kiIuzQ6uVP8wd0c5UAbBZpZ1jujvS03XtP87oEhju\n\t4VxsxWqrGpbH0XSt4i5dm3uc2apu6aPwC7NcN7q1586nQaJjq1e1Ni69ebzvAxtF5a/v\n\tDSjGIfO9qeGuOwPHt5N/w97va9llH7ik3L4X4s2Rd/avA7W/otVcyuM3NdvtXpy08f+u\n\t8VWw==",
        "X-Gm-Message-State": "ALoCoQnC3YkcUSqOKj6C6Z2yxDcUgFFW1P7nk5Yj7Ortjv+3ntuNgjUQ6tmxWu3Pa8xgeOmX3UUN",
        "X-Received": "by 10.70.55.199 with SMTP id u7mr48567306pdp.42.1432644620074;\n\tTue, 26 May 2015 05:50:20 -0700 (PDT)",
        "From": "Hanjun Guo <hanjun.guo@linaro.org>",
        "To": "Bjorn Helgaas <bhelgaas@google.com>, Arnd Bergmann <arnd@arndb.de>,\n\tCatalin Marinas <catalin.marinas@arm.com>,\n\tWill Deacon <will.deacon@arm.com>,\n\t\"Rafael J. Wysocki\" <rjw@rjwysocki.net>",
        "Cc": "Jiang Liu <jiang.liu@linux.intel.com>, Liviu Dudau <Liviu.Dudau@arm.com>,\n\tThomas Gleixner <tglx@linutronix.de>,\n\tYijing Wang <wangyijing@huawei.com>,\n\tLorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>,\n\tTomasz Nowicki <tomasz.nowicki@linaro.org>,\n\tSuravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>,\n\tMark Salter <msalter@redhat.com>, linux-pci@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, linaro-acpi@lists.linaro.org,\n\tHanjun Guo <hanjun.guo@linaro.org>",
        "Subject": "[PATCH 03/11] x86,\n\tpci: Abstract PCI config accessors and use AMD Fam10h workaround\n\texclusively.",
        "Date": "Tue, 26 May 2015 20:49:16 +0800",
        "Message-Id": "<1432644564-24746-4-git-send-email-hanjun.guo@linaro.org>",
        "X-Mailer": "git-send-email 1.9.1",
        "In-Reply-To": "<1432644564-24746-1-git-send-email-hanjun.guo@linaro.org>",
        "References": "<1432644564-24746-1-git-send-email-hanjun.guo@linaro.org>",
        "Sender": "linux-pci-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<linux-pci.vger.kernel.org>",
        "X-Mailing-List": "linux-pci@vger.kernel.org"
    },
    "content": "From: Tomasz Nowicki <tomasz.nowicki@linaro.org>\n\napproach. Special MMIO accessors are registered for AMD Fam10h CPUs only.\n\nSigned-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>\nSigned-off-by: Hanjun Guo <hanjun.guo@linaro.org>\nTested-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>\n---\n arch/x86/include/asm/pci_x86.h |   8 +++\n arch/x86/pci/mmconfig-shared.c | 114 +++++++++++++++++++++++++++++++++++++++++\n arch/x86/pci/mmconfig_32.c     |  24 +--------\n arch/x86/pci/mmconfig_64.c     |  24 +--------\n arch/x86/pci/numachip.c        |  24 +--------\n 5 files changed, 128 insertions(+), 66 deletions(-)",
    "diff": "diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h\nindex eddf8f0..f7f3b6a 100644\n--- a/arch/x86/include/asm/pci_x86.h\n+++ b/arch/x86/include/asm/pci_x86.h\n@@ -139,6 +139,11 @@ struct pci_mmcfg_region {\n \tchar name[PCI_MMCFG_RESOURCE_NAME_LEN];\n };\n \n+struct pci_mmcfg_mmio_ops {\n+\tu32 (*read)(int len, void __iomem *addr);\n+\tvoid (*write)(int len, void __iomem *addr, u32 value);\n+};\n+\n extern int __init pci_mmcfg_arch_init(void);\n extern void __init pci_mmcfg_arch_free(void);\n extern int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg);\n@@ -147,6 +152,9 @@ extern int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,\n \t\t\t       phys_addr_t addr);\n extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end);\n extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);\n+extern u32 pci_mmio_read(int len, void __iomem *addr);\n+extern void pci_mmio_write(int len, void __iomem *addr, u32 value);\n+extern void pci_mmconfig_register_mmio(struct pci_mmcfg_mmio_ops *ops);\n \n extern struct list_head pci_mmcfg_list;\n \ndiff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c\nindex dd30b7e..8b3bc4f 100644\n--- a/arch/x86/pci/mmconfig-shared.c\n+++ b/arch/x86/pci/mmconfig-shared.c\n@@ -31,6 +31,118 @@ static DEFINE_MUTEX(pci_mmcfg_lock);\n \n LIST_HEAD(pci_mmcfg_list);\n \n+static u32\n+pci_mmconfig_generic_read(int len, void __iomem *addr)\n+{\n+\tu32 data = 0;\n+\n+\tswitch (len) {\n+\tcase 1:\n+\t\tdata = readb(addr);\n+\t\tbreak;\n+\tcase 2:\n+\t\tdata = readw(addr);\n+\t\tbreak;\n+\tcase 4:\n+\t\tdata = readl(addr);\n+\t\tbreak;\n+\t}\n+\n+\treturn data;\n+}\n+\n+static void\n+pci_mmconfig_generic_write(int len, void __iomem *addr, u32 value)\n+{\n+\tswitch (len) {\n+\tcase 1:\n+\t\twriteb(value, addr);\n+\t\tbreak;\n+\tcase 2:\n+\t\twritew(value, addr);\n+\t\tbreak;\n+\tcase 4:\n+\t\twritel(value, addr);\n+\t\tbreak;\n+\t}\n+}\n+\n+static struct pci_mmcfg_mmio_ops pci_mmcfg_mmio_default = {\n+\t.read = pci_mmconfig_generic_read,\n+\t.write = pci_mmconfig_generic_write,\n+};\n+\n+static struct pci_mmcfg_mmio_ops *pci_mmcfg_mmio = &pci_mmcfg_mmio_default;\n+\n+static u32\n+pci_mmconfig_amd_read(int len, void __iomem *addr)\n+{\n+\tu32 data = 0;\n+\n+\tswitch (len) {\n+\tcase 1:\n+\t\tdata = mmio_config_readb(addr);\n+\t\tbreak;\n+\tcase 2:\n+\t\tdata = mmio_config_readw(addr);\n+\t\tbreak;\n+\tcase 4:\n+\t\tdata = mmio_config_readl(addr);\n+\t\tbreak;\n+\t}\n+\n+\treturn data;\n+}\n+\n+static void\n+pci_mmconfig_amd_write(int len, void __iomem *addr, u32 value)\n+{\n+\tswitch (len) {\n+\tcase 1:\n+\t\tmmio_config_writeb(addr, value);\n+\t\tbreak;\n+\tcase 2:\n+\t\tmmio_config_writew(addr, value);\n+\t\tbreak;\n+\tcase 4:\n+\t\tmmio_config_writel(addr, value);\n+\t\tbreak;\n+\t}\n+}\n+\n+static struct pci_mmcfg_mmio_ops pci_mmcfg_mmio_amd_fam10h = {\n+\t.read = pci_mmconfig_amd_read,\n+\t.write = pci_mmconfig_amd_write,\n+};\n+\n+void\n+pci_mmconfig_register_mmio(struct pci_mmcfg_mmio_ops *ops)\n+{\n+\tpci_mmcfg_mmio = ops;\n+}\n+\n+u32\n+pci_mmio_read(int len, void __iomem *addr)\n+{\n+\tif (!pci_mmcfg_mmio) {\n+\t\tpr_err(\"PCI config space has no accessors !\");\n+\t\treturn 0;\n+\t}\n+\n+\treturn pci_mmcfg_mmio->read(len, addr);\n+}\n+\n+void\n+pci_mmio_write(int len, void __iomem *addr, u32 value)\n+{\n+\tif (!pci_mmcfg_mmio) {\n+\t\tpr_err(\"PCI config space has no accessors !\");\n+\t\treturn;\n+\t}\n+\n+\tpci_mmcfg_mmio->write(len, addr, value);\n+}\n+\n static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg)\n {\n \tif (cfg->res.parent)\n@@ -231,6 +343,8 @@ static const char *__init pci_mmcfg_amd_fam10h(void)\n \t\t\treturn NULL;\n \t\t}\n \n+\tpci_mmconfig_register_mmio(&pci_mmcfg_mmio_amd_fam10h);\n+\n \treturn \"AMD Family 10h NB\";\n }\n \ndiff --git a/arch/x86/pci/mmconfig_32.c b/arch/x86/pci/mmconfig_32.c\nindex 43984bc..4b3d025 100644\n--- a/arch/x86/pci/mmconfig_32.c\n+++ b/arch/x86/pci/mmconfig_32.c\n@@ -71,17 +71,7 @@ err:\t\t*value = -1;\n \n \tpci_exp_set_dev_base(base, bus, devfn);\n \n-\tswitch (len) {\n-\tcase 1:\n-\t\t*value = mmio_config_readb(mmcfg_virt_addr + reg);\n-\t\tbreak;\n-\tcase 2:\n-\t\t*value = mmio_config_readw(mmcfg_virt_addr + reg);\n-\t\tbreak;\n-\tcase 4:\n-\t\t*value = mmio_config_readl(mmcfg_virt_addr + reg);\n-\t\tbreak;\n-\t}\n+\t*value = pci_mmio_read(len, mmcfg_virt_addr + reg);\n \traw_spin_unlock_irqrestore(&pci_config_lock, flags);\n \trcu_read_unlock();\n \n@@ -108,17 +98,7 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus,\n \n \tpci_exp_set_dev_base(base, bus, devfn);\n \n-\tswitch (len) {\n-\tcase 1:\n-\t\tmmio_config_writeb(mmcfg_virt_addr + reg, value);\n-\t\tbreak;\n-\tcase 2:\n-\t\tmmio_config_writew(mmcfg_virt_addr + reg, value);\n-\t\tbreak;\n-\tcase 4:\n-\t\tmmio_config_writel(mmcfg_virt_addr + reg, value);\n-\t\tbreak;\n-\t}\n+\tpci_mmio_write(len, mmcfg_virt_addr + reg, value);\n \traw_spin_unlock_irqrestore(&pci_config_lock, flags);\n \trcu_read_unlock();\n \ndiff --git a/arch/x86/pci/mmconfig_64.c b/arch/x86/pci/mmconfig_64.c\nindex bea5249..032593d 100644\n--- a/arch/x86/pci/mmconfig_64.c\n+++ b/arch/x86/pci/mmconfig_64.c\n@@ -42,17 +42,7 @@ err:\t\t*value = -1;\n \t\tgoto err;\n \t}\n \n-\tswitch (len) {\n-\tcase 1:\n-\t\t*value = mmio_config_readb(addr + reg);\n-\t\tbreak;\n-\tcase 2:\n-\t\t*value = mmio_config_readw(addr + reg);\n-\t\tbreak;\n-\tcase 4:\n-\t\t*value = mmio_config_readl(addr + reg);\n-\t\tbreak;\n-\t}\n+\t*value = pci_mmio_read(len, addr + reg);\n \trcu_read_unlock();\n \n \treturn 0;\n@@ -74,17 +64,7 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus,\n \t\treturn -EINVAL;\n \t}\n \n-\tswitch (len) {\n-\tcase 1:\n-\t\tmmio_config_writeb(addr + reg, value);\n-\t\tbreak;\n-\tcase 2:\n-\t\tmmio_config_writew(addr + reg, value);\n-\t\tbreak;\n-\tcase 4:\n-\t\tmmio_config_writel(addr + reg, value);\n-\t\tbreak;\n-\t}\n+\tpci_mmio_write(len, addr + reg, value);\n \trcu_read_unlock();\n \n \treturn 0;\ndiff --git a/arch/x86/pci/numachip.c b/arch/x86/pci/numachip.c\nindex 2e565e6..5047e9b 100644\n--- a/arch/x86/pci/numachip.c\n+++ b/arch/x86/pci/numachip.c\n@@ -51,17 +51,7 @@ err:\t\t*value = -1;\n \t\tgoto err;\n \t}\n \n-\tswitch (len) {\n-\tcase 1:\n-\t\t*value = mmio_config_readb(addr + reg);\n-\t\tbreak;\n-\tcase 2:\n-\t\t*value = mmio_config_readw(addr + reg);\n-\t\tbreak;\n-\tcase 4:\n-\t\t*value = mmio_config_readl(addr + reg);\n-\t\tbreak;\n-\t}\n+\t*value = pci_mmio_read(len, addr + reg);\n \trcu_read_unlock();\n \n \treturn 0;\n@@ -87,17 +77,7 @@ static int pci_mmcfg_write_numachip(unsigned int seg, unsigned int bus,\n \t\treturn -EINVAL;\n \t}\n \n-\tswitch (len) {\n-\tcase 1:\n-\t\tmmio_config_writeb(addr + reg, value);\n-\t\tbreak;\n-\tcase 2:\n-\t\tmmio_config_writew(addr + reg, value);\n-\t\tbreak;\n-\tcase 4:\n-\t\tmmio_config_writel(addr + reg, value);\n-\t\tbreak;\n-\t}\n+\tpci_mmio_write(len, addr + reg, value);\n \trcu_read_unlock();\n \n \treturn 0;\n",
    "prefixes": [
        "03/11"
    ]
}