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GET /api/patches/476455/?format=api
{ "id": 476455, "url": "http://patchwork.ozlabs.org/api/patches/476455/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/1432644564-24746-5-git-send-email-hanjun.guo@linaro.org/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1432644564-24746-5-git-send-email-hanjun.guo@linaro.org>", "list_archive_url": null, "date": "2015-05-26T12:49:17", "name": "[04/11] x86, pci: Reorder logic of pci_mmconfig_insert() function", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "42e35f035ffbb8f40b135e9506aa87bb33b214cc", "submitter": { "id": 47236, "url": "http://patchwork.ozlabs.org/api/people/47236/?format=api", "name": "Hanjun Guo", "email": "hanjun.guo@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/1432644564-24746-5-git-send-email-hanjun.guo@linaro.org/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/476455/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/476455/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-pci-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 51BC5140E0F\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 26 May 2015 23:19:39 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753139AbbEZMxR (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tTue, 26 May 2015 08:53:17 -0400", "from [209.85.192.174] ([209.85.192.174]:34819 \"EHLO\n\tmail-pd0-f174.google.com\" rhost-flags-FAIL-FAIL-OK-FAIL)\n\tby vger.kernel.org with ESMTP id S1753117AbbEZMxP (ORCPT\n\t<rfc822; linux-pci@vger.kernel.org>); Tue, 26 May 2015 08:53:15 -0400", "by pdea3 with SMTP id a3so90223914pde.2\n\tfor <linux-pci@vger.kernel.org>; Tue, 26 May 2015 05:50:24 -0700 (PDT)", "from localhost ([180.150.153.56]) by mx.google.com with ESMTPSA id\n\tnq2sm13047509pdb.70.2015.05.26.05.50.23\n\t(version=TLSv1.2 cipher=RC4-SHA bits=128/128);\n\tTue, 26 May 2015 05:50:24 -0700 (PDT)" ], "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20130820;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=Bpc/6Mda+qd+HsEVWDdbPhc46eVLDB5dYjHM6VRId2o=;\n\tb=C1OD9C3Ki8bA4/JDAg6/SMCuPflsV7XrvjopYvaG0hiaMG66wKVVWczuRVc84dAdr2\n\tUENMScND8tU71EFKujkrbUilNajEI/5kke7z1gvbvUno/H7DgMq+ZA3ugbPy3bcOVtCj\n\tMeY3LC/4rhiaUjscdIvS8jkijHxQARNFSJsP2is8KryY9JvgwHJRJmnzmTQlo0D3d1P8\n\tdRSoL2nKeEObwCZ7glPsNFfLKnziHqAhUUVarKcFRoWbwpP9s+L8jUP5cNVF2jI9Cctt\n\t3QjH5zZsd4K9g3ZfBUKuH9VrZyRNxfQV3HmEwtRKxrKYbdEkikKgO+3jQyKQN8TNuEgw\n\tP4gg==", "X-Gm-Message-State": "ALoCoQkXFEpA4kBnIJDuqgDZCfyUhFN1Drpby5u3ywtXZNL8LNpBlOde26qfR+tEK0ZAe1Il4Rld", "X-Received": "by 10.68.65.17 with SMTP id t17mr49065487pbs.9.1432644624778;\n\tTue, 26 May 2015 05:50:24 -0700 (PDT)", "From": "Hanjun Guo <hanjun.guo@linaro.org>", "To": "Bjorn Helgaas <bhelgaas@google.com>, Arnd Bergmann <arnd@arndb.de>,\n\tCatalin Marinas <catalin.marinas@arm.com>,\n\tWill Deacon <will.deacon@arm.com>,\n\t\"Rafael J. Wysocki\" <rjw@rjwysocki.net>", "Cc": "Jiang Liu <jiang.liu@linux.intel.com>, Liviu Dudau <Liviu.Dudau@arm.com>,\n\tThomas Gleixner <tglx@linutronix.de>,\n\tYijing Wang <wangyijing@huawei.com>,\n\tLorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>,\n\tTomasz Nowicki <tomasz.nowicki@linaro.org>,\n\tSuravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>,\n\tMark Salter <msalter@redhat.com>, linux-pci@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, linaro-acpi@lists.linaro.org,\n\tHanjun Guo <hanjun.guo@linaro.org>", "Subject": "[PATCH 04/11] x86,\n\tpci: Reorder logic of pci_mmconfig_insert() function", "Date": "Tue, 26 May 2015 20:49:17 +0800", "Message-Id": "<1432644564-24746-5-git-send-email-hanjun.guo@linaro.org>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1432644564-24746-1-git-send-email-hanjun.guo@linaro.org>", "References": "<1432644564-24746-1-git-send-email-hanjun.guo@linaro.org>", "Sender": "linux-pci-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-pci.vger.kernel.org>", "X-Mailing-List": "linux-pci@vger.kernel.org" }, "content": "From: Tomasz Nowicki <tomasz.nowicki@linaro.org>\n\nThis patch is the first step for MMCONFIG refactoring process.\n\nCode that uses pci_mmcfg_lock will be moved to common file and become\naccessible for all architectures. pci_mmconfig_insert() cannot be moved\nso easily since it is mixing generic mmconfig code with x86 specific logic\ninside of mutual exclusive block guarded by pci_mmcfg_lock.\n\nTo get rid of that constraint, we reorder actions as follow:\n1. sanity check for mmconfig region presence, if we already have such\nregion it doesn't make snese to alloc new mmconfig list entry\n2. mmconfig entry allocation, no need to lock\n3. insertion to iomem_resource has its own lock, no need to wrap it into mutex\n4. insertion to mmconfig list can be done as the final step in separate\nfunction (candidate for further refactoring) and needs another mmconfig\nlookup to avoid race condition.\n\nSigned-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>\nSigned-off-by: Hanjun Guo <hanjun.guo@linaro.org>\nTested-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>\n---\n arch/x86/pci/mmconfig-shared.c | 99 +++++++++++++++++++++++-------------------\n 1 file changed, 54 insertions(+), 45 deletions(-)", "diff": "diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c\nindex 8b3bc4f..e770b70 100644\n--- a/arch/x86/pci/mmconfig-shared.c\n+++ b/arch/x86/pci/mmconfig-shared.c\n@@ -834,6 +834,38 @@ static int __init pci_mmcfg_late_insert_resources(void)\n */\n late_initcall(pci_mmcfg_late_insert_resources);\n \n+static int pci_mmconfig_inject(struct pci_mmcfg_region *cfg)\n+{\n+\tstruct pci_mmcfg_region *cfg_conflict;\n+\tint err = 0;\n+\n+\tmutex_lock(&pci_mmcfg_lock);\n+\tcfg_conflict = pci_mmconfig_lookup(cfg->segment, cfg->start_bus);\n+\tif (cfg_conflict) {\n+\t\tif (cfg_conflict->end_bus < cfg->end_bus)\n+\t\t\tpr_info(FW_INFO \"MMCONFIG for \"\n+\t\t\t\t\"domain %04x [bus %02x-%02x] \"\n+\t\t\t\t\"only partially covers this bridge\\n\",\n+\t\t\t\tcfg_conflict->segment, cfg_conflict->start_bus,\n+\t\t\t\tcfg_conflict->end_bus);\n+\t\terr = -EEXIST;\n+\t\tgoto out;\n+\t}\n+\n+\tif (pci_mmcfg_arch_map(cfg)) {\n+\t\tpr_warn(\"fail to map MMCONFIG %pR.\\n\", &cfg->res);\n+\t\terr = -ENOMEM;\n+\t\tgoto out;\n+\t} else {\n+\t\tlist_add_sorted(cfg);\n+\t\tpr_info(\"MMCONFIG at %pR (base %#lx)\\n\",\n+\t\t\t&cfg->res, (unsigned long)cfg->address);\n+\t}\n+out:\n+\tmutex_unlock(&pci_mmcfg_lock);\n+\treturn err;\n+}\n+\n /* Add MMCFG information for host bridges */\n int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,\n \t\t\tphys_addr_t addr)\n@@ -845,66 +877,43 @@ int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,\n \tif (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed)\n \t\treturn -ENODEV;\n \n-\tif (start > end)\n+\tif ((start > end) || !addr)\n \t\treturn -EINVAL;\n \n-\tmutex_lock(&pci_mmcfg_lock);\n+\trcu_read_lock();\n \tcfg = pci_mmconfig_lookup(seg, start);\n-\tif (cfg) {\n-\t\tif (cfg->end_bus < end)\n-\t\t\tdev_info(dev, FW_INFO\n-\t\t\t\t \"MMCONFIG for \"\n-\t\t\t\t \"domain %04x [bus %02x-%02x] \"\n-\t\t\t\t \"only partially covers this bridge\\n\",\n-\t\t\t\t cfg->segment, cfg->start_bus, cfg->end_bus);\n-\t\tmutex_unlock(&pci_mmcfg_lock);\n+\trcu_read_unlock();\n+\tif (cfg)\n \t\treturn -EEXIST;\n-\t}\n-\n-\tif (!addr) {\n-\t\tmutex_unlock(&pci_mmcfg_lock);\n-\t\treturn -EINVAL;\n-\t}\n \n-\trc = -EBUSY;\n \tcfg = pci_mmconfig_alloc(seg, start, end, addr);\n-\tif (cfg == NULL) {\n+\tif (!cfg) {\n \t\tdev_warn(dev, \"fail to add MMCONFIG (out of memory)\\n\");\n-\t\trc = -ENOMEM;\n+\t\treturn -ENOMEM;\n \t} else if (!pci_mmcfg_check_reserved(dev, cfg, 0)) {\n \t\tdev_warn(dev, FW_BUG \"MMCONFIG %pR isn't reserved\\n\",\n \t\t\t &cfg->res);\n-\t} else {\n-\t\t/* Insert resource if it's not in boot stage */\n-\t\tif (pci_mmcfg_running_state)\n-\t\t\ttmp = insert_resource_conflict(&iomem_resource,\n-\t\t\t\t\t\t &cfg->res);\n-\n-\t\tif (tmp) {\n-\t\t\tdev_warn(dev,\n-\t\t\t\t \"MMCONFIG %pR conflicts with \"\n-\t\t\t\t \"%s %pR\\n\",\n-\t\t\t\t &cfg->res, tmp->name, tmp);\n-\t\t} else if (pci_mmcfg_arch_map(cfg)) {\n-\t\t\tdev_warn(dev, \"fail to map MMCONFIG %pR.\\n\",\n-\t\t\t\t &cfg->res);\n-\t\t} else {\n-\t\t\tlist_add_sorted(cfg);\n-\t\t\tdev_info(dev, \"MMCONFIG at %pR (base %#lx)\\n\",\n-\t\t\t\t &cfg->res, (unsigned long)addr);\n-\t\t\tcfg = NULL;\n-\t\t\trc = 0;\n-\t\t}\n+\t\tgoto error;\n \t}\n \n-\tif (cfg) {\n-\t\tif (cfg->res.parent)\n-\t\t\trelease_resource(&cfg->res);\n-\t\tkfree(cfg);\n+\t/* Insert resource if it's not in boot stage */\n+\tif (pci_mmcfg_running_state)\n+\t\ttmp = insert_resource_conflict(&iomem_resource, &cfg->res);\n+\n+\tif (tmp) {\n+\t\tdev_warn(dev, \"MMCONFIG %pR conflicts with %s %pR\\n\",\n+\t\t\t &cfg->res, tmp->name, tmp);\n+\t\tgoto error;\n \t}\n \n-\tmutex_unlock(&pci_mmcfg_lock);\n+\trc = pci_mmconfig_inject(cfg);\n+\tif (!rc)\n+\t\treturn 0;\n \n+error:\n+\tif (cfg->res.parent)\n+\t\trelease_resource(&cfg->res);\n+\tkfree(cfg);\n \treturn rc;\n }\n \n", "prefixes": [ "04/11" ] }