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{
    "id": 476450,
    "url": "http://patchwork.ozlabs.org/api/patches/476450/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/1432644564-24746-3-git-send-email-hanjun.guo@linaro.org/",
    "project": {
        "id": 28,
        "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api",
        "name": "Linux PCI development",
        "link_name": "linux-pci",
        "list_id": "linux-pci.vger.kernel.org",
        "list_email": "linux-pci@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<1432644564-24746-3-git-send-email-hanjun.guo@linaro.org>",
    "list_archive_url": null,
    "date": "2015-05-26T12:49:15",
    "name": "[02/11] x86, pci: Clean up comment about buggy MMIO config space access for AMD Fam10h CPUs.",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": false,
    "hash": "3a91be5f8b89881dc49f29ef1049bc712a3d47c3",
    "submitter": {
        "id": 47236,
        "url": "http://patchwork.ozlabs.org/api/people/47236/?format=api",
        "name": "Hanjun Guo",
        "email": "hanjun.guo@linaro.org"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/1432644564-24746-3-git-send-email-hanjun.guo@linaro.org/mbox/",
    "series": [],
    "comments": "http://patchwork.ozlabs.org/api/patches/476450/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/476450/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-pci-owner@vger.kernel.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
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        ],
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        "X-Received": "by 10.70.29.164 with SMTP id l4mr48515657pdh.32.1432644615402;\n\tTue, 26 May 2015 05:50:15 -0700 (PDT)",
        "From": "Hanjun Guo <hanjun.guo@linaro.org>",
        "To": "Bjorn Helgaas <bhelgaas@google.com>, Arnd Bergmann <arnd@arndb.de>,\n\tCatalin Marinas <catalin.marinas@arm.com>,\n\tWill Deacon <will.deacon@arm.com>,\n\t\"Rafael J. Wysocki\" <rjw@rjwysocki.net>",
        "Cc": "Jiang Liu <jiang.liu@linux.intel.com>, Liviu Dudau <Liviu.Dudau@arm.com>,\n\tThomas Gleixner <tglx@linutronix.de>,\n\tYijing Wang <wangyijing@huawei.com>,\n\tLorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>,\n\tTomasz Nowicki <tomasz.nowicki@linaro.org>,\n\tSuravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>,\n\tMark Salter <msalter@redhat.com>, linux-pci@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, linaro-acpi@lists.linaro.org,\n\tHanjun Guo <hanjun.guo@linaro.org>",
        "Subject": "[PATCH 02/11] x86,\n\tpci: Clean up comment about buggy MMIO config space access for AMD\n\tFam10h CPUs.",
        "Date": "Tue, 26 May 2015 20:49:15 +0800",
        "Message-Id": "<1432644564-24746-3-git-send-email-hanjun.guo@linaro.org>",
        "X-Mailer": "git-send-email 1.9.1",
        "In-Reply-To": "<1432644564-24746-1-git-send-email-hanjun.guo@linaro.org>",
        "References": "<1432644564-24746-1-git-send-email-hanjun.guo@linaro.org>",
        "Sender": "linux-pci-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<linux-pci.vger.kernel.org>",
        "X-Mailing-List": "linux-pci@vger.kernel.org"
    },
    "content": "From: Tomasz Nowicki <tomasz.nowicki@linaro.org>\n\n- fix typo\n- improve explanation\n- add reference to the related document\n\nSigned-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>\nSigned-off-by: Hanjun Guo <hanjun.guo@linaro.org>\nTested-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>\n---\n arch/x86/include/asm/pci_x86.h | 9 ++++++---\n 1 file changed, 6 insertions(+), 3 deletions(-)",
    "diff": "diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h\nindex 164e3f8..eddf8f0 100644\n--- a/arch/x86/include/asm/pci_x86.h\n+++ b/arch/x86/include/asm/pci_x86.h\n@@ -154,10 +154,13 @@ extern struct list_head pci_mmcfg_list;\n \n /*\n  * AMD Fam10h CPUs are buggy, and cannot access MMIO config space\n- * on their northbrige except through the * %eax register. As such, you MUST\n- * NOT use normal IOMEM accesses, you need to only use the magic mmio-config\n+ * on their northbridge except through the * %eax register. As such, you MUST\n+ * NOT use normal IOMEM accesses, you need to only use the magic mmio_config_*\n  * accessor functions.\n- * In fact just use pci_config_*, nothing else please.\n+ *\n+ * Please refer to the following doc:\n+ * \"BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors\",\n+ * rev. 3.48, sec 2.11.1, \"MMIO Configuration Coding Requirements\".\n  */\n static inline unsigned char mmio_config_readb(void __iomem *pos)\n {\n",
    "prefixes": [
        "02/11"
    ]
}