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GET /api/patches/466687/?format=api
{ "id": 466687, "url": "http://patchwork.ozlabs.org/api/patches/466687/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1430417955-28252-2-git-send-email-tharvey@gateworks.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1430417955-28252-2-git-send-email-tharvey@gateworks.com>", "list_archive_url": null, "date": "2015-04-30T18:19:13", "name": "[1/3] net: igb: add i210/i211 support for phy read/write", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "e2245d0c067933c94a22d2cc8fc68e89f4452b0b", "submitter": { "id": 41730, "url": "http://patchwork.ozlabs.org/api/people/41730/?format=api", "name": "Tim Harvey", "email": "tharvey@gateworks.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1430417955-28252-2-git-send-email-tharvey@gateworks.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/466687/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/466687/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from whitealder.osuosl.org (whitealder.osuosl.org\n\t[140.211.166.138])\n\tby ozlabs.org (Postfix) with ESMTP id 59E5A140323\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 1 May 2015 04:24:49 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 75F5E91ADE;\n\tThu, 30 Apr 2015 18:24:48 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id ZluZtGBgn18z; Thu, 30 Apr 2015 18:24:47 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id EB4F0919DE;\n\tThu, 30 Apr 2015 18:24:47 +0000 (UTC)", "from whitealder.osuosl.org (whitealder.osuosl.org\n\t[140.211.166.138])\n\tby ash.osuosl.org (Postfix) with ESMTP id A27761BFA96\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 30 Apr 2015 18:24:47 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 9BA45919DE\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 30 Apr 2015 18:24:47 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id ao95QdOAspZI for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 30 Apr 2015 18:24:46 +0000 (UTC)", "from mail-pd0-f169.google.com (mail-pd0-f169.google.com\n\t[209.85.192.169])\n\tby whitealder.osuosl.org (Postfix) with ESMTPS id B7A3B91AD9\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 30 Apr 2015 18:24:46 +0000 (UTC)", "by pdea3 with SMTP id a3so68325544pde.3\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 30 Apr 2015 11:24:46 -0700 (PDT)", "from tharvey.gw (68-189-91-139.static.snlo.ca.charter.com.\n\t[68.189.91.139]) by mx.google.com with ESMTPSA id\n\tbs4sm2821374pdb.21.2015.04.30.11.19.20\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tThu, 30 Apr 2015 11:19:21 -0700 (PDT)" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "delayed 00:05:26 by SQLgrey-1.7.6", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20130820;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=xvrTzNgsjE9Gsn17tCxiWvCBxqAAM1NncEaleX+gbHQ=;\n\tb=UVrE9N32as41RixuegZLVivOaYx1wqaoJii+CIbaoEhUv+Mj81mQxUf2ZMhv4dfrVg\n\tZqEspYqUiwT4DQzK0c8A6gTF+rHtk1iSlxpqs0MS6jj276tSGu/3l+RM7y8eBCwSeILS\n\t+2xCLHkGKaPyURfWvReCg6nhyovCqBZUmmr8xY8jSkeQ2w1Z/6kbrmrzHehmxFnynXb2\n\tdAZiVAJ+45neMJm1XacWGs4pUAyS4Zv3t4RNDnYwm5nLG3dGv70VVX7elREokPS5cGIs\n\tazToxtz9KFbntOmsCvWRehf6Lr/hAUwZJAg5i6BqXMIdxOPniWpmpAQS3kM9PU+xRaJh\n\tikXg==", "X-Gm-Message-State": "ALoCoQnhRa+ywurOeAEs++CGJB3CAkeoE51BYVU6hEJoQO17gU+WFlJPcb10s/3uItfu3AHK4lak", "X-Received": "by 10.70.129.133 with SMTP id nw5mr10433971pdb.155.1430417961766;\n\tThu, 30 Apr 2015 11:19:21 -0700 (PDT)", "From": "Tim Harvey <tharvey@gateworks.com>", "To": "Jeff Kirsher <jeffrey.t.kirsher@intel.com>", "Date": "Thu, 30 Apr 2015 11:19:13 -0700", "Message-Id": "<1430417955-28252-2-git-send-email-tharvey@gateworks.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1430417955-28252-1-git-send-email-tharvey@gateworks.com>", "References": "<1430417955-28252-1-git-send-email-tharvey@gateworks.com>", "Cc": "intel-wired-lan@lists.osuosl.org", "Subject": "[Intel-wired-lan] [PATCH 1/3] net: igb: add i210/i211 support for\n\tphy read/write", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "The i210/i211 uses the MDICNFG register for the phy address instead\nof the MDIC register.\n\nSigned-off-by: Tim Harvey <tharvey@gateworks.com>\n---\n drivers/net/ethernet/intel/igb/e1000_phy.c | 71 ++++++++++++++++++++++++++----\n 1 file changed, 62 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/igb/e1000_phy.c b/drivers/net/ethernet/intel/igb/e1000_phy.c\nindex c1bb64d..2307ac6 100644\n--- a/drivers/net/ethernet/intel/igb/e1000_phy.c\n+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c\n@@ -135,7 +135,7 @@ out:\n s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)\n {\n \tstruct e1000_phy_info *phy = &hw->phy;\n-\tu32 i, mdic = 0;\n+\tu32 i, mdicnfg, mdic = 0;\n \ts32 ret_val = 0;\n \n \tif (offset > MAX_PHY_REG_ADDRESS) {\n@@ -148,11 +148,25 @@ s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)\n \t * Control register. The MAC will take care of interfacing with the\n \t * PHY to retrieve the desired data.\n \t */\n-\tmdic = ((offset << E1000_MDIC_REG_SHIFT) |\n-\t\t(phy->addr << E1000_MDIC_PHY_SHIFT) |\n-\t\t(E1000_MDIC_OP_READ));\n+\tswitch (hw->mac.type) {\n+\tcase e1000_i210:\n+\tcase e1000_i211:\n+\t\tmdicnfg = rd32(E1000_MDICNFG);\n+\t\tmdicnfg &= ~(E1000_MDICNFG_PHY_MASK);\n+\t\tmdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);\n+\t\twr32(E1000_MDICNFG, mdicnfg);\n+\t\tmdic = ((offset << E1000_MDIC_REG_SHIFT) |\n+\t\t\t(E1000_MDIC_OP_READ));\n+\t\tbreak;\n+\tdefault:\n+\t\tmdic = ((offset << E1000_MDIC_REG_SHIFT) |\n+\t\t\t(phy->addr << E1000_MDIC_PHY_SHIFT) |\n+\t\t\t(E1000_MDIC_OP_READ));\n+\t\tbreak;\n+\t}\n \n \twr32(E1000_MDIC, mdic);\n+\twrfl();\n \n \t/* Poll the ready bit to see if the MDI read completed\n \t * Increasing the time out as testing showed failures with\n@@ -177,6 +191,18 @@ s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)\n \t*data = (u16) mdic;\n \n out:\n+\tswitch (hw->mac.type) {\n+\t/* restore MDICNFG to have phy's addr */\n+\tcase e1000_i210:\n+\tcase e1000_i211:\n+\t\tmdicnfg = rd32(E1000_MDICNFG);\n+\t\tmdicnfg &= ~(E1000_MDICNFG_PHY_MASK);\n+\t\tmdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT);\n+\t\twr32(E1000_MDICNFG, mdicnfg);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n \treturn ret_val;\n }\n \n@@ -191,7 +217,7 @@ out:\n s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)\n {\n \tstruct e1000_phy_info *phy = &hw->phy;\n-\tu32 i, mdic = 0;\n+\tu32 i, mdicnfg, mdic = 0;\n \ts32 ret_val = 0;\n \n \tif (offset > MAX_PHY_REG_ADDRESS) {\n@@ -204,12 +230,27 @@ s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)\n \t * Control register. The MAC will take care of interfacing with the\n \t * PHY to retrieve the desired data.\n \t */\n-\tmdic = (((u32)data) |\n-\t\t(offset << E1000_MDIC_REG_SHIFT) |\n-\t\t(phy->addr << E1000_MDIC_PHY_SHIFT) |\n-\t\t(E1000_MDIC_OP_WRITE));\n+\tswitch (hw->mac.type) {\n+\tcase e1000_i210:\n+\tcase e1000_i211:\n+\t\tmdicnfg = rd32(E1000_MDICNFG);\n+\t\tmdicnfg &= ~(E1000_MDICNFG_PHY_MASK);\n+\t\tmdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT);\n+\t\twr32(E1000_MDICNFG, mdicnfg);\n+\t\tmdic = (((u32)data) |\n+\t\t\t(offset << E1000_MDIC_REG_SHIFT) |\n+\t\t\t(E1000_MDIC_OP_WRITE));\n+\t\tbreak;\n+\tdefault:\n+\t\tmdic = (((u32)data) |\n+\t\t\t(offset << E1000_MDIC_REG_SHIFT) |\n+\t\t\t(phy->addr << E1000_MDIC_PHY_SHIFT) |\n+\t\t\t(E1000_MDIC_OP_WRITE));\n+\t\tbreak;\n+\t}\n \n \twr32(E1000_MDIC, mdic);\n+\twrfl();\n \n \t/* Poll the ready bit to see if the MDI read completed\n \t * Increasing the time out as testing showed failures with\n@@ -233,6 +274,18 @@ s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)\n \t}\n \n out:\n+\tswitch (hw->mac.type) {\n+\t/* restore MDICNFG to have phy's addr */\n+\tcase e1000_i210:\n+\tcase e1000_i211:\n+\t\tmdicnfg = rd32(E1000_MDICNFG);\n+\t\tmdicnfg &= ~(E1000_MDICNFG_PHY_MASK);\n+\t\tmdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT);\n+\t\twr32(E1000_MDICNFG, mdicnfg);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n \treturn ret_val;\n }\n \n", "prefixes": [ "1/3" ] }