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GET /api/patches/465196/?format=api
{ "id": 465196, "url": "http://patchwork.ozlabs.org/api/patches/465196/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1430161042-28494-12-git-send-email-catherine.sullivan@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1430161042-28494-12-git-send-email-catherine.sullivan@intel.com>", "list_archive_url": null, "date": "2015-04-27T18:57:18", "name": "[net-next,S5,11/15] i40e/i40evf: Fix and refactor dynamic ITR code", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "1fdf09dad7a2d921f992dff1af2bcbc22904167d", "submitter": { "id": 13931, "url": "http://patchwork.ozlabs.org/api/people/13931/?format=api", "name": "Catherine Sullivan", "email": "catherine.sullivan@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/1430161042-28494-12-git-send-email-catherine.sullivan@intel.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/465196/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/465196/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@lists.osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Received": [ "from fraxinus.osuosl.org (fraxinus.osuosl.org [140.211.166.137])\n\tby ozlabs.org (Postfix) with ESMTP id A30A21400DE\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 28 Apr 2015 04:54:57 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id F0F3CA12BC;\n\tMon, 27 Apr 2015 18:54:56 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id of1ncsW8EDiy; Mon, 27 Apr 2015 18:54:56 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 162818BF0F;\n\tMon, 27 Apr 2015 18:54:56 +0000 (UTC)", "from whitealder.osuosl.org (whitealder.osuosl.org\n\t[140.211.166.138])\n\tby ash.osuosl.org (Postfix) with ESMTP id A838F1C21C0\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 27 Apr 2015 18:54:54 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id A36CA8B8E6\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 27 Apr 2015 18:54:54 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id voFmx+40ebdw for <intel-wired-lan@lists.osuosl.org>;\n\tMon, 27 Apr 2015 18:54:53 +0000 (UTC)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 7088A8B8CC\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 27 Apr 2015 18:54:53 +0000 (UTC)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby fmsmga102.fm.intel.com with ESMTP; 27 Apr 2015 11:54:53 -0700", "from catheri1-tigger.jf.intel.com ([134.134.176.92])\n\tby FMSMGA003.fm.intel.com with ESMTP; 27 Apr 2015 11:54:52 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.11,658,1422950400\"; d=\"scan'208\";a=\"486315527\"", "From": "Catherine Sullivan <catherine.sullivan@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Mon, 27 Apr 2015 14:57:18 -0400", "Message-Id": "<1430161042-28494-12-git-send-email-catherine.sullivan@intel.com>", "X-Mailer": "git-send-email 1.9.3", "In-Reply-To": "<1430161042-28494-1-git-send-email-catherine.sullivan@intel.com>", "References": "<1430161042-28494-1-git-send-email-catherine.sullivan@intel.com>", "Cc": "Anjali Singhai Jain <anjali.singhai@intel.com>,\n\tAkeem G Abodunrin <akeem.g.abodunrin@intel.com>", "Subject": "[Intel-wired-lan] [net-next S5 11/15] i40e/i40evf: Fix and refactor\n\tdynamic ITR code", "X-BeenThere": "intel-wired-lan@lists.osuosl.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.lists.osuosl.org>", "List-Unsubscribe": "<http://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@lists.osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@lists.osuosl.org?subject=help>", "List-Subscribe": "<http://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@lists.osuosl.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@lists.osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@lists.osuosl.org>" }, "content": "From: Carolyn Wyborny <carolyn.wyborny@intel.com>\n\nThis patch changes the switch statement for dynamic interrupt throttling\nand adds a default case. With this patch, we check the latency setting\ninstead of the current ITR settings and the included refactor improves\nperformance.\n\nWithout this patch, the ITR setting would never change dynamically, and\nthere was no default.\n\nSigned-off-by: Carolyn Wyborny <carolyn.wyborny@intel.com>\nSigned-off-by: Anjali Singhai Jain <anjali.singhai@intel.com>\nSigned-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>\nSigned-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>\nChange-ID: Idb5a8a14c7109ec47c90f6e94bd43baa17d7ee37\n---\n drivers/net/ethernet/intel/i40e/i40e_txrx.c | 146 ++++++++++++++++----------\n drivers/net/ethernet/intel/i40evf/i40e_txrx.c | 113 +++++++++++++-------\n 2 files changed, 161 insertions(+), 98 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c\nindex 74022ac..44aa93e 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c\n@@ -892,7 +892,7 @@ static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)\n \t * 20-1249MB/s bulk (8000 ints/s)\n \t */\n \tbytes_per_int = rc->total_bytes / rc->itr;\n-\tswitch (rc->itr) {\n+\tswitch (new_latency_range) {\n \tcase I40E_LOWEST_LATENCY:\n \t\tif (bytes_per_int > 10)\n \t\t\tnew_latency_range = I40E_LOW_LATENCY;\n@@ -905,9 +905,14 @@ static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)\n \t\tbreak;\n \tcase I40E_BULK_LATENCY:\n \t\tif (bytes_per_int <= 20)\n-\t\t\trc->latency_range = I40E_LOW_LATENCY;\n+\t\t\tnew_latency_range = I40E_LOW_LATENCY;\n+\t\tbreak;\n+\tdefault:\n+\t\tif (bytes_per_int <= 20)\n+\t\t\tnew_latency_range = I40E_LOW_LATENCY;\n \t\tbreak;\n \t}\n+\trc->latency_range = new_latency_range;\n \n \tswitch (new_latency_range) {\n \tcase I40E_LOWEST_LATENCY:\n@@ -923,42 +928,14 @@ static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)\n \t\tbreak;\n \t}\n \n-\tif (new_itr != rc->itr) {\n-\t\t/* do an exponential smoothing */\n-\t\tnew_itr = (10 * new_itr * rc->itr) /\n-\t\t\t ((9 * new_itr) + rc->itr);\n-\t\trc->itr = new_itr & I40E_MAX_ITR;\n-\t}\n+\tif (new_itr != rc->itr)\n+\t\trc->itr = new_itr;\n \n \trc->total_bytes = 0;\n \trc->total_packets = 0;\n }\n \n /**\n- * i40e_update_dynamic_itr - Adjust ITR based on bytes per int\n- * @q_vector: the vector to adjust\n- **/\n-static void i40e_update_dynamic_itr(struct i40e_q_vector *q_vector)\n-{\n-\tu16 vector = q_vector->vsi->base_vector + q_vector->v_idx;\n-\tstruct i40e_hw *hw = &q_vector->vsi->back->hw;\n-\tu32 reg_addr;\n-\tu16 old_itr;\n-\n-\treg_addr = I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1);\n-\told_itr = q_vector->rx.itr;\n-\ti40e_set_new_dynamic_itr(&q_vector->rx);\n-\tif (old_itr != q_vector->rx.itr)\n-\t\twr32(hw, reg_addr, q_vector->rx.itr);\n-\n-\treg_addr = I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1);\n-\told_itr = q_vector->tx.itr;\n-\ti40e_set_new_dynamic_itr(&q_vector->tx);\n-\tif (old_itr != q_vector->tx.itr)\n-\t\twr32(hw, reg_addr, q_vector->tx.itr);\n-}\n-\n-/**\n * i40e_clean_programming_status - clean the programming status descriptor\n * @rx_ring: the rx ring that has this descriptor\n * @rx_desc: the rx descriptor written back by HW\n@@ -1829,6 +1806,68 @@ static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)\n }\n \n /**\n+ * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt\n+ * @vsi: the VSI we care about\n+ * @q_vector: q_vector for which itr is being updated and interrupt enabled\n+ *\n+ **/\n+static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,\n+\t\t\t\t\t struct i40e_q_vector *q_vector)\n+{\n+\tstruct i40e_hw *hw = &vsi->back->hw;\n+\tu16 old_itr;\n+\tint vector;\n+\tu32 val;\n+\n+\tvector = (q_vector->v_idx + vsi->base_vector);\n+\tif (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {\n+\t\told_itr = q_vector->rx.itr;\n+\t\ti40e_set_new_dynamic_itr(&q_vector->rx);\n+\t\tif (old_itr != q_vector->rx.itr) {\n+\t\t\tval = I40E_PFINT_DYN_CTLN_INTENA_MASK |\n+\t\t\tI40E_PFINT_DYN_CTLN_CLEARPBA_MASK |\n+\t\t\t(I40E_RX_ITR <<\n+\t\t\t\tI40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |\n+\t\t\t(q_vector->rx.itr <<\n+\t\t\t\tI40E_PFINT_DYN_CTLN_INTERVAL_SHIFT);\n+\t\t} else {\n+\t\t\tval = I40E_PFINT_DYN_CTLN_INTENA_MASK |\n+\t\t\tI40E_PFINT_DYN_CTLN_CLEARPBA_MASK |\n+\t\t\t(I40E_ITR_NONE <<\n+\t\t\t\tI40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);\n+\t\t}\n+\t\tif (!test_bit(__I40E_DOWN, &vsi->state))\n+\t\t\twr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);\n+\t} else {\n+\t\ti40e_irq_dynamic_enable(vsi,\n+\t\t\t\t\tq_vector->v_idx + vsi->base_vector);\n+\t}\n+\tif (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {\n+\t\told_itr = q_vector->tx.itr;\n+\t\ti40e_set_new_dynamic_itr(&q_vector->tx);\n+\t\tif (old_itr != q_vector->tx.itr) {\n+\t\t\tval = I40E_PFINT_DYN_CTLN_INTENA_MASK |\n+\t\t\t\tI40E_PFINT_DYN_CTLN_CLEARPBA_MASK |\n+\t\t\t\t(I40E_TX_ITR <<\n+\t\t\t\t I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |\n+\t\t\t\t(q_vector->tx.itr <<\n+\t\t\t\t I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT);\n+\t\t} else {\n+\t\t\tval = I40E_PFINT_DYN_CTLN_INTENA_MASK |\n+\t\t\t\tI40E_PFINT_DYN_CTLN_CLEARPBA_MASK |\n+\t\t\t\t(I40E_ITR_NONE <<\n+\t\t\t\t I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);\n+\t\t}\n+\t\tif (!test_bit(__I40E_DOWN, &vsi->state))\n+\t\t\twr32(hw, I40E_PFINT_DYN_CTLN(q_vector->v_idx +\n+\t\t\t vsi->base_vector - 1), val);\n+\t} else {\n+\t\ti40e_irq_dynamic_enable(vsi,\n+\t\t\t\t\tq_vector->v_idx + vsi->base_vector);\n+\t}\n+}\n+\n+/**\n * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine\n * @napi: napi struct with our devices info in it\n * @budget: amount of work driver is allowed to do this pass, in packets\n@@ -1884,33 +1923,24 @@ int i40e_napi_poll(struct napi_struct *napi, int budget)\n \n \t/* Work is done so exit the polling mode and re-enable the interrupt */\n \tnapi_complete(napi);\n-\tif (ITR_IS_DYNAMIC(vsi->rx_itr_setting) ||\n-\t ITR_IS_DYNAMIC(vsi->tx_itr_setting))\n-\t\ti40e_update_dynamic_itr(q_vector);\n-\n-\tif (!test_bit(__I40E_DOWN, &vsi->state)) {\n-\t\tif (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {\n-\t\t\ti40e_irq_dynamic_enable(vsi,\n-\t\t\t\t\tq_vector->v_idx + vsi->base_vector);\n-\t\t} else {\n-\t\t\tstruct i40e_hw *hw = &vsi->back->hw;\n-\t\t\t/* We re-enable the queue 0 cause, but\n-\t\t\t * don't worry about dynamic_enable\n-\t\t\t * because we left it on for the other\n-\t\t\t * possible interrupts during napi\n-\t\t\t */\n-\t\t\tu32 qval = rd32(hw, I40E_QINT_RQCTL(0));\n-\t\t\tqval |= I40E_QINT_RQCTL_CAUSE_ENA_MASK;\n-\t\t\twr32(hw, I40E_QINT_RQCTL(0), qval);\n-\n-\t\t\tqval = rd32(hw, I40E_QINT_TQCTL(0));\n-\t\t\tqval |= I40E_QINT_TQCTL_CAUSE_ENA_MASK;\n-\t\t\twr32(hw, I40E_QINT_TQCTL(0), qval);\n-\n-\t\t\ti40e_irq_dynamic_enable_icr0(vsi->back);\n-\t\t}\n+\tif (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {\n+\t\ti40e_update_enable_itr(vsi, q_vector);\n+\t} else { /* Legacy mode */\n+\t\tstruct i40e_hw *hw = &vsi->back->hw;\n+\t\t/* We re-enable the queue 0 cause, but\n+\t\t * don't worry about dynamic_enable\n+\t\t * because we left it on for the other\n+\t\t * possible interrupts during napi\n+\t\t */\n+\t\tu32 qval = rd32(hw, I40E_QINT_RQCTL(0)) |\n+\t\t\t I40E_QINT_RQCTL_CAUSE_ENA_MASK;\n+\n+\t\twr32(hw, I40E_QINT_RQCTL(0), qval);\n+\t\tqval = rd32(hw, I40E_QINT_TQCTL(0)) |\n+\t\t I40E_QINT_TQCTL_CAUSE_ENA_MASK;\n+\t\twr32(hw, I40E_QINT_TQCTL(0), qval);\n+\t\ti40e_irq_dynamic_enable_icr0(vsi->back);\n \t}\n-\n \treturn 0;\n }\n \ndiff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\nindex e629762..cce2e23 100644\n--- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\n+++ b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c\n@@ -404,7 +404,7 @@ static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)\n \t * 20-1249MB/s bulk (8000 ints/s)\n \t */\n \tbytes_per_int = rc->total_bytes / rc->itr;\n-\tswitch (rc->itr) {\n+\tswitch (new_latency_range) {\n \tcase I40E_LOWEST_LATENCY:\n \t\tif (bytes_per_int > 10)\n \t\t\tnew_latency_range = I40E_LOW_LATENCY;\n@@ -417,9 +417,14 @@ static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)\n \t\tbreak;\n \tcase I40E_BULK_LATENCY:\n \t\tif (bytes_per_int <= 20)\n-\t\t\trc->latency_range = I40E_LOW_LATENCY;\n+\t\t\tnew_latency_range = I40E_LOW_LATENCY;\n+\t\tbreak;\n+\tdefault:\n+\t\tif (bytes_per_int <= 20)\n+\t\t\tnew_latency_range = I40E_LOW_LATENCY;\n \t\tbreak;\n \t}\n+\trc->latency_range = new_latency_range;\n \n \tswitch (new_latency_range) {\n \tcase I40E_LOWEST_LATENCY:\n@@ -435,42 +440,14 @@ static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)\n \t\tbreak;\n \t}\n \n-\tif (new_itr != rc->itr) {\n-\t\t/* do an exponential smoothing */\n-\t\tnew_itr = (10 * new_itr * rc->itr) /\n-\t\t\t ((9 * new_itr) + rc->itr);\n-\t\trc->itr = new_itr & I40E_MAX_ITR;\n-\t}\n+\tif (new_itr != rc->itr)\n+\t\trc->itr = new_itr;\n \n \trc->total_bytes = 0;\n \trc->total_packets = 0;\n }\n \n-/**\n- * i40e_update_dynamic_itr - Adjust ITR based on bytes per int\n- * @q_vector: the vector to adjust\n- **/\n-static void i40e_update_dynamic_itr(struct i40e_q_vector *q_vector)\n-{\n-\tu16 vector = q_vector->vsi->base_vector + q_vector->v_idx;\n-\tstruct i40e_hw *hw = &q_vector->vsi->back->hw;\n-\tu32 reg_addr;\n-\tu16 old_itr;\n-\n-\treg_addr = I40E_VFINT_ITRN1(I40E_RX_ITR, vector - 1);\n-\told_itr = q_vector->rx.itr;\n-\ti40e_set_new_dynamic_itr(&q_vector->rx);\n-\tif (old_itr != q_vector->rx.itr)\n-\t\twr32(hw, reg_addr, q_vector->rx.itr);\n-\n-\treg_addr = I40E_VFINT_ITRN1(I40E_TX_ITR, vector - 1);\n-\told_itr = q_vector->tx.itr;\n-\ti40e_set_new_dynamic_itr(&q_vector->tx);\n-\tif (old_itr != q_vector->tx.itr)\n-\t\twr32(hw, reg_addr, q_vector->tx.itr);\n-}\n-\n-/**\n+/*\n * i40evf_setup_tx_descriptors - Allocate the Tx descriptors\n * @tx_ring: the tx ring to set up\n *\n@@ -1279,6 +1256,68 @@ static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)\n }\n \n /**\n+ * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt\n+ * @vsi: the VSI we care about\n+ * @q_vector: q_vector for which itr is being updated and interrupt enabled\n+ *\n+ **/\n+static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,\n+\t\t\t\t\t struct i40e_q_vector *q_vector)\n+{\n+\tstruct i40e_hw *hw = &vsi->back->hw;\n+\tu16 old_itr;\n+\tint vector;\n+\tu32 val;\n+\n+\tvector = (q_vector->v_idx + vsi->base_vector);\n+\tif (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {\n+\t\told_itr = q_vector->rx.itr;\n+\t\ti40e_set_new_dynamic_itr(&q_vector->rx);\n+\t\tif (old_itr != q_vector->rx.itr) {\n+\t\t\tval = I40E_VFINT_DYN_CTLN_INTENA_MASK |\n+\t\t\tI40E_VFINT_DYN_CTLN_CLEARPBA_MASK |\n+\t\t\t(I40E_RX_ITR <<\n+\t\t\t\tI40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT) |\n+\t\t\t(q_vector->rx.itr <<\n+\t\t\t\tI40E_VFINT_DYN_CTLN_INTERVAL_SHIFT);\n+\t\t} else {\n+\t\t\tval = I40E_VFINT_DYN_CTLN_INTENA_MASK |\n+\t\t\tI40E_VFINT_DYN_CTLN_CLEARPBA_MASK |\n+\t\t\t(I40E_ITR_NONE <<\n+\t\t\t\tI40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT);\n+\t\t}\n+\t\tif (!test_bit(__I40E_DOWN, &vsi->state))\n+\t\t\twr32(hw, I40E_VFINT_DYN_CTLN(vector - 1), val);\n+\t} else {\n+\t\ti40evf_irq_enable_queues(vsi->back, 1\n+\t\t\t<< q_vector->v_idx);\n+\t}\n+\tif (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {\n+\t\told_itr = q_vector->tx.itr;\n+\t\ti40e_set_new_dynamic_itr(&q_vector->tx);\n+\t\tif (old_itr != q_vector->tx.itr) {\n+\t\t\tval = I40E_VFINT_DYN_CTLN_INTENA_MASK |\n+\t\t\t\tI40E_VFINT_DYN_CTLN_CLEARPBA_MASK |\n+\t\t\t\t(I40E_TX_ITR <<\n+\t\t\t\t I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT) |\n+\t\t\t\t(q_vector->tx.itr <<\n+\t\t\t\t I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT);\n+\n+\t\t} else {\n+\t\t\tval = I40E_VFINT_DYN_CTLN_INTENA_MASK |\n+\t\t\t\tI40E_VFINT_DYN_CTLN_CLEARPBA_MASK |\n+\t\t\t\t(I40E_ITR_NONE <<\n+\t\t\t\t I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT);\n+\t\t}\n+\t\tif (!test_bit(__I40E_DOWN, &vsi->state))\n+\t\t\twr32(hw, I40E_VFINT_DYN_CTLN(vector - 1), val);\n+\t} else {\n+\t\ti40evf_irq_enable_queues(vsi->back,\n+\t\t\t\t\t 1 << q_vector->v_idx);\n+\t}\n+}\n+\n+/**\n * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine\n * @napi: napi struct with our devices info in it\n * @budget: amount of work driver is allowed to do this pass, in packets\n@@ -1334,13 +1373,7 @@ int i40evf_napi_poll(struct napi_struct *napi, int budget)\n \n \t/* Work is done so exit the polling mode and re-enable the interrupt */\n \tnapi_complete(napi);\n-\tif (ITR_IS_DYNAMIC(vsi->rx_itr_setting) ||\n-\t ITR_IS_DYNAMIC(vsi->tx_itr_setting))\n-\t\ti40e_update_dynamic_itr(q_vector);\n-\n-\tif (!test_bit(__I40E_DOWN, &vsi->state))\n-\t\ti40evf_irq_enable_queues(vsi->back, 1 << q_vector->v_idx);\n-\n+\ti40e_update_enable_itr(vsi, q_vector);\n \treturn 0;\n }\n \n", "prefixes": [ "net-next", "S5", "11/15" ] }