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GET /api/patches/457778/?format=api
{ "id": 457778, "url": "http://patchwork.ozlabs.org/api/patches/457778/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-i2c/patch/1428004866-13543-1-git-send-email-kdasu.kdev@gmail.com/", "project": { "id": 35, "url": "http://patchwork.ozlabs.org/api/projects/35/?format=api", "name": "Linux I2C development", "link_name": "linux-i2c", "list_id": "linux-i2c.vger.kernel.org", "list_email": "linux-i2c@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1428004866-13543-1-git-send-email-kdasu.kdev@gmail.com>", "list_archive_url": null, "date": "2015-04-02T20:01:05", "name": "[V2,1/2] i2c: brcmstb: Add Broadcom settop SoC i2c controller driver", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "7bdb56f563eda0e4732b8da96e3fd755a290ad3f", "submitter": { "id": 63968, "url": "http://patchwork.ozlabs.org/api/people/63968/?format=api", "name": "Kamal Dasu", "email": "kdasu.kdev@gmail.com" }, "delegate": { "id": 9049, "url": "http://patchwork.ozlabs.org/api/users/9049/?format=api", "username": "wsa", "first_name": "Wolfram", "last_name": "Sang", "email": "wolfram@the-dreams.de" }, "mbox": "http://patchwork.ozlabs.org/project/linux-i2c/patch/1428004866-13543-1-git-send-email-kdasu.kdev@gmail.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/457778/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/457778/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-i2c-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id D822814009B\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 3 Apr 2015 07:01:16 +1100 (AEDT)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1750797AbbDBUBP (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tThu, 2 Apr 2015 16:01:15 -0400", "from mail-gw3-out.broadcom.com ([216.31.210.64]:56783 \"EHLO\n\tmail-gw3-out.broadcom.com\" rhost-flags-OK-OK-OK-OK) by\n\tvger.kernel.org with ESMTP id S1751118AbbDBUBO (ORCPT\n\t<rfc822;linux-i2c@vger.kernel.org>); Thu, 2 Apr 2015 16:01:14 -0400", "from irvexchcas06.broadcom.com (HELO\n\tIRVEXCHCAS06.corp.ad.broadcom.com) ([10.9.208.53])\n\tby mail-gw3-out.broadcom.com with ESMTP; 02 Apr 2015 13:05:11 -0700", "from IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) by\n\tIRVEXCHCAS06.corp.ad.broadcom.com (10.9.208.53) with Microsoft SMTP\n\tServer (TLS) id 14.3.174.1; Thu, 2 Apr 2015 13:01:13 -0700", "from mail-irva-13.broadcom.com (10.10.10.20) by\n\tIRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) with Microsoft SMTP\n\tServer id 14.3.174.1; Thu, 2 Apr 2015 13:01:13 -0700", "from kdasu-ltmht-linux.and.broadcom.com (unknown [10.28.65.84])\tby\n\tmail-irva-13.broadcom.com (Postfix) with ESMTP id C7C6340FEA;\n\tThu, 2 Apr 2015 12:59:48 -0700 (PDT)" ], "X-IronPort-AV": "E=Sophos;i=\"5.11,512,1422950400\"; d=\"scan'208\";a=\"60961871\"", "From": "Kamal Dasu <kdasu.kdev@gmail.com>", "To": "<linux-i2c@vger.kernel.org>", "CC": "<wsa@the-dreams.de>, <f.fainelli@gmail.com>,\n\t<gregory.0xf0@gmail.com>, Kamal Dasu <kdasu.kdev@gmail.com>", "Subject": "[V2 1/2] i2c: brcmstb: Add Broadcom settop SoC i2c controller driver", "Date": "Thu, 2 Apr 2015 16:01:05 -0400", "Message-ID": "<1428004866-13543-1-git-send-email-kdasu.kdev@gmail.com>", "X-Mailer": "git-send-email 2.3.2", "MIME-Version": "1.0", "Content-Type": "text/plain", "Sender": "linux-i2c-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-i2c.vger.kernel.org>", "X-Mailing-List": "linux-i2c@vger.kernel.org" }, "content": "Adding support for i2c controller driver for Broadcom settop\nSoCs.\n\nSigned-off-by: Kamal Dasu <kdasu.kdev@gmail.com>\n---\nV2 changes\n - Separate commits for device tree bindings and\n initial i2c-brcmstb driver code\n---\n drivers/i2c/busses/Kconfig | 10 +\n drivers/i2c/busses/Makefile | 1 +\n drivers/i2c/busses/i2c-brcmstb.c | 703 +++++++++++++++++++++++++++++++++++++++\n 3 files changed, 714 insertions(+)\n create mode 100644 drivers/i2c/busses/i2c-brcmstb.c", "diff": "diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig\nindex 22da9c2..e3938f4 100644\n--- a/drivers/i2c/busses/Kconfig\n+++ b/drivers/i2c/busses/Kconfig\n@@ -392,6 +392,16 @@ config I2C_BCM_KONA\n \n \t If you do not need KONA I2C interface, say N.\n \n+config I2C_BRCMSTB\n+\ttristate \"BRCM Settop I2C adapter\"\n+\tdepends on ARCH_BRCMSTB\n+\tdefault y\n+\thelp\n+\t If you say yes to this option, support will be included for the\n+\t I2C interface on the Broadcom Settop SoCs.\n+\n+\t If you do not need I2C interface, say N.\n+\n config I2C_BLACKFIN_TWI\n \ttristate \"Blackfin TWI I2C support\"\n \tdepends on BLACKFIN\ndiff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile\nindex 3638feb..91a0b5f 100644\n--- a/drivers/i2c/busses/Makefile\n+++ b/drivers/i2c/busses/Makefile\n@@ -102,6 +102,7 @@ obj-$(CONFIG_I2C_VIPERBOARD)\t+= i2c-viperboard.o\n # Other I2C/SMBus bus drivers\n obj-$(CONFIG_I2C_ACORN)\t\t+= i2c-acorn.o\n obj-$(CONFIG_I2C_BCM_KONA)\t+= i2c-bcm-kona.o\n+obj-$(CONFIG_I2C_BRCMSTB)\t+= i2c-brcmstb.o\n obj-$(CONFIG_I2C_CROS_EC_TUNNEL)\t+= i2c-cros-ec-tunnel.o\n obj-$(CONFIG_I2C_ELEKTOR)\t+= i2c-elektor.o\n obj-$(CONFIG_I2C_OPAL)\t\t+= i2c-opal.o\ndiff --git a/drivers/i2c/busses/i2c-brcmstb.c b/drivers/i2c/busses/i2c-brcmstb.c\nnew file mode 100644\nindex 0000000..b69ab14\n--- /dev/null\n+++ b/drivers/i2c/busses/i2c-brcmstb.c\n@@ -0,0 +1,703 @@\n+/*\n+ * Copyright (C) 2014 Broadcom Corporation\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License as\n+ * published by the Free Software Foundation version 2.\n+ *\n+ * This program is distributed \"as is\" WITHOUT ANY WARRANTY of any\n+ * kind, whether express or implied; without even the implied warranty\n+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ */\n+\n+#include <linux/device.h>\n+#include <linux/kernel.h>\n+#include <linux/module.h>\n+#include <linux/sched.h>\n+#include <linux/i2c.h>\n+#include <linux/interrupt.h>\n+#include <linux/platform_device.h>\n+#include <linux/clk.h>\n+#include <linux/io.h>\n+#include <linux/clk.h>\n+#include <linux/slab.h>\n+#include <linux/version.h>\n+#include <linux/delay.h>\n+\n+#define N_DATA_REGS\t\t\t\t\t8\n+#define N_DATA_BYTES\t\t\t\t\t(N_DATA_REGS * 4)\n+\n+/* BSC count register field definitions */\n+#define BSC_CNT_REG1_MASK\t\t\t\t0x0000003f\n+#define BSC_CNT_REG1_SHIFT\t\t\t\t0\n+#define BSC_CNT_REG2_MASK\t\t\t\t0x00000fc0\n+#define BSC_CNT_REG2_SHIFT\t\t\t\t6\n+\n+/* BSC CTL register field definitions */\n+#define BSC_CTL_REG_DTF_MASK\t\t\t\t0x00000003\n+#define BSC_CTL_REG_SCL_SEL_MASK\t\t\t0x00000030\n+#define BSC_CTL_REG_SCL_SEL_SHIFT\t\t\t4\n+#define BSC_CTL_REG_INT_EN_MASK\t\t\t\t0x00000040\n+#define BSC_CTL_REG_INT_EN_SHIFT\t\t\t6\n+#define BSC_CTL_REG_DIV_CLK_MASK\t\t\t0x00000080\n+\n+/* BSC_IIC_ENABLE r/w enable and interrupt field defintions */\n+#define BSC_IIC_EN_RESTART_MASK\t\t\t\t0x00000040\n+#define BSC_IIC_EN_NOSTART_MASK\t\t\t\t0x00000020\n+#define BSC_IIC_EN_NOSTOP_MASK\t\t\t\t0x00000010\n+#define BSC_IIC_EN_NOACK_MASK\t\t\t\t0x00000004\n+#define BSC_IIC_EN_INTRP_MASK\t\t\t\t0x00000002\n+#define BSC_IIC_EN_ENABLE_MASK\t\t\t\t0x00000001\n+\n+/* BSC_CTLHI control register field definitions */\n+#define BSC_CTLHI_REG_INPUT_SWITCHING_LEVEL_MASK\t0x00000080\n+#define BSC_CTLHI_REG_DATAREG_SIZE_MASK\t\t\t0x00000040\n+#define BSC_CTLHI_REG_IGNORE_ACK_MASK\t\t\t0x00000002\n+#define BSC_CTLHI_REG_WAIT_DIS_MASK\t\t\t0x00000001\n+\n+#define I2C_TIMEOUT\t\t\t\t\t100 /* msecs */\n+\n+/* Condition mask used for non combined transfer */\n+#define COND_RESTART\t\tBSC_IIC_EN_RESTART_MASK\n+#define COND_NOSTART\t\tBSC_IIC_EN_NOSTART_MASK\n+#define\tCOND_NOSTOP\t\tBSC_IIC_EN_NOSTOP_MASK\n+#define COND_START_STOP\t\t(COND_RESTART | COND_NOSTART | COND_NOSTOP)\n+\n+/* BSC data transfer direction */\n+#define DTF_WR_MASK\t\t0x00000000\n+#define DTF_RD_MASK\t\t0x00000001\n+/* BSC data transfer direction combined format */\n+#define DTF_RD_WR_MASK\t\t0x00000002\n+#define DTF_WR_RD_MASK\t\t0x00000003\n+/* default bus speed */\n+#define DEFAULT_BUS_SPEEDHZ 375000\n+\n+struct bsc_regs {\n+\tu32\tchip_address;\n+\tu32\tdata_in[N_DATA_REGS];\n+\tu32\tcnt_reg;\n+\tu32\tctl_reg;\n+\tu32\tiic_enable;\n+\tu32\tdata_out[N_DATA_REGS];\n+\tu32\tctlhi_reg;\n+\tu32\tscl_param;\n+};\n+\n+struct bsc_clk_param {\n+\tu32 hz;\n+\tu32 scl_mask;\n+\tu32 div_mask;\n+};\n+\n+enum bsc_xfer_cmd {\n+\tCMD_WR,\n+\tCMD_RD,\n+\tCMD_WR_NOACK,\n+\tCMD_RD_NOACK,\n+};\n+\n+static char const *cmd_string[] = {\n+\t[CMD_WR] = \"WR\",\n+\t[CMD_RD] = \"RD\",\n+\t[CMD_WR_NOACK] = \"WR NOACK\",\n+\t[CMD_RD_NOACK] = \"RD NOACK\",\n+};\n+\n+enum bus_speeds {\n+\tSPD_375K,\n+\tSPD_390K,\n+\tSPD_187K,\n+\tSPD_200K,\n+\tSPD_93K,\n+\tSPD_97K,\n+\tSPD_46K,\n+\tSPD_50K\n+};\n+\n+static const struct bsc_clk_param bsc_clk[] = {\n+\t[SPD_375K] = {\n+\t\t.hz = 375000,\n+\t\t.scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,\n+\t\t.div_mask = 0\n+\t},\n+\t[SPD_390K] = {\n+\t\t.hz = 390000,\n+\t\t.scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,\n+\t\t.div_mask = 0\n+\t},\n+\t[SPD_187K] = {\n+\t\t.hz = 187500,\n+\t\t.scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,\n+\t\t.div_mask = 0\n+\t},\n+\t[SPD_200K] = {\n+\t\t.hz = 200000,\n+\t\t.scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,\n+\t\t.div_mask = 0\n+\t},\n+\t[SPD_93K] = {\n+\t\t.hz = 93750,\n+\t\t.scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT,\n+\t\t.div_mask = BSC_CTL_REG_DIV_CLK_MASK\n+\t},\n+\t[SPD_97K] = {\n+\t\t.hz = 97500,\n+\t\t.scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT,\n+\t\t.div_mask = BSC_CTL_REG_DIV_CLK_MASK\n+\t},\n+\t[SPD_46K] = {\n+\t\t.hz = 46875,\n+\t\t.scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT,\n+\t\t.div_mask = BSC_CTL_REG_DIV_CLK_MASK\n+\t},\n+\t[SPD_50K] = {\n+\t\t.hz = 50000,\n+\t\t.scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT,\n+\t\t.div_mask = BSC_CTL_REG_DIV_CLK_MASK\n+\t}\n+};\n+\n+struct brcmstb_i2c_dev {\n+\tstruct device *device;\n+\tvoid __iomem *base;\n+\tvoid __iomem *irq_base;\n+\tint irq;\n+\tstruct bsc_regs *bsc_regmap;\n+\tstruct i2c_adapter adapter;\n+\tstruct completion done;\n+\tbool is_suspended;\n+\tu32 clk_freq_hz;\n+};\n+\n+#define bsc_readl(_dev, reg)\t\t\t\t\t\t\\\n+\t__bsc_readl(_dev, offsetof(struct bsc_regs, reg))\n+\n+#define bsc_writel(_dev, val, reg)\t\t\t\t\t\\\n+\t__bsc_writel(_dev, val, offsetof(struct bsc_regs, reg))\n+\n+static inline u32 __bsc_readl(struct brcmstb_i2c_dev *dev, u32 reg)\n+{\n+\treturn __raw_readl(dev->base + reg);\n+}\n+\n+static inline void __bsc_writel(struct brcmstb_i2c_dev *dev, u32 val,\n+\t\t\t\t u32 reg)\n+{\n+\t__raw_writel(val, dev->base + reg);\n+}\n+\n+static void brcmstb_i2c_disable_irq(struct brcmstb_i2c_dev *dev)\n+{\n+\t/* Disable BSC CTL interrupt line */\n+\tdev->bsc_regmap->ctl_reg &= ~BSC_CTL_REG_INT_EN_MASK;\n+\tbarrier();\n+\tbsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);\n+}\n+\n+static void brcmstb_i2c_enable_irq(struct brcmstb_i2c_dev *dev)\n+{\n+\t/* Enable BSC CTL interrupt line */\n+\tdev->bsc_regmap->ctl_reg |= BSC_CTL_REG_INT_EN_MASK;\n+\tbarrier();\n+\tbsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);\n+}\n+\n+static irqreturn_t brcmstb_i2c_isr(int irq, void *devid)\n+{\n+\tstruct brcmstb_i2c_dev *dev = devid;\n+\tu32 status_bsc_ctl = bsc_readl(dev, ctl_reg);\n+\tu32 status_iic_intrp = bsc_readl(dev, iic_enable);\n+\n+\tdev_dbg(dev->device, \"isr CTL_REG %x IIC_EN %x\\n\",\n+\t\tstatus_bsc_ctl, status_iic_intrp);\n+\n+\tif (!(status_bsc_ctl & BSC_CTL_REG_INT_EN_MASK))\n+\t\treturn IRQ_NONE;\n+\n+\tbrcmstb_i2c_disable_irq(dev);\n+\tcomplete_all(&dev->done);\n+\n+\tdev_dbg(dev->device, \"isr handled\");\n+\treturn IRQ_HANDLED;\n+}\n+\n+/* Wait for device to be ready */\n+static int brcmstb_i2c_wait_if_busy(struct brcmstb_i2c_dev *dev)\n+{\n+\tunsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT);\n+\n+\twhile ((bsc_readl(dev, iic_enable) & BSC_IIC_EN_INTRP_MASK)) {\n+\t\tif (time_after(jiffies, timeout)) {\n+\t\t\tdev_err(dev->device, \"i2c device busy timeout\\n\");\n+\t\t\treturn -ETIMEDOUT;\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+\n+/* i2c xfer completion function, handles both irq and polling mode\n+ */\n+static int brcmstb_i2c_waitforcompletion(struct brcmstb_i2c_dev *dev)\n+{\n+\tint ret = 0;\n+\tunsigned long timeout = msecs_to_jiffies(I2C_TIMEOUT);\n+\n+\tif (dev->irq >= 0) {\n+\t\tif (!wait_for_completion_timeout(&dev->done, timeout))\n+\t\t\tret = -ETIMEDOUT;\n+\t} else {\n+\t\t/* we are in polling mode */\n+\t\tu32 bsc_intrp;\n+\t\tunsigned long time_left = jiffies + timeout;\n+\n+\t\tdo {\n+\t\t\tbsc_intrp = bsc_readl(dev, iic_enable) &\n+\t\t\t\tBSC_IIC_EN_INTRP_MASK;\n+\t\t\tif (time_after(jiffies, time_left)) {\n+\t\t\t\tret = -ETIMEDOUT;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tudelay(100);\n+\t\t} while (!bsc_intrp);\n+\t\tbrcmstb_i2c_disable_irq(dev);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+/* Set xfer START/STOP conditions for subsequent transfer */\n+static void brcmstb_set_i2c_start_stop(struct brcmstb_i2c_dev *dev,\n+\t\t\t\t u32 cond_flag)\n+{\n+\tu32 regval = dev->bsc_regmap->iic_enable;\n+\n+\tdev->bsc_regmap->iic_enable = (regval & ~COND_START_STOP) | cond_flag;\n+}\n+\n+/* Send I2C request */\n+static int brcmstb_send_i2c_cmd(struct brcmstb_i2c_dev *dev,\n+\t\t\t\tenum bsc_xfer_cmd cmd)\n+{\n+\tint rc = 0, ignore_ack = 0;\n+\tstruct bsc_regs *pi2creg = dev->bsc_regmap;\n+\tu32 ctl_reg;\n+\n+\t/* Make sure the hardware is ready */\n+\trc = brcmstb_i2c_wait_if_busy(dev);\n+\tif (rc < 0)\n+\t\treturn rc;\n+\n+\tdev_dbg(dev->device, \"%s, %d\\n\", __func__, cmd);\n+\n+\t/* see if the transaction needs check NACK conditions */\n+\tignore_ack = (cmd == CMD_WR || cmd == CMD_RD) ? 0 : 1;\n+\tif (ignore_ack)\n+\t\tpi2creg->ctlhi_reg |= BSC_CTLHI_REG_IGNORE_ACK_MASK;\n+\telse\n+\t\tpi2creg->ctlhi_reg &= ~BSC_CTLHI_REG_IGNORE_ACK_MASK;\n+\tbsc_writel(dev, pi2creg->ctlhi_reg, ctlhi_reg);\n+\n+\tif (dev->irq >= 0)\n+\t\treinit_completion(&dev->done);\n+\n+\t/* set data transfer direction */\n+\tctl_reg = pi2creg->ctl_reg & ~BSC_CTL_REG_DTF_MASK;\n+\tif (cmd == CMD_WR || cmd == CMD_WR_NOACK)\n+\t\tpi2creg->ctl_reg = ctl_reg | DTF_WR_MASK;\n+\telse\n+\t\tpi2creg->ctl_reg = ctl_reg | DTF_RD_MASK;\n+\n+\t/* enable BSC CTL interrupt line */\n+\tbrcmstb_i2c_enable_irq(dev);\n+\n+\t/* initiate transfer by setting iic_enable */\n+\tpi2creg->iic_enable |= BSC_IIC_EN_ENABLE_MASK;\n+\tbsc_writel(dev, pi2creg->iic_enable, iic_enable);\n+\n+\t/* Wait for transaction to finish or timeout */\n+\trc = brcmstb_i2c_waitforcompletion(dev);\n+\tif (rc) {\n+\t\tdev_err(dev->device, \"intr timeout for cmd %s\\n\",\n+\t\t\tcmd_string[cmd]);\n+\t\tgoto cmd_out;\n+\t}\n+\n+\tif (!ignore_ack && bsc_readl(dev, iic_enable) & BSC_IIC_EN_NOACK_MASK) {\n+\t\trc = -EREMOTEIO;\n+\t\tdev_dbg(dev->device, \"controller received NOACK intr for %s\\n\",\n+\t\t\tcmd_string[cmd]);\n+\t}\n+\n+cmd_out:\n+\tbsc_writel(dev, 0, cnt_reg);\n+\tbsc_writel(dev, 0, iic_enable);\n+\n+\treturn rc;\n+}\n+\n+static int brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev *dev,\n+\t\t\t\t u8 *buf, unsigned int len,\n+\t\t\t\t enum bsc_xfer_cmd cmd)\n+{\n+\tint i, j, rc;\n+\n+\t/* set the read/write length */\n+\tbsc_writel(dev, BSC_CNT_REG1_MASK & (len << BSC_CNT_REG1_SHIFT),\n+\t\t cnt_reg);\n+\n+\t/* Write data into data_in register */\n+\tif (cmd == CMD_WR || cmd == CMD_WR_NOACK) {\n+\t\tfor (i = 0; i < len; i += 4) {\n+\t\t\tu32 word = 0;\n+\n+\t\t\tfor (j = 0; j < 4; j++) {\n+\t\t\t\tword >>= 8;\n+\t\t\t\tif ((i + j) < len)\n+\t\t\t\t\tword |= buf[i + j] << 24;\n+\t\t\t}\n+\t\t\tbsc_writel(dev, word, data_in[i >> 2]);\n+\t\t}\n+\t}\n+\n+\t/* Initiate xfer */\n+\trc = brcmstb_send_i2c_cmd(dev, cmd);\n+\n+\tif (rc != 0)\n+\t\treturn rc;\n+\n+\tif (cmd == CMD_RD || cmd == CMD_RD_NOACK) {\n+\t\tfor (i = 0; i < len; i += 4) {\n+\t\t\tu32 data = bsc_readl(dev, data_out[i >> 2]);\n+\n+\t\t\tfor (j = 0; j < 4 && (j + i) < len; j++) {\n+\t\t\t\tbuf[i + j] = data & 0xff;\n+\t\t\t\tdata >>= 8;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* Write a single byte of data to the i2c bus */\n+static int brcmstb_i2c_write_data_byte(struct brcmstb_i2c_dev *dev,\n+\t\t\t\t u8 *buf, unsigned int nak_expected)\n+{\n+\tenum bsc_xfer_cmd cmd = nak_expected ? CMD_WR : CMD_WR_NOACK;\n+\n+\tbsc_writel(dev, 1, cnt_reg);\n+\tbsc_writel(dev, *buf, data_in);\n+\n+\treturn brcmstb_send_i2c_cmd(dev, cmd);\n+}\n+\n+/* Send i2c address */\n+static int brcmstb_i2c_do_addr(struct brcmstb_i2c_dev *dev,\n+\t\t\t struct i2c_msg *msg)\n+{\n+\tunsigned char addr;\n+\n+\tif (msg->flags & I2C_M_TEN) {\n+\n+\t\t/* First byte is 11110XX0 where XX is upper 2 bits */\n+\t\taddr = 0xF0 | ((msg->addr & 0x300) >> 7);\n+\t\tbsc_writel(dev, addr, chip_address);\n+\n+\t\t/* Second byte is the remaining 8 bits */\n+\t\taddr = msg->addr & 0xFF;\n+\t\tif (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0)\n+\t\t\treturn -EREMOTEIO;\n+\n+\t\tif (msg->flags & I2C_M_RD) {\n+\t\t\t/* For read, send restart without stop condition */\n+\t\t\tbrcmstb_set_i2c_start_stop(dev, COND_RESTART\n+\t\t\t\t\t\t | COND_NOSTOP);\n+\t\t\t/* Then re-send the first byte with the read bit set */\n+\t\t\taddr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01;\n+\t\t\tif (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0)\n+\t\t\t\treturn -EREMOTEIO;\n+\n+\t\t}\n+\t} else {\n+\t\taddr = msg->addr << 1;\n+\t\tif (msg->flags & I2C_M_RD)\n+\t\t\taddr |= 1;\n+\n+\t\tbsc_writel(dev, addr, chip_address);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* Master transfer function */\n+static int brcmstb_i2c_xfer(struct i2c_adapter *adapter,\n+\t\t\t struct i2c_msg msgs[], int num)\n+{\n+\tstruct brcmstb_i2c_dev *dev = i2c_get_adapdata(adapter);\n+\tstruct i2c_msg *pmsg;\n+\tint rc = 0;\n+\tint i;\n+\tint bytes_to_xfer;\n+\tenum bsc_xfer_cmd cmd;\n+\tu8 *tmp_buf;\n+\tint len = 0;\n+\tint ignore_nack = 0;\n+\n+\tif (dev->is_suspended)\n+\t\treturn -EBUSY;\n+\n+\t/* Loop through all messages */\n+\tfor (i = 0; i < num; i++) {\n+\t\tpmsg = &msgs[i];\n+\t\tlen = pmsg->len;\n+\t\ttmp_buf = pmsg->buf;\n+\t\tignore_nack = pmsg->flags & I2C_M_IGNORE_NAK;\n+\n+\t\tdev_dbg(dev->device,\n+\t\t\t\"msg# %d/%d flg %x buf %x len %d\\n\", i,\n+\t\t\tnum - 1, pmsg->flags,\n+\t\t\tpmsg->buf ? pmsg->buf[0] : '0', pmsg->len);\n+\n+\t\tif (i < (num - 1) && (msgs[i + 1].flags & I2C_M_NOSTART))\n+\t\t\tbrcmstb_set_i2c_start_stop(dev, ~(COND_START_STOP));\n+\t\telse\n+\t\t\tbrcmstb_set_i2c_start_stop(dev,\n+\t\t\t\t\t\t COND_RESTART | COND_NOSTOP);\n+\n+\t\t/* Send slave address */\n+\t\tif (!(pmsg->flags & I2C_M_NOSTART)) {\n+\t\t\trc = brcmstb_i2c_do_addr(dev, pmsg);\n+\t\t\tif (rc < 0) {\n+\t\t\t\tdev_dbg(dev->device,\n+\t\t\t\t\t\"NACK for addr %2.2x msg#%d rc = %d\\n\",\n+\t\t\t\t\tpmsg->addr, i, rc);\n+\t\t\t\tgoto out;\n+\t\t\t}\n+\t\t}\n+\n+\t\tcmd = (pmsg->flags & I2C_M_RD) ? CMD_RD : CMD_WR;\n+\n+\t\t/* Perform data transfer */\n+\t\twhile (len) {\n+\t\t\tbytes_to_xfer = min(len, N_DATA_BYTES);\n+\n+\t\t\tif (ignore_nack || len <= N_DATA_BYTES)\n+\t\t\t\tcmd = (pmsg->flags & I2C_M_RD) ? CMD_RD_NOACK\n+\t\t\t\t\t: CMD_WR_NOACK;\n+\n+\t\t\tif (len <= N_DATA_BYTES && i == (num - 1))\n+\t\t\t\tbrcmstb_set_i2c_start_stop(dev,\n+\t\t\t\t\t\t\t ~(COND_START_STOP));\n+\n+\t\t\trc = brcmstb_i2c_xfer_bsc_data(dev, tmp_buf,\n+\t\t\t\t\t\t bytes_to_xfer, cmd);\n+\t\t\tif (rc < 0) {\n+\t\t\t\tdev_dbg(dev->device, \"%s failure\",\n+\t\t\t\t\tcmd_string[cmd]);\n+\t\t\t\tgoto out;\n+\t\t\t}\n+\n+\t\t\tlen -= bytes_to_xfer;\n+\t\t\ttmp_buf += bytes_to_xfer;\n+\t\t}\n+\t}\n+\n+\trc = num;\n+out:\n+\treturn rc;\n+\n+}\n+\n+static u32 brcmstb_i2c_functionality(struct i2c_adapter *adap)\n+{\n+\treturn I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR\n+\t\t| I2C_FUNC_NOSTART | I2C_FUNC_PROTOCOL_MANGLING;\n+}\n+\n+static const struct i2c_algorithm brcmstb_i2c_algo = {\n+\t.master_xfer = brcmstb_i2c_xfer,\n+\t.functionality = brcmstb_i2c_functionality,\n+};\n+\n+static void brcmstb_i2c_set_bus_speed(struct brcmstb_i2c_dev *dev)\n+{\n+\tint i = 0, num_speeds = ARRAY_SIZE(bsc_clk);\n+\tu32 clk_freq_hz = dev->clk_freq_hz;\n+\n+\tfor (i = 0; i < num_speeds; i++) {\n+\t\tif (bsc_clk[i].hz == clk_freq_hz) {\n+\t\t\tdev->bsc_regmap->ctl_reg &= ~(BSC_CTL_REG_SCL_SEL_MASK\n+\t\t\t\t\t\t| BSC_CTL_REG_DIV_CLK_MASK);\n+\t\t\tdev->bsc_regmap->ctl_reg |= (bsc_clk[i].scl_mask |\n+\t\t\t\t\t\t bsc_clk[i].div_mask);\n+\t\t\tbsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tif (i == num_speeds) {\n+\t\ti = (bsc_readl(dev, ctl_reg) & BSC_CTL_REG_SCL_SEL_MASK) >>\n+\t\t\tBSC_CTL_REG_SCL_SEL_SHIFT;\n+\t\tdev_warn(dev->device, \"invalid input clock-frequency %dHz\\n\",\n+\t\t\tclk_freq_hz);\n+\t\tdev_warn(dev->device, \"leaving current clock-frequency @ %dHz\\n\",\n+\t\t\tbsc_clk[i].hz);\n+\t}\n+}\n+\n+static void brcmstb_i2c_set_bsc_reg_defaults(struct brcmstb_i2c_dev *dev)\n+{\n+\t/* 4 byte data register */\n+\tdev->bsc_regmap->ctlhi_reg = BSC_CTLHI_REG_DATAREG_SIZE_MASK;\n+\tbsc_writel(dev, dev->bsc_regmap->ctlhi_reg, ctlhi_reg);\n+\t/* set bus speed */\n+\tbrcmstb_i2c_set_bus_speed(dev);\n+}\n+\n+static int brcmstb_i2c_probe(struct platform_device *pdev)\n+{\n+\tint rc = 0;\n+\tstruct brcmstb_i2c_dev *dev;\n+\tstruct i2c_adapter *adap;\n+\tstruct resource *iomem;\n+\tconst char *int_name;\n+\n+\t/* Allocate memory for private data structure */\n+\tdev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);\n+\tif (!dev)\n+\t\treturn -ENOMEM;\n+\n+\tdev->bsc_regmap = kzalloc(sizeof(struct bsc_regs), GFP_KERNEL);\n+\tif (!dev->bsc_regmap)\n+\t\treturn -ENOMEM;\n+\n+\tplatform_set_drvdata(pdev, dev);\n+\tdev->device = &pdev->dev;\n+\tinit_completion(&dev->done);\n+\n+\t/* Map hardware registers */\n+\tiomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tdev->base = devm_ioremap_resource(dev->device, iomem);\n+\tif (IS_ERR(dev->base)) {\n+\t\trc = -ENOMEM;\n+\t\tgoto probe_errorout;\n+\t}\n+\n+\trc = of_property_read_string(dev->device->of_node, \"interrupt-names\",\n+\t\t\t\t &int_name);\n+\tif (rc < 0)\n+\t\tint_name = NULL;\n+\n+\t/* Get the interrupt number */\n+\tdev->irq = platform_get_irq(pdev, 0);\n+\n+\t/* disable the bsc interrupt line */\n+\tbrcmstb_i2c_disable_irq(dev);\n+\n+\t/* register the ISR handler */\n+\trc = devm_request_irq(&pdev->dev, dev->irq, brcmstb_i2c_isr,\n+\t\t\t IRQF_SHARED,\n+\t\t\t int_name ? int_name : pdev->name,\n+\t\t\t dev);\n+\n+\tif (rc) {\n+\t\tdev_dbg(dev->device, \"falling back to polling mode\");\n+\t\tdev->irq = -1;\n+\t}\n+\n+\t/* Add the i2c adapter */\n+\tadap = &dev->adapter;\n+\ti2c_set_adapdata(adap, dev);\n+\tadap->owner = THIS_MODULE;\n+\tstrlcpy(adap->name, \"Broadcom STB : \", sizeof(adap->name));\n+\tif (int_name)\n+\t\tstrlcat(adap->name, int_name, sizeof(adap->name));\n+\tadap->algo = &brcmstb_i2c_algo;\n+\tadap->dev.parent = &pdev->dev;\n+\tadap->dev.of_node = pdev->dev.of_node;\n+\trc = i2c_add_adapter(adap);\n+\tif (rc) {\n+\t\tdev_err(dev->device, \"failed to add adapter\\n\");\n+\t\tgoto probe_errorout;\n+\t}\n+\n+\tif (of_property_read_u32(dev->device->of_node,\n+\t\t\t\t \"clock-frequency\", &dev->clk_freq_hz)) {\n+\t\tdev_warn(dev->device, \"missing clock-frequency property\\n\");\n+\t\tdev_warn(dev->device, \"setting default clock-frequency %dHz\\n\",\n+\t\t\t bsc_clk[0].hz);\n+\t\tdev->clk_freq_hz = bsc_clk[0].hz;\n+\t}\n+\n+\tbrcmstb_i2c_set_bsc_reg_defaults(dev);\n+\tdev_info(dev->device, \"%s@%dhz registered in %s mode\\n\",\n+\t\t int_name ? int_name : \" \", dev->clk_freq_hz,\n+\t\t (dev->irq >= 0) ? \"interrupt\" : \"polling\");\n+\n+\treturn 0;\n+\n+probe_errorout:\n+\tkfree(dev->bsc_regmap);\n+\treturn rc;\n+}\n+\n+static int brcmstb_i2c_remove(struct platform_device *pdev)\n+{\n+\tstruct brcmstb_i2c_dev *dev = platform_get_drvdata(pdev);\n+\n+\tkfree(dev->bsc_regmap);\n+\ti2c_del_adapter(&dev->adapter);\n+\n+\treturn 0;\n+}\n+\n+#ifdef CONFIG_PM_SLEEP\n+static int brcmstb_i2c_suspend(struct device *dev)\n+{\n+\tstruct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);\n+\n+\ti2c_lock_adapter(&i2c_dev->adapter);\n+\ti2c_dev->is_suspended = true;\n+\ti2c_unlock_adapter(&i2c_dev->adapter);\n+\n+\treturn 0;\n+}\n+\n+static int brcmstb_i2c_resume(struct device *dev)\n+{\n+\tstruct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev);\n+\n+\ti2c_lock_adapter(&i2c_dev->adapter);\n+\tbrcmstb_i2c_set_bsc_reg_defaults(i2c_dev);\n+\ti2c_dev->is_suspended = false;\n+\ti2c_unlock_adapter(&i2c_dev->adapter);\n+\n+\treturn 0;\n+}\n+#endif\n+\n+static SIMPLE_DEV_PM_OPS(brcmstb_i2c_pm, brcmstb_i2c_suspend,\n+\t\t\t brcmstb_i2c_resume);\n+\n+static const struct of_device_id brcmstb_i2c_of_match[] = {\n+\t{.compatible = \"brcm,brcmstb-i2c\"},\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, brcmstb_i2c_of_match);\n+\n+static struct platform_driver brcmstb_i2c_driver = {\n+\t.driver = {\n+\t\t .name = \"brcmstb-i2c\",\n+\t\t .owner = THIS_MODULE,\n+\t\t .of_match_table = brcmstb_i2c_of_match,\n+\t\t .pm = &brcmstb_i2c_pm,\n+\t\t },\n+\t.probe = brcmstb_i2c_probe,\n+\t.remove = brcmstb_i2c_remove,\n+};\n+module_platform_driver(brcmstb_i2c_driver);\n+\n+MODULE_AUTHOR(\"Kamal Dasu <kdasu@broadcom.com>\");\n+MODULE_DESCRIPTION(\"Broadcom Settop I2C Driver\");\n+MODULE_LICENSE(\"GPL v2\");\n", "prefixes": [ "V2", "1/2" ] }