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GET /api/patches/454886/?format=api
{ "id": 454886, "url": "http://patchwork.ozlabs.org/api/patches/454886/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/patch/1427348225-40731-2-git-send-email-b52261@freescale.com/", "project": { "id": 19, "url": "http://patchwork.ozlabs.org/api/projects/19/?format=api", "name": "Linux IMX development", "link_name": "linux-imx", "list_id": "linux-imx-kernel.lists.patchwork.ozlabs.org", "list_email": "linux-imx-kernel@lists.patchwork.ozlabs.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1427348225-40731-2-git-send-email-b52261@freescale.com>", "list_archive_url": null, "date": "2015-03-26T05:37:03", "name": "[v3,2/4] arm/layerscape/ls1021a: DCU pixel clock control", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "973f5d8ad7b80cfa1df1f1564e0b45493767b3bb", "submitter": { "id": 65958, "url": "http://patchwork.ozlabs.org/api/people/65958/?format=api", "name": "Jianwei Wang", "email": "b52261@freescale.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-imx/patch/1427348225-40731-2-git-send-email-b52261@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/454886/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/454886/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming-imx@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-imx@bilbo.ozlabs.org", "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n\t[IPv6:2001:1868:205::9])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 7C02C1400B7\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tThu, 26 Mar 2015 16:44:10 +1100 (AEDT)", "from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux))\n\tid 1Yb0XR-00038N-UG; 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Wed, 25 Mar 2015 22:40:30 -0700" ], "From": "Jianwei Wang <b52261@freescale.com>", "To": "<scottwood@freescale.com>, <airlied@linux.ie>,\n\t<dri-devel@lists.freedesktop.org>", "Subject": "[PATCH v3 2/4] arm/layerscape/ls1021a: DCU pixel clock control", "Date": "Thu, 26 Mar 2015 13:37:03 +0800", "Message-ID": "<1427348225-40731-2-git-send-email-b52261@freescale.com>", "X-Mailer": "git-send-email 2.1.0.27.g96db324", "In-Reply-To": "<1427348225-40731-1-git-send-email-b52261@freescale.com>", "References": "<1427348225-40731-1-git-send-email-b52261@freescale.com>", "X-EOPAttributedMessage": "0", "Received-SPF": "Fail (protection.outlook.com: domain of freescale.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=b52261@freescale.com; cmss.chinamobile.com;\n\tdkim=none (message not signed) header.d=none;", "X-Forefront-Antispam-Report": "CIP:192.88.168.50; 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\n\tHelo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM2PR0301MB1232", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20150325_224100_112359_A5D836E9 ", "X-CRM114-Status": "UNSURE ( 8.81 )", "X-CRM114-Notice": "Please train this message.", "X-Spam-Score": "-0.0 (/)", "X-Spam-Report": "SpamAssassin version 3.4.0 on bombadil.infradead.org summary:\n\tContent analysis details: (-0.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [65.55.169.130 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2)\n\t[65.55.169.130 listed in wl.mailspike.net]\n\t-0.0 SPF_HELO_PASS SPF: HELO matches SPF record", "Cc": "devicetree@vger.kernel.org, Xiubo Li <lixiubo@cmss.chinamobile.com>,\n\tAlison Wang <b18965@freescale.com>, linux-kernel@vger.kernel.org, Jianwei\n\tWang <b52261@freescale.com>, Jason.Jin@freescale.com,\n\tlinux-arm-kernel@lists.infradead.org", "X-BeenThere": "linux-arm-kernel@lists.infradead.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-arm-kernel/>", "List-Post": "<mailto:linux-arm-kernel@lists.infradead.org>", "List-Help": "<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>", "Errors-To": "linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org", "List-Id": "linux-imx-kernel.lists.patchwork.ozlabs.org" }, "content": "Enable DCU pixel clock when platform devices initinalizing and\nprovide enable and disable pixel clock functions for drm driver\n\nSigned-off-by: Alison Wang <b18965@freescale.com>\nSigned-off-by: Xiubo Li <lixiubo@cmss.chinamobile.com>\nSigned-off-by: Jianwei Wang <b52261@freescale.com>\n---\n arch/arm/mach-imx/mach-ls1021a.c | 36 ++++++++++++++++++++++++++++++++++++\n include/linux/fsl/dcu.h | 22 ++++++++++++++++++++++\n 2 files changed, 58 insertions(+)\n create mode 100644 include/linux/fsl/dcu.h", "diff": "diff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx/mach-ls1021a.c\nindex b89c858..4fb346d 100644\n--- a/arch/arm/mach-imx/mach-ls1021a.c\n+++ b/arch/arm/mach-imx/mach-ls1021a.c\n@@ -8,9 +8,44 @@\n */\n \n #include <asm/mach/arch.h>\n+#include <linux/of_platform.h>\n+#include <linux/mfd/syscon.h>\n+#include <linux/regmap.h>\n+#include <linux/fsl/dcu.h>\n \n #include \"common.h\"\n \n+void dcu_pixclk_disable(void)\n+{\n+\tstruct regmap *scfg_regmap;\n+\n+\tscfg_regmap = syscon_regmap_lookup_by_compatible(\"fsl,ls1021a-scfg\");\n+\tif (IS_ERR(scfg_regmap)) {\n+\t\tpr_err(\"No syscfg phandle specified\\n\");\n+\t\treturn;\n+\t}\n+\n+\tregmap_write(scfg_regmap, SCFG_PIXCLKCR, PXCK_DISABLE);\n+}\n+\n+void dcu_pixclk_enable(void)\n+{\n+\tstruct regmap *scfg_regmap;\n+\n+\tscfg_regmap = syscon_regmap_lookup_by_compatible(\"fsl,ls1021a-scfg\");\n+\tif (IS_ERR(scfg_regmap)) {\n+\t\tpr_err(\"No syscfg phandle specified\\n\");\n+\t\treturn;\n+\t}\n+\n+\tregmap_write(scfg_regmap, SCFG_PIXCLKCR, PXCK_ENABLE);\n+}\n+\n+static void __init ls1021a_init_machine(void)\n+{\n+\tof_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);\n+\tdcu_pixclk_enable();\n+}\n static const char * const ls1021a_dt_compat[] __initconst = {\n \t\"fsl,ls1021a\",\n \tNULL,\n@@ -18,5 +53,6 @@ static const char * const ls1021a_dt_compat[] __initconst = {\n \n DT_MACHINE_START(LS1021A, \"Freescale LS1021A\")\n \t.smp\t\t= smp_ops(ls1021a_smp_ops),\n+\t.init_machine\t= ls1021a_init_machine,\n \t.dt_compat\t= ls1021a_dt_compat,\n MACHINE_END\ndiff --git a/include/linux/fsl/dcu.h b/include/linux/fsl/dcu.h\nnew file mode 100644\nindex 0000000..1873057\n--- /dev/null\n+++ b/include/linux/fsl/dcu.h\n@@ -0,0 +1,22 @@\n+/*\n+ * Copyright 2015 Freescale Semiconductor, Inc.\n+ *\n+ * Freescale DCU drm device driver\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ */\n+\n+#ifndef __FSL_DCU_H__\n+#define __FSL_DCU_H__\n+\n+#define SCFG_PIXCLKCR\t\t\t0x28\n+#define PXCK_ENABLE\t\t\tBIT(31)\n+#define PXCK_DISABLE\t\t\t0\n+\n+void dcu_pixclk_enable(void);\n+void dcu_pixclk_disable(void);\n+\n+#endif /* __FSL_DCU_H__ */\n", "prefixes": [ "v3", "2/4" ] }