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GET /api/patches/454373/?format=api
{ "id": 454373, "url": "http://patchwork.ozlabs.org/api/patches/454373/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1427286206-28095-1-git-send-email-haikun.wang@freescale.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1427286206-28095-1-git-send-email-haikun.wang@freescale.com>", "list_archive_url": null, "date": "2015-03-25T12:23:26", "name": "[U-Boot,2/5,v2] dm: ls1021a: Bring in ls1021a dts files from linux kernel", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "42c1bb869e4ba73a979bd369b4630643d2a52df7", "submitter": { "id": 65869, "url": "http://patchwork.ozlabs.org/api/people/65869/?format=api", "name": "Haikun.Wang@freescale.com", "email": "Haikun.Wang@freescale.com" }, "delegate": { "id": 3184, "url": "http://patchwork.ozlabs.org/api/users/3184/?format=api", "username": "sjg", "first_name": "Simon", "last_name": "Glass", "email": "sjg@chromium.org" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1427286206-28095-1-git-send-email-haikun.wang@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/454373/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/454373/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id 2D200140119\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 25 Mar 2015 23:27:32 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 45CE5B37B2;\n\tWed, 25 Mar 2015 13:27:30 +0100 (CET)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id XpUhexTwcxY7; Wed, 25 Mar 2015 13:27:30 +0100 (CET)", "from theia.denx.de (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 98FF84A03B;\n\tWed, 25 Mar 2015 13:27:27 +0100 (CET)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id D6B3C4A03B\n\tfor <u-boot@lists.denx.de>; Wed, 25 Mar 2015 13:27:16 +0100 (CET)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id hJvp2wn6CDxc for <u-boot@lists.denx.de>;\n\tWed, 25 Mar 2015 13:27:16 +0100 (CET)", "from na01-bl2-obe.outbound.protection.outlook.com\n\t(mail-bl2on0102.outbound.protection.outlook.com [65.55.169.102])\n\tby theia.denx.de (Postfix) with ESMTPS id 22C0D4B653\n\tfor <u-boot@lists.denx.de>; Wed, 25 Mar 2015 13:26:45 +0100 (CET)", "from DM2PR03CA0028.namprd03.prod.outlook.com (10.141.96.27) by\n\tCY1PR0301MB0618.namprd03.prod.outlook.com (25.160.142.25) with\n\tMicrosoft SMTP\n\tServer (TLS) id 15.1.125.19; Wed, 25 Mar 2015 12:26:42 +0000", "from BN1BFFO11FD003.protection.gbl (2a01:111:f400:7c10::1:122) by\n\tDM2PR03CA0028.outlook.office365.com (2a01:111:e400:2428::27) with\n\tMicrosoft SMTP Server (TLS) id 15.1.125.19 via Frontend Transport;\n\tWed, 25 Mar 2015 12:26:42 +0000", "from tx30smr01.am.freescale.net ([192.88.168.50]) by\n\tBN1BFFO11FD003.mail.protection.outlook.com ([10.58.144.66]) with\n\tMicrosoft SMTP Server (TLS) id 15.1.130.10 via Frontend Transport;\n\tWed, 25 Mar 2015 12:26:42 +0000", "from titan.ap.freescale.net ([10.192.208.233])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tt2PCQbRE024424; Wed, 25 Mar 2015 05:26:39 -0700" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "Haikun Wang <haikun.wang@freescale.com>", "To": "<u-boot@lists.denx.de>", "Date": "Wed, 25 Mar 2015 20:23:26 +0800", "Message-ID": "<1427286206-28095-1-git-send-email-haikun.wang@freescale.com>", "X-Mailer": "git-send-email 2.1.0.27.g96db324", "X-EOPAttributedMessage": "0", "Received-SPF": "Fail (protection.outlook.com: domain of freescale.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=haikun.wang@freescale.com;\n\tfreescale.mail.onmicrosoft.com; \n\tdkim=none (message not signed) header.d=none;", "X-Forefront-Antispam-Report": "CIP:192.88.168.50; CTRY:US; IPV:NLI; EFV:NLI;\n\tBMV:1; SFV:NSPM;\n\tSFS:(10019020)(6009001)(339900001)(199003)(189002)(47776003)(19580395003)(19580405001)(50986999)(86362001)(87936001)(50226001)(85426001)(575784001)(106466001)(105606002)(46102003)(229853001)(110136001)(33646002)(2351001)(92566002)(50466002)(48376002)(77096005)(62966003)(77156002)(36756003);\n\tDIR:OUT; SFP:1102; SCL:1; SRVR:CY1PR0301MB0618;\n\tH:tx30smr01.am.freescale.net; \n\tFPR:; SPF:Fail; MLV:sfv; A:1; MX:1; LANG:en; ", "MIME-Version": "1.0", "X-Microsoft-Antispam": "UriScan:;BCL:0;PCL:0;RULEID:;SRVR:CY1PR0301MB0618;", "X-Microsoft-Antispam-PRVS": "<CY1PR0301MB0618B636FB9AA2D02153F8F8F80B0@CY1PR0301MB0618.namprd03.prod.outlook.com>", "X-Exchange-Antispam-Report-Test": "UriScan:;", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(601004)(5005006)(5002010); SRVR:CY1PR0301MB0618; BCL:0; PCL:0;\n\tRULEID:; SRVR:CY1PR0301MB0618; ", "X-Forefront-PRVS": "052670E5A4", "X-OriginatorOrg": "freescale.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "25 Mar 2015 12:26:42.0818\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "710a03f5-10f6-4d38-9ff4-a80b81da590d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY1PR0301MB0618", "Subject": "[U-Boot] [PATCH 2/5 v2] dm: ls1021a: Bring in ls1021a dts files\n\tfrom linux kernel", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: haikun <haikun.wang@freescale.com>\n\nBring in required device tree files for ls1021a from Linux.\nThese are initially unchanged and have a number of pieces not needed by U-Boot.\n\nSigned-off-by: Haikun Wang <Haikun.Wang@freescale.com>\n---\n\nChanges in v2:\n- Use CONFIG_LS102XA in arch/arm/dts/Makefile\n\nChanges in v1: None\n\n arch/arm/dts/Makefile | 3 +\n arch/arm/dts/ls1021a-qds.dts | 201 +++++++++++++++++++++++\n arch/arm/dts/ls1021a-twr.dts | 88 ++++++++++\n arch/arm/dts/ls1021a.dtsi | 370 +++++++++++++++++++++++++++++++++++++++++++\n 4 files changed, 662 insertions(+)\n create mode 100644 arch/arm/dts/ls1021a-qds.dts\n create mode 100644 arch/arm/dts/ls1021a-twr.dts\n create mode 100644 arch/arm/dts/ls1021a.dtsi", "diff": "diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex cbe5b86..c326707 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -54,6 +54,9 @@ dtb-$(CONFIG_SOCFPGA) +=\t\t\t\t\\\n \tsocfpga_cyclone5_socdk.dtb\t\t\t\\\n \tsocfpga_cyclone5_socrates.dtb\n \n+dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \\\n+\tls1021a-twr.dtb\n+\n targets += $(dtb-y)\n \n DTC_FLAGS += -R 4 -p 0x1000\ndiff --git a/arch/arm/dts/ls1021a-qds.dts b/arch/arm/dts/ls1021a-qds.dts\nnew file mode 100644\nindex 0000000..c89f85e\n--- /dev/null\n+++ b/arch/arm/dts/ls1021a-qds.dts\n@@ -0,0 +1,201 @@\n+/*\n+ * Freescale ls1021a QDS board device tree source\n+ *\n+ * Copyright 2013-2015 Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+/dts-v1/;\n+#include \"ls1021a.dtsi\"\n+\n+/ {\n+\tmodel = \"LS1021A QDS Board\";\n+\n+\taliases {\n+\t\tenet0_rgmii_phy = &rgmii_phy1;\n+\t\tenet1_rgmii_phy = &rgmii_phy2;\n+\t\tenet2_rgmii_phy = &rgmii_phy3;\n+\t\tenet0_sgmii_phy = &sgmii_phy1c;\n+\t\tenet1_sgmii_phy = &sgmii_phy1d;\n+\t};\n+};\n+\n+&dspi0 {\n+\tbus-num = <0>;\n+\tstatus = \"okay\";\n+\n+\tdspiflash: at45db021d@0 {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"atmel,at45db021d\", \"atmel,at45\", \"atmel,dataflash\";\n+\t\tspi-max-frequency = <16000000>;\n+\t\tspi-cpol;\n+\t\tspi-cpha;\n+\t\treg = <0>;\n+\t};\n+};\n+\n+&i2c0 {\n+\tstatus = \"okay\";\n+\n+\tpca9547: mux@77 {\n+\t\treg = <0x77>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\ti2c@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0x0>;\n+\n+\t\t\tds3232: rtc@68 {\n+\t\t\t\tcompatible = \"dallas,ds3232\";\n+\t\t\t\treg = <0x68>;\n+\t\t\t\tinterrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t};\n+\t\t};\n+\n+\t\ti2c@2 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0x2>;\n+\n+\t\t\tina220@40 {\n+\t\t\t\tcompatible = \"ti,ina220\";\n+\t\t\t\treg = <0x40>;\n+\t\t\t\tshunt-resistor = <1000>;\n+\t\t\t};\n+\n+\t\t\tina220@41 {\n+\t\t\t\tcompatible = \"ti,ina220\";\n+\t\t\t\treg = <0x41>;\n+\t\t\t\tshunt-resistor = <1000>;\n+\t\t\t};\n+\t\t};\n+\n+\t\ti2c@3 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0x3>;\n+\n+\t\t\teeprom@56 {\n+\t\t\t\tcompatible = \"atmel,24c512\";\n+\t\t\t\treg = <0x56>;\n+\t\t\t};\n+\n+\t\t\teeprom@57 {\n+\t\t\t\tcompatible = \"atmel,24c512\";\n+\t\t\t\treg = <0x57>;\n+\t\t\t};\n+\n+\t\t\tadt7461a@4c {\n+\t\t\t\tcompatible = \"adi,adt7461a\";\n+\t\t\t\treg = <0x4c>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&ifc {\n+\t#address-cells = <2>;\n+\t#size-cells = <1>;\n+\t/* NOR, NAND Flashes and FPGA on board */\n+\tranges = <0x0 0x0 0x0 0x60000000 0x08000000\n+\t\t 0x2 0x0 0x0 0x7e800000 0x00010000\n+\t\t 0x3 0x0 0x0 0x7fb00000 0x00000100>;\n+\tstatus = \"okay\";\n+\n+\tnor@0,0 {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"cfi-flash\";\n+\t\treg = <0x0 0x0 0x8000000>;\n+\t\tbank-width = <2>;\n+\t\tdevice-width = <1>;\n+\t};\n+\n+\tfpga: board-control@3,0 {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"simple-bus\";\n+\t\treg = <0x3 0x0 0x0000100>;\n+\t\tbank-width = <1>;\n+\t\tdevice-width = <1>;\n+\t\tranges = <0 3 0 0x100>;\n+\n+\t\tmdio-mux-emi1 {\n+\t\t\tcompatible = \"mdio-mux-mmioreg\";\n+\t\t\tmdio-parent-bus = <&mdio0>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0x54 1>; /* BRDCFG4 */\n+\t\t\tmux-mask = <0xe0>; /* EMI1[2:0] */\n+\n+\t\t\t/* Onboard PHYs */\n+\t\t\tls1021amdio0: mdio@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\trgmii_phy1: ethernet-phy@1 {\n+\t\t\t\t\treg = <0x1>;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tls1021amdio1: mdio@20 {\n+\t\t\t\treg = <0x20>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\trgmii_phy2: ethernet-phy@2 {\n+\t\t\t\t\treg = <0x2>;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tls1021amdio2: mdio@40 {\n+\t\t\t\treg = <0x40>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\trgmii_phy3: ethernet-phy@3 {\n+\t\t\t\t\treg = <0x3>;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tls1021amdio3: mdio@60 {\n+\t\t\t\treg = <0x60>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tsgmii_phy1c: ethernet-phy@1c {\n+\t\t\t\t\treg = <0x1c>;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tls1021amdio4: mdio@80 {\n+\t\t\t\treg = <0x80>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tsgmii_phy1d: ethernet-phy@1d {\n+\t\t\t\t\treg = <0x1d>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&lpuart0 {\n+\tstatus = \"okay\";\n+};\n+\n+&mdio0 {\n+\ttbi0: tbi-phy@8 {\n+\t\treg = <0x8>;\n+\t\tdevice_type = \"tbi-phy\";\n+\t};\n+};\n+\n+&uart0 {\n+\tstatus = \"okay\";\n+};\n+\n+&uart1 {\n+\tstatus = \"okay\";\n+};\ndiff --git a/arch/arm/dts/ls1021a-twr.dts b/arch/arm/dts/ls1021a-twr.dts\nnew file mode 100644\nindex 0000000..34ac82d\n--- /dev/null\n+++ b/arch/arm/dts/ls1021a-twr.dts\n@@ -0,0 +1,88 @@\n+/*\n+ * Freescale ls1021a TWR board device tree source\n+ *\n+ * Copyright 2013-2015 Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+/dts-v1/;\n+#include \"ls1021a.dtsi\"\n+\n+/ {\n+\tmodel = \"LS1021A TWR Board\";\n+\n+\taliases {\n+\t\tenet2_rgmii_phy = &rgmii_phy1;\n+\t\tenet0_sgmii_phy = &sgmii_phy2;\n+\t\tenet1_sgmii_phy = &sgmii_phy0;\n+\t};\n+};\n+\n+&dspi1 {\n+\tbus-num = <0>;\n+\tstatus = \"okay\";\n+\n+\tdspiflash: s25fl064k@0 {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"spansion,s25fl064k\";\n+\t\tspi-max-frequency = <16000000>;\n+\t\tspi-cpol;\n+\t\tspi-cpha;\n+\t\treg = <0>;\n+\t};\n+};\n+\n+&i2c0 {\n+\tstatus = \"okay\";\n+};\n+\n+&i2c1 {\n+\tstatus = \"okay\";\n+};\n+\n+&ifc {\n+\t#address-cells = <2>;\n+\t#size-cells = <1>;\n+\t/* NOR Flash on board */\n+\tranges = <0x0 0x0 0x0 0x60000000 0x08000000>;\n+\tstatus = \"okay\";\n+\n+\tnor@0,0 {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"cfi-flash\";\n+\t\treg = <0x0 0x0 0x8000000>;\n+\t\tbank-width = <2>;\n+\t\tdevice-width = <1>;\n+\t};\n+};\n+\n+&lpuart0 {\n+\tstatus = \"okay\";\n+};\n+\n+&mdio0 {\n+\tsgmii_phy0: ethernet-phy@0 {\n+\t\treg = <0x0>;\n+\t};\n+\trgmii_phy1: ethernet-phy@1 {\n+\t\treg = <0x1>;\n+\t};\n+\tsgmii_phy2: ethernet-phy@2 {\n+\t\treg = <0x2>;\n+\t};\n+\ttbi1: tbi-phy@1f {\n+\t\treg = <0x1f>;\n+\t\tdevice_type = \"tbi-phy\";\n+\t};\n+};\n+\n+&uart0 {\n+\tstatus = \"okay\";\n+};\n+\n+&uart1 {\n+\tstatus = \"okay\";\n+};\ndiff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi\nnew file mode 100644\nindex 0000000..434b938\n--- /dev/null\n+++ b/arch/arm/dts/ls1021a.dtsi\n@@ -0,0 +1,370 @@\n+/*\n+ * Freescale ls1021a SOC common device tree source\n+ *\n+ * Copyright 2013-2015 Freescale Semiconductor, Inc.\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include \"skeleton64.dtsi\"\n+#include <dt-bindings/interrupt-controller/arm-gic.h>\n+\n+/ {\n+\tcompatible = \"fsl,ls1021a\";\n+\tinterrupt-parent = <&gic>;\n+\n+\taliases {\n+\t\tserial0 = &lpuart0;\n+\t\tserial1 = &lpuart1;\n+\t\tserial2 = &lpuart2;\n+\t\tserial3 = &lpuart3;\n+\t\tserial4 = &lpuart4;\n+\t\tserial5 = &lpuart5;\n+\t\tsysclk = &sysclk;\n+\t};\n+\n+\tcpus {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tcpu@f00 {\n+\t\t\tcompatible = \"arm,cortex-a7\";\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\treg = <0xf00>;\n+\t\t\tclocks = <&cluster1_clk>;\n+\t\t};\n+\n+\t\tcpu@f01 {\n+\t\t\tcompatible = \"arm,cortex-a7\";\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\treg = <0xf01>;\n+\t\t\tclocks = <&cluster1_clk>;\n+\t\t};\n+\t};\n+\n+\ttimer {\n+\t\tcompatible = \"arm,armv7-timer\";\n+\t\tinterrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,\n+\t\t\t <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,\n+\t\t\t <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,\n+\t\t\t <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;\n+\t};\n+\n+\tpmu {\n+\t\tcompatible = \"arm,cortex-a7-pmu\";\n+\t\tinterrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;\n+\t};\n+\n+\tsoc {\n+\t\tcompatible = \"simple-bus\";\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\t\tdevice_type = \"soc\";\n+\t\tinterrupt-parent = <&gic>;\n+\t\tranges;\n+\n+\t\tgic: interrupt-controller@1400000 {\n+\t\t\tcompatible = \"arm,cortex-a7-gic\";\n+\t\t\t#interrupt-cells = <3>;\n+\t\t\tinterrupt-controller;\n+\t\t\treg = <0x0 0x1401000 0x0 0x1000>,\n+\t\t\t <0x0 0x1402000 0x0 0x1000>,\n+\t\t\t <0x0 0x1404000 0x0 0x2000>,\n+\t\t\t <0x0 0x1406000 0x0 0x2000>;\n+\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;\n+\n+\t\t};\n+\n+\t\tifc: ifc@1530000 {\n+\t\t\tcompatible = \"fsl,ifc\", \"simple-bus\";\n+\t\t\treg = <0x0 0x1530000 0x0 0x10000>;\n+\t\t\tinterrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t};\n+\n+\t\tdcfg: dcfg@1ee0000 {\n+\t\t\tcompatible = \"fsl,ls1021a-dcfg\", \"syscon\";\n+\t\t\treg = <0x0 0x1ee0000 0x0 0x10000>;\n+\t\t\tbig-endian;\n+\t\t};\n+\n+\t\tesdhc: esdhc@1560000 {\n+\t\t\tcompatible = \"fsl,esdhc\";\n+\t\t\treg = <0x0 0x1560000 0x0 0x10000>;\n+\t\t\tinterrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclock-frequency = <0>;\n+\t\t\tvoltage-ranges = <1800 1800 3300 3300>;\n+\t\t\tsdhci,auto-cmd12;\n+\t\t\tbig-endian;\n+\t\t\tbus-width = <4>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tscfg: scfg@1570000 {\n+\t\t\tcompatible = \"fsl,ls1021a-scfg\", \"syscon\";\n+\t\t\treg = <0x0 0x1570000 0x0 0x10000>;\n+\t\t\tbig-endian;\n+\t\t};\n+\n+\t\tclockgen: clocking@1ee1000 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges = <0x0 0x0 0x1ee1000 0x10000>;\n+\n+\t\t\tsysclk: sysclk {\n+\t\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\tclock-output-names = \"sysclk\";\n+\t\t\t};\n+\n+\t\t\tcga_pll1: pll@800 {\n+\t\t\t\tcompatible = \"fsl,qoriq-core-pll-2.0\";\n+\t\t\t\t#clock-cells = <1>;\n+\t\t\t\treg = <0x800 0x10>;\n+\t\t\t\tclocks = <&sysclk>;\n+\t\t\t\tclock-output-names = \"cga-pll1\", \"cga-pll1-div2\",\n+\t\t\t\t\t\t \"cga-pll1-div4\";\n+\t\t\t};\n+\n+\t\t\tplatform_clk: pll@c00 {\n+\t\t\t\tcompatible = \"fsl,qoriq-core-pll-2.0\";\n+\t\t\t\t#clock-cells = <1>;\n+\t\t\t\treg = <0xc00 0x10>;\n+\t\t\t\tclocks = <&sysclk>;\n+\t\t\t\tclock-output-names = \"platform-clk\", \"platform-clk-div2\";\n+\t\t\t};\n+\n+\t\t\tcluster1_clk: clk0c0@0 {\n+\t\t\t\tcompatible = \"fsl,qoriq-core-mux-2.0\";\n+\t\t\t\t#clock-cells = <0>;\n+\t\t\t\treg = <0x0 0x10>;\n+\t\t\t\tclock-names = \"pll1cga\", \"pll1cga-div2\", \"pll1cga-div4\";\n+\t\t\t\tclocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;\n+\t\t\t\tclock-output-names = \"cluster1-clk\";\n+\t\t\t};\n+\t\t};\n+\n+\t\tdspi0: dspi@2100000 {\n+\t\t\tcompatible = \"fsl,vf610-dspi\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0x0 0x2100000 0x0 0x10000>;\n+\t\t\tinterrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclock-names = \"dspi\";\n+\t\t\tclocks = <&platform_clk 1>;\n+\t\t\tspi-num-chipselects = <5>;\n+\t\t\tbig-endian;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tdspi1: dspi@2110000 {\n+\t\t\tcompatible = \"fsl,vf610-dspi\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0x0 0x2110000 0x0 0x10000>;\n+\t\t\tinterrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclock-names = \"dspi\";\n+\t\t\tclocks = <&platform_clk 1>;\n+\t\t\tspi-num-chipselects = <5>;\n+\t\t\tbig-endian;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\ti2c0: i2c@2180000 {\n+\t\t\tcompatible = \"fsl,vf610-i2c\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0x0 0x2180000 0x0 0x10000>;\n+\t\t\tinterrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclock-names = \"i2c\";\n+\t\t\tclocks = <&platform_clk 1>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\ti2c1: i2c@2190000 {\n+\t\t\tcompatible = \"fsl,vf610-i2c\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0x0 0x2190000 0x0 0x10000>;\n+\t\t\tinterrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclock-names = \"i2c\";\n+\t\t\tclocks = <&platform_clk 1>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\ti2c2: i2c@21a0000 {\n+\t\t\tcompatible = \"fsl,vf610-i2c\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0x0 0x21a0000 0x0 0x10000>;\n+\t\t\tinterrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclock-names = \"i2c\";\n+\t\t\tclocks = <&platform_clk 1>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart0: serial@21c0500 {\n+\t\t\tcompatible = \"fsl,16550-FIFO64\", \"ns16550a\";\n+\t\t\treg = <0x0 0x21c0500 0x0 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclock-frequency = <0>;\n+\t\t\tfifo-size = <15>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart1: serial@21c0600 {\n+\t\t\tcompatible = \"fsl,16550-FIFO64\", \"ns16550a\";\n+\t\t\treg = <0x0 0x21c0600 0x0 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclock-frequency = <0>;\n+\t\t\tfifo-size = <15>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart2: serial@21d0500 {\n+\t\t\tcompatible = \"fsl,16550-FIFO64\", \"ns16550a\";\n+\t\t\treg = <0x0 0x21d0500 0x0 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclock-frequency = <0>;\n+\t\t\tfifo-size = <15>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tuart3: serial@21d0600 {\n+\t\t\tcompatible = \"fsl,16550-FIFO64\", \"ns16550a\";\n+\t\t\treg = <0x0 0x21d0600 0x0 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclock-frequency = <0>;\n+\t\t\tfifo-size = <15>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tlpuart0: serial@2950000 {\n+\t\t\tcompatible = \"fsl,ls1021a-lpuart\";\n+\t\t\treg = <0x0 0x2950000 0x0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&sysclk>;\n+\t\t\tclock-names = \"ipg\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tlpuart1: serial@2960000 {\n+\t\t\tcompatible = \"fsl,ls1021a-lpuart\";\n+\t\t\treg = <0x0 0x2960000 0x0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&platform_clk 1>;\n+\t\t\tclock-names = \"ipg\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tlpuart2: serial@2970000 {\n+\t\t\tcompatible = \"fsl,ls1021a-lpuart\";\n+\t\t\treg = <0x0 0x2970000 0x0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&platform_clk 1>;\n+\t\t\tclock-names = \"ipg\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tlpuart3: serial@2980000 {\n+\t\t\tcompatible = \"fsl,ls1021a-lpuart\";\n+\t\t\treg = <0x0 0x2980000 0x0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&platform_clk 1>;\n+\t\t\tclock-names = \"ipg\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tlpuart4: serial@2990000 {\n+\t\t\tcompatible = \"fsl,ls1021a-lpuart\";\n+\t\t\treg = <0x0 0x2990000 0x0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&platform_clk 1>;\n+\t\t\tclock-names = \"ipg\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tlpuart5: serial@29a0000 {\n+\t\t\tcompatible = \"fsl,ls1021a-lpuart\";\n+\t\t\treg = <0x0 0x29a0000 0x0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&platform_clk 1>;\n+\t\t\tclock-names = \"ipg\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\twdog0: watchdog@2ad0000 {\n+\t\t\tcompatible = \"fsl,imx21-wdt\";\n+\t\t\treg = <0x0 0x2ad0000 0x0 0x10000>;\n+\t\t\tinterrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&platform_clk 1>;\n+\t\t\tclock-names = \"wdog-en\";\n+\t\t\tbig-endian;\n+\t\t};\n+\n+\t\tsai1: sai@2b50000 {\n+\t\t\tcompatible = \"fsl,vf610-sai\";\n+\t\t\treg = <0x0 0x2b50000 0x0 0x10000>;\n+\t\t\tinterrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&platform_clk 1>;\n+\t\t\tclock-names = \"sai\";\n+\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\tdmas = <&edma0 1 47>,\n+\t\t\t <&edma0 1 46>;\n+\t\t\tbig-endian;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tsai2: sai@2b60000 {\n+\t\t\tcompatible = \"fsl,vf610-sai\";\n+\t\t\treg = <0x0 0x2b60000 0x0 0x10000>;\n+\t\t\tinterrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&platform_clk 1>;\n+\t\t\tclock-names = \"sai\";\n+\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\tdmas = <&edma0 1 45>,\n+\t\t\t <&edma0 1 44>;\n+\t\t\tbig-endian;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tedma0: edma@2c00000 {\n+\t\t\t#dma-cells = <2>;\n+\t\t\tcompatible = \"fsl,vf610-edma\";\n+\t\t\treg = <0x0 0x2c00000 0x0 0x10000>,\n+\t\t\t <0x0 0x2c10000 0x0 0x10000>,\n+\t\t\t <0x0 0x2c20000 0x0 0x10000>;\n+\t\t\tinterrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-names = \"edma-tx\", \"edma-err\";\n+\t\t\tdma-channels = <32>;\n+\t\t\tbig-endian;\n+\t\t\tclock-names = \"dmamux0\", \"dmamux1\";\n+\t\t\tclocks = <&platform_clk 1>,\n+\t\t\t\t <&platform_clk 1>;\n+\t\t};\n+\n+\t\tmdio0: mdio@2d24000 {\n+\t\t\tcompatible = \"gianfar\";\n+\t\t\tdevice_type = \"mdio\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0x0 0x2d24000 0x0 0x4000>;\n+\t\t};\n+\n+\t\tusb@8600000 {\n+\t\t\tcompatible = \"fsl-usb2-dr-v2.5\", \"fsl-usb2-dr\";\n+\t\t\treg = <0x0 0x8600000 0x0 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tdr_mode = \"host\";\n+\t\t\tphy_type = \"ulpi\";\n+\t\t};\n+\n+\t\tusb3@3100000 {\n+\t\t\tcompatible = \"snps,dwc3\";\n+\t\t\treg = <0x0 0x3100000 0x0 0x10000>;\n+\t\t\tinterrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tdr_mode = \"host\";\n+\t\t};\n+\t};\n+};\n", "prefixes": [ "U-Boot", "2/5", "v2" ] }