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{
    "id": 454248,
    "url": "http://patchwork.ozlabs.org/api/patches/454248/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/1427265761-31828-1-git-send-email-Minghuan.Lian@freescale.com/",
    "project": {
        "id": 28,
        "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api",
        "name": "Linux PCI development",
        "link_name": "linux-pci",
        "list_id": "linux-pci.vger.kernel.org",
        "list_email": "linux-pci@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
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    },
    "msgid": "<1427265761-31828-1-git-send-email-Minghuan.Lian@freescale.com>",
    "list_archive_url": null,
    "date": "2015-03-25T06:42:38",
    "name": "arm/dts/ls1021a: Add PCIe dts node",
    "commit_ref": null,
    "pull_url": null,
    "state": "not-applicable",
    "archived": false,
    "hash": "4e4393674e230cd95f4636fe94c6e6b36474393a",
    "submitter": {
        "id": 16185,
        "url": "http://patchwork.ozlabs.org/api/people/16185/?format=api",
        "name": "Minghuan Lian",
        "email": "Minghuan.Lian@freescale.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/1427265761-31828-1-git-send-email-Minghuan.Lian@freescale.com/mbox/",
    "series": [],
    "comments": "http://patchwork.ozlabs.org/api/patches/454248/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/454248/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-pci-owner@vger.kernel.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
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        ],
        "From": "Minghuan Lian <Minghuan.Lian@freescale.com>",
        "To": "<linux-pci@vger.kernel.org>",
        "CC": "<linux-arm-kernel@lists.infradead.org>,\n\tZang Roy-R61911 <r61911@freescale.com>,\n\tHu Mingkai-B21284 <B21284@freescale.com>,\n\tScott Wood <scottwood@freescale.com>,\n\tYoder Stuart-B08248 <stuart.yoder@freescale.com>,\n\tArnd Bergmann <arnd@arndb.de>, Bjorn Helgaas <bhelgaas@google.com>,\n\t\"Jingoo Han\" <jg1.han@samsung.com>,\n\tMinghuan Lian <Minghuan.Lian@freescale.com>",
        "Subject": "[PATCH] arm/dts/ls1021a: Add PCIe dts node",
        "Date": "Wed, 25 Mar 2015 14:42:38 +0800",
        "Message-ID": "<1427265761-31828-1-git-send-email-Minghuan.Lian@freescale.com>",
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        "Sender": "linux-pci-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<linux-pci.vger.kernel.org>",
        "X-Mailing-List": "linux-pci@vger.kernel.org"
    },
    "content": "Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>\n---\n arch/arm/boot/dts/ls1021a.dtsi | 48 ++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 48 insertions(+)",
    "diff": "diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi\nindex c70bb27..2f9556e 100644\n--- a/arch/arm/boot/dts/ls1021a.dtsi\n+++ b/arch/arm/boot/dts/ls1021a.dtsi\n@@ -405,5 +405,53 @@\n \t\t\tinterrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tdr_mode = \"host\";\n \t\t};\n+\n+\t\tpcie@3400000 {\n+\t\t\tcompatible = \"fsl,ls1021a-pcie\", \"snps,dw-pcie\";\n+\t\t\treg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */\n+\t\t\t       0x40 0x00000000 0x0 0x00002000>; /* configuration space */\n+\t\t\treg-names = \"regs\", \"config\";\n+\t\t\tinterrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */\n+\t\t\t\t     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */\n+\t\t\tinterrupt-names = \"intr\", \"pme\";\n+\t\t\tfsl,pcie-scfg = <&scfg 0>;\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tdevice_type = \"pci\";\n+\t\t\tnum-lanes = <4>;\n+\t\t\tbus-range = <0x0 0xff>;\n+\t\t\tranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */\n+\t\t\t\t  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */\n+\t\t\t#interrupt-cells = <1>;\n+\t\t\tinterrupt-map-mask = <0 0 0 7>;\n+\t\t\tinterrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t};\n+\n+\t\tpcie@3500000 {\n+\t\t\tcompatible = \"fsl,ls1021a-pcie\", \"snps,dw-pcie\";\n+\t\t\treg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */\n+\t\t\t       0x48 0x00000000 0x0 0x00002000>; /* configuration space */\n+\t\t\treg-names = \"regs\", \"config\";\n+\t\t\tinterrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-names = \"intr\", \"pme\";\n+\t\t\tfsl,pcie-scfg = <&scfg 1>;\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tdevice_type = \"pci\";\n+\t\t\tnum-lanes = <2>;\n+\t\t\tbus-range = <0x0 0xff>;\n+\t\t\tranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */\n+\t\t\t\t  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */\n+\t\t\t#interrupt-cells = <1>;\n+\t\t\tinterrupt-map-mask = <0 0 0 7>;\n+\t\t\tinterrupt-map = <0000 0 0 1 &gic GIC_SPI 92  IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t};\n \t};\n };\n",
    "prefixes": []
}