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GET /api/patches/453829/?format=api
{ "id": 453829, "url": "http://patchwork.ozlabs.org/api/patches/453829/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1427202991-27150-1-git-send-email-haikun.wang@freescale.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1427202991-27150-1-git-send-email-haikun.wang@freescale.com>", "list_archive_url": null, "date": "2015-03-24T13:16:31", "name": "[U-Boot,3/5,v1] dm: ls1021a: dts: Change address_cells and size_cells from 2 to 1", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "3da604bc933d3c97f48d64a55b3349e758e22e38", "submitter": { "id": 65869, "url": "http://patchwork.ozlabs.org/api/people/65869/?format=api", "name": "Haikun.Wang@freescale.com", "email": "Haikun.Wang@freescale.com" }, "delegate": { "id": 3184, "url": "http://patchwork.ozlabs.org/api/users/3184/?format=api", "username": "sjg", "first_name": "Simon", "last_name": "Glass", "email": "sjg@chromium.org" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1427202991-27150-1-git-send-email-haikun.wang@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/453829/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/453829/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id F3D45140079\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 25 Mar 2015 00:19:57 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 400FC4A04A;\n\tTue, 24 Mar 2015 14:19:56 +0100 (CET)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id bsg2aKv_g6Hy; Tue, 24 Mar 2015 14:19:56 +0100 (CET)", "from theia.denx.de (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id CFF554A036;\n\tTue, 24 Mar 2015 14:19:55 +0100 (CET)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 2E6644A036\n\tfor <u-boot@lists.denx.de>; Tue, 24 Mar 2015 14:19:52 +0100 (CET)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id neUiwH0w8KCB for <u-boot@lists.denx.de>;\n\tTue, 24 Mar 2015 14:19:52 +0100 (CET)", "from na01-by2-obe.outbound.protection.outlook.com\n\t(mail-by2on0141.outbound.protection.outlook.com [207.46.100.141])\n\tby theia.denx.de (Postfix) with ESMTPS id 3FAB94A029\n\tfor <u-boot@lists.denx.de>; Tue, 24 Mar 2015 14:19:48 +0100 (CET)", "from DM2PR03CA0051.namprd03.prod.outlook.com (10.141.96.50) by\n\tCY1PR0301MB0617.namprd03.prod.outlook.com (25.160.142.24) with\n\tMicrosoft SMTP\n\tServer (TLS) id 15.1.118.21; Tue, 24 Mar 2015 13:19:42 +0000", "from BL2FFO11FD040.protection.gbl (2a01:111:f400:7c09::118) by\n\tDM2PR03CA0051.outlook.office365.com (2a01:111:e400:2428::50) with\n\tMicrosoft SMTP Server (TLS) id 15.1.118.21 via Frontend Transport;\n\tTue, 24 Mar 2015 13:19:42 +0000", "from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBL2FFO11FD040.mail.protection.outlook.com (10.173.161.136) with\n\tMicrosoft SMTP Server (TLS) id 15.1.125.13 via Frontend Transport;\n\tTue, 24 Mar 2015 13:19:41 +0000", "from titan.ap.freescale.net ([10.192.208.233])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tt2ODJcFh016179; Tue, 24 Mar 2015 06:19:39 -0700" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "Haikun Wang <haikun.wang@freescale.com>", "To": "<u-boot@lists.denx.de>", "Date": "Tue, 24 Mar 2015 21:16:31 +0800", "Message-ID": "<1427202991-27150-1-git-send-email-haikun.wang@freescale.com>", "X-Mailer": "git-send-email 2.1.0.27.g96db324", "X-EOPAttributedMessage": "0", "Received-SPF": "Fail (protection.outlook.com: domain of freescale.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=haikun.wang@freescale.com;\n\tfreescale.mail.onmicrosoft.com; \n\tdkim=none (message not signed) header.d=none;", "X-Forefront-Antispam-Report": "CIP:192.88.168.50; CTRY:US; IPV:NLI; EFV:NLI;\n\tBMV:1; SFV:NSPM;\n\tSFS:(10019020)(979002)(6009001)(339900001)(199003)(189002)(50226001)(36756003)(50466002)(229853001)(110136001)(47776003)(6806004)(87936001)(85426001)(19580405001)(19580395003)(62966003)(77156002)(50986999)(106466001)(104016003)(48376002)(2351001)(33646002)(92566002)(77096005)(86362001)(46102003)(105606002)(21314002)(969003)(989001)(999001)(1009001)(1019001);\n\tDIR:OUT; SFP:1102; SCL:1; SRVR:CY1PR0301MB0617;\n\tH:tx30smr01.am.freescale.net; \n\tFPR:; SPF:Fail; MLV:ovrnspm; A:1; MX:1; PTR:InfoDomainNonexistent;\n\tLANG:en; ", "MIME-Version": "1.0", "X-Microsoft-Antispam": "UriScan:;BCL:0;PCL:0;RULEID:;SRVR:CY1PR0301MB0617;", "X-Microsoft-Antispam-PRVS": "<CY1PR0301MB06177EB486B167DDDF8C4042F80A0@CY1PR0301MB0617.namprd03.prod.outlook.com>", "X-Exchange-Antispam-Report-Test": "UriScan:;", "X-Exchange-Antispam-Report-CFA-Test": "BCL:0; PCL:0;\n\tRULEID:(601004)(5002010)(5005006); SRVR:CY1PR0301MB0617; BCL:0; PCL:0;\n\tRULEID:; SRVR:CY1PR0301MB0617; ", "X-Forefront-PRVS": "0525BB0ADF", "X-OriginatorOrg": "freescale.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Mar 2015 13:19:41.6410\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "710a03f5-10f6-4d38-9ff4-a80b81da590d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY1PR0301MB0617", "Subject": "[U-Boot] [PATCH 3/5 v1] dm: ls1021a: dts: Change address_cells and\n\tsize_cells from 2 to 1", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: haikun <haikun.wang@freescale.com>\n\nChange address_cells and size_cells of root node and 'soc' node\nfrom 2 to 1.\n\nWe backport ls1021a device tree source files from kernel to u-boot.\nKernel files set address_cells and size_cells to 2 in order to access\nmore than 4GB space.\nBut we don't have this requirement now and u-boot fdtdec_get_xxx interfaces\ncan't support property whose size is 'u64' completely.\nSo make this change.\n\nSigned-off-by: Haikun Wang <Haikun.Wang@freescale.com>\n---\n arch/arm/dts/ls1021a-qds.dts | 6 ++--\n arch/arm/dts/ls1021a-twr.dts | 2 +-\n arch/arm/dts/ls1021a.dtsi | 72 ++++++++++++++++++++++----------------------\n 3 files changed, 40 insertions(+), 40 deletions(-)", "diff": "diff --git a/arch/arm/dts/ls1021a-qds.dts b/arch/arm/dts/ls1021a-qds.dts\nindex c89f85e..7454ac6 100644\n--- a/arch/arm/dts/ls1021a-qds.dts\n+++ b/arch/arm/dts/ls1021a-qds.dts\n@@ -101,9 +101,9 @@\n \t#address-cells = <2>;\n \t#size-cells = <1>;\n \t/* NOR, NAND Flashes and FPGA on board */\n-\tranges = <0x0 0x0 0x0 0x60000000 0x08000000\n-\t\t 0x2 0x0 0x0 0x7e800000 0x00010000\n-\t\t 0x3 0x0 0x0 0x7fb00000 0x00000100>;\n+\tranges = <0x0 0x0 0x60000000 0x08000000\n+\t\t 0x2 0x0 0x7e800000 0x00010000\n+\t\t 0x3 0x0 0x7fb00000 0x00000100>;\n \tstatus = \"okay\";\n \n \tnor@0,0 {\ndiff --git a/arch/arm/dts/ls1021a-twr.dts b/arch/arm/dts/ls1021a-twr.dts\nindex 34ac82d..2f0481d 100644\n--- a/arch/arm/dts/ls1021a-twr.dts\n+++ b/arch/arm/dts/ls1021a-twr.dts\n@@ -46,7 +46,7 @@\n \t#address-cells = <2>;\n \t#size-cells = <1>;\n \t/* NOR Flash on board */\n-\tranges = <0x0 0x0 0x0 0x60000000 0x08000000>;\n+\tranges = <0x0 0x0 0x60000000 0x08000000>;\n \tstatus = \"okay\";\n \n \tnor@0,0 {\ndiff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi\nindex 434b938..064d10c 100644\n--- a/arch/arm/dts/ls1021a.dtsi\n+++ b/arch/arm/dts/ls1021a.dtsi\n@@ -6,7 +6,7 @@\n * SPDX-License-Identifier:\tGPL-2.0+\n */\n \n-#include \"skeleton64.dtsi\"\n+#include \"skeleton.dtsi\"\n #include <dt-bindings/interrupt-controller/arm-gic.h>\n \n / {\n@@ -58,8 +58,8 @@\n \n \tsoc {\n \t\tcompatible = \"simple-bus\";\n-\t\t#address-cells = <2>;\n-\t\t#size-cells = <2>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n \t\tdevice_type = \"soc\";\n \t\tinterrupt-parent = <&gic>;\n \t\tranges;\n@@ -68,29 +68,29 @@\n \t\t\tcompatible = \"arm,cortex-a7-gic\";\n \t\t\t#interrupt-cells = <3>;\n \t\t\tinterrupt-controller;\n-\t\t\treg = <0x0 0x1401000 0x0 0x1000>,\n-\t\t\t <0x0 0x1402000 0x0 0x1000>,\n-\t\t\t <0x0 0x1404000 0x0 0x2000>,\n-\t\t\t <0x0 0x1406000 0x0 0x2000>;\n+\t\t\treg = <0x1401000 0x1000>,\n+\t\t\t <0x1402000 0x1000>,\n+\t\t\t <0x1404000 0x2000>,\n+\t\t\t <0x1406000 0x2000>;\n \t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;\n \n \t\t};\n \n \t\tifc: ifc@1530000 {\n \t\t\tcompatible = \"fsl,ifc\", \"simple-bus\";\n-\t\t\treg = <0x0 0x1530000 0x0 0x10000>;\n+\t\t\treg = <0x1530000 0x10000>;\n \t\t\tinterrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;\n \t\t};\n \n \t\tdcfg: dcfg@1ee0000 {\n \t\t\tcompatible = \"fsl,ls1021a-dcfg\", \"syscon\";\n-\t\t\treg = <0x0 0x1ee0000 0x0 0x10000>;\n+\t\t\treg = <0x1ee0000 0x10000>;\n \t\t\tbig-endian;\n \t\t};\n \n \t\tesdhc: esdhc@1560000 {\n \t\t\tcompatible = \"fsl,esdhc\";\n-\t\t\treg = <0x0 0x1560000 0x0 0x10000>;\n+\t\t\treg = <0x1560000 0x10000>;\n \t\t\tinterrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tclock-frequency = <0>;\n \t\t\tvoltage-ranges = <1800 1800 3300 3300>;\n@@ -102,14 +102,14 @@\n \n \t\tscfg: scfg@1570000 {\n \t\t\tcompatible = \"fsl,ls1021a-scfg\", \"syscon\";\n-\t\t\treg = <0x0 0x1570000 0x0 0x10000>;\n+\t\t\treg = <0x1570000 0x10000>;\n \t\t\tbig-endian;\n \t\t};\n \n \t\tclockgen: clocking@1ee1000 {\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <1>;\n-\t\t\tranges = <0x0 0x0 0x1ee1000 0x10000>;\n+\t\t\tranges = <0x0 0x1ee1000 0x10000>;\n \n \t\t\tsysclk: sysclk {\n \t\t\t\tcompatible = \"fixed-clock\";\n@@ -148,7 +148,7 @@\n \t\t\tcompatible = \"fsl,vf610-dspi\";\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t\treg = <0x0 0x2100000 0x0 0x10000>;\n+\t\t\treg = <0x2100000 0x10000>;\n \t\t\tinterrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tclock-names = \"dspi\";\n \t\t\tclocks = <&platform_clk 1>;\n@@ -161,7 +161,7 @@\n \t\t\tcompatible = \"fsl,vf610-dspi\";\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t\treg = <0x0 0x2110000 0x0 0x10000>;\n+\t\t\treg = <0x2110000 0x10000>;\n \t\t\tinterrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tclock-names = \"dspi\";\n \t\t\tclocks = <&platform_clk 1>;\n@@ -174,7 +174,7 @@\n \t\t\tcompatible = \"fsl,vf610-i2c\";\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t\treg = <0x0 0x2180000 0x0 0x10000>;\n+\t\t\treg = <0x2180000 0x10000>;\n \t\t\tinterrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tclock-names = \"i2c\";\n \t\t\tclocks = <&platform_clk 1>;\n@@ -185,7 +185,7 @@\n \t\t\tcompatible = \"fsl,vf610-i2c\";\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t\treg = <0x0 0x2190000 0x0 0x10000>;\n+\t\t\treg = <0x2190000 0x10000>;\n \t\t\tinterrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tclock-names = \"i2c\";\n \t\t\tclocks = <&platform_clk 1>;\n@@ -196,7 +196,7 @@\n \t\t\tcompatible = \"fsl,vf610-i2c\";\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t\treg = <0x0 0x21a0000 0x0 0x10000>;\n+\t\t\treg = <0x21a0000 0x10000>;\n \t\t\tinterrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tclock-names = \"i2c\";\n \t\t\tclocks = <&platform_clk 1>;\n@@ -205,7 +205,7 @@\n \n \t\tuart0: serial@21c0500 {\n \t\t\tcompatible = \"fsl,16550-FIFO64\", \"ns16550a\";\n-\t\t\treg = <0x0 0x21c0500 0x0 0x100>;\n+\t\t\treg = <0x21c0500 0x100>;\n \t\t\tinterrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tclock-frequency = <0>;\n \t\t\tfifo-size = <15>;\n@@ -214,7 +214,7 @@\n \n \t\tuart1: serial@21c0600 {\n \t\t\tcompatible = \"fsl,16550-FIFO64\", \"ns16550a\";\n-\t\t\treg = <0x0 0x21c0600 0x0 0x100>;\n+\t\t\treg = <0x21c0600 0x100>;\n \t\t\tinterrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tclock-frequency = <0>;\n \t\t\tfifo-size = <15>;\n@@ -223,7 +223,7 @@\n \n \t\tuart2: serial@21d0500 {\n \t\t\tcompatible = \"fsl,16550-FIFO64\", \"ns16550a\";\n-\t\t\treg = <0x0 0x21d0500 0x0 0x100>;\n+\t\t\treg = <0x21d0500 0x100>;\n \t\t\tinterrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tclock-frequency = <0>;\n \t\t\tfifo-size = <15>;\n@@ -232,7 +232,7 @@\n \n \t\tuart3: serial@21d0600 {\n \t\t\tcompatible = \"fsl,16550-FIFO64\", \"ns16550a\";\n-\t\t\treg = <0x0 0x21d0600 0x0 0x100>;\n+\t\t\treg = <0x21d0600 0x100>;\n \t\t\tinterrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tclock-frequency = <0>;\n \t\t\tfifo-size = <15>;\n@@ -241,7 +241,7 @@\n \n \t\tlpuart0: serial@2950000 {\n \t\t\tcompatible = \"fsl,ls1021a-lpuart\";\n-\t\t\treg = <0x0 0x2950000 0x0 0x1000>;\n+\t\t\treg = <0x2950000 0x1000>;\n \t\t\tinterrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tclocks = <&sysclk>;\n \t\t\tclock-names = \"ipg\";\n@@ -250,7 +250,7 @@\n \n \t\tlpuart1: serial@2960000 {\n \t\t\tcompatible = \"fsl,ls1021a-lpuart\";\n-\t\t\treg = <0x0 0x2960000 0x0 0x1000>;\n+\t\t\treg = <0x2960000 0x1000>;\n \t\t\tinterrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tclocks = <&platform_clk 1>;\n \t\t\tclock-names = \"ipg\";\n@@ -259,7 +259,7 @@\n \n \t\tlpuart2: serial@2970000 {\n \t\t\tcompatible = \"fsl,ls1021a-lpuart\";\n-\t\t\treg = <0x0 0x2970000 0x0 0x1000>;\n+\t\t\treg = <0x2970000 0x1000>;\n \t\t\tinterrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tclocks = <&platform_clk 1>;\n \t\t\tclock-names = \"ipg\";\n@@ -268,7 +268,7 @@\n \n \t\tlpuart3: serial@2980000 {\n \t\t\tcompatible = \"fsl,ls1021a-lpuart\";\n-\t\t\treg = <0x0 0x2980000 0x0 0x1000>;\n+\t\t\treg = <0x2980000 0x1000>;\n \t\t\tinterrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tclocks = <&platform_clk 1>;\n \t\t\tclock-names = \"ipg\";\n@@ -277,7 +277,7 @@\n \n \t\tlpuart4: serial@2990000 {\n \t\t\tcompatible = \"fsl,ls1021a-lpuart\";\n-\t\t\treg = <0x0 0x2990000 0x0 0x1000>;\n+\t\t\treg = <0x2990000 0x1000>;\n \t\t\tinterrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tclocks = <&platform_clk 1>;\n \t\t\tclock-names = \"ipg\";\n@@ -286,7 +286,7 @@\n \n \t\tlpuart5: serial@29a0000 {\n \t\t\tcompatible = \"fsl,ls1021a-lpuart\";\n-\t\t\treg = <0x0 0x29a0000 0x0 0x1000>;\n+\t\t\treg = <0x29a0000 0x1000>;\n \t\t\tinterrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tclocks = <&platform_clk 1>;\n \t\t\tclock-names = \"ipg\";\n@@ -295,7 +295,7 @@\n \n \t\twdog0: watchdog@2ad0000 {\n \t\t\tcompatible = \"fsl,imx21-wdt\";\n-\t\t\treg = <0x0 0x2ad0000 0x0 0x10000>;\n+\t\t\treg = <0x2ad0000 0x10000>;\n \t\t\tinterrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tclocks = <&platform_clk 1>;\n \t\t\tclock-names = \"wdog-en\";\n@@ -304,7 +304,7 @@\n \n \t\tsai1: sai@2b50000 {\n \t\t\tcompatible = \"fsl,vf610-sai\";\n-\t\t\treg = <0x0 0x2b50000 0x0 0x10000>;\n+\t\t\treg = <0x2b50000 0x10000>;\n \t\t\tinterrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tclocks = <&platform_clk 1>;\n \t\t\tclock-names = \"sai\";\n@@ -317,7 +317,7 @@\n \n \t\tsai2: sai@2b60000 {\n \t\t\tcompatible = \"fsl,vf610-sai\";\n-\t\t\treg = <0x0 0x2b60000 0x0 0x10000>;\n+\t\t\treg = <0x2b60000 0x10000>;\n \t\t\tinterrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tclocks = <&platform_clk 1>;\n \t\t\tclock-names = \"sai\";\n@@ -331,9 +331,9 @@\n \t\tedma0: edma@2c00000 {\n \t\t\t#dma-cells = <2>;\n \t\t\tcompatible = \"fsl,vf610-edma\";\n-\t\t\treg = <0x0 0x2c00000 0x0 0x10000>,\n-\t\t\t <0x0 0x2c10000 0x0 0x10000>,\n-\t\t\t <0x0 0x2c20000 0x0 0x10000>;\n+\t\t\treg = <0x2c00000 0x10000>,\n+\t\t\t <0x2c10000 0x10000>,\n+\t\t\t <0x2c20000 0x10000>;\n \t\t\tinterrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,\n \t\t\t\t <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tinterrupt-names = \"edma-tx\", \"edma-err\";\n@@ -349,12 +349,12 @@\n \t\t\tdevice_type = \"mdio\";\n \t\t\t#address-cells = <1>;\n \t\t\t#size-cells = <0>;\n-\t\t\treg = <0x0 0x2d24000 0x0 0x4000>;\n+\t\t\treg = <0x2d24000 0x4000>;\n \t\t};\n \n \t\tusb@8600000 {\n \t\t\tcompatible = \"fsl-usb2-dr-v2.5\", \"fsl-usb2-dr\";\n-\t\t\treg = <0x0 0x8600000 0x0 0x1000>;\n+\t\t\treg = <0x8600000 0x1000>;\n \t\t\tinterrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tdr_mode = \"host\";\n \t\t\tphy_type = \"ulpi\";\n@@ -362,7 +362,7 @@\n \n \t\tusb3@3100000 {\n \t\t\tcompatible = \"snps,dwc3\";\n-\t\t\treg = <0x0 0x3100000 0x0 0x10000>;\n+\t\t\treg = <0x3100000 0x10000>;\n \t\t\tinterrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tdr_mode = \"host\";\n \t\t};\n", "prefixes": [ "U-Boot", "3/5", "v1" ] }