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GET /api/patches/434834/?format=api
{ "id": 434834, "url": "http://patchwork.ozlabs.org/api/patches/434834/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/patch/1422620541-6843-4-git-send-email-chenhui.zhao@freescale.com/", "project": { "id": 19, "url": "http://patchwork.ozlabs.org/api/projects/19/?format=api", "name": "Linux IMX development", "link_name": "linux-imx", "list_id": "linux-imx-kernel.lists.patchwork.ozlabs.org", "list_email": "linux-imx-kernel@lists.patchwork.ozlabs.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1422620541-6843-4-git-send-email-chenhui.zhao@freescale.com>", "list_archive_url": null, "date": "2015-01-30T12:22:21", "name": "[4/4] arm: ls1021a: set wakeup devices dynamically for sleep/deep sleep", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "897c5278c1989568d7c6e1f36e971e3c470bef43", "submitter": { "id": 8974, "url": "http://patchwork.ozlabs.org/api/people/8974/?format=api", "name": "chenhui zhao", "email": "chenhui.zhao@freescale.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-imx/patch/1422620541-6843-4-git-send-email-chenhui.zhao@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/434834/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/434834/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming-imx@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-imx@bilbo.ozlabs.org", "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n\t[IPv6:2001:1868:205::9])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4D34C1402AE\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tFri, 30 Jan 2015 23:25:19 +1100 (AEDT)", "from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux))\n\tid 1YHAbY-0002ch-Pf; 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Fri, 30 Jan 2015 05:22:24 -0700" ], "From": "Chenhui Zhao <chenhui.zhao@freescale.com>", "To": "<linux-kernel@vger.kernel.org>, <kernel@pengutronix.de>,\n\t<linux-arm-kernel@lists.infradead.org>", "Subject": "[PATCH 4/4] arm: ls1021a: set wakeup devices dynamically for\n\tsleep/deep sleep", "Date": "Fri, 30 Jan 2015 20:22:21 +0800", "Message-ID": "<1422620541-6843-4-git-send-email-chenhui.zhao@freescale.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1422620541-6843-1-git-send-email-chenhui.zhao@freescale.com>", "References": "<1422620541-6843-1-git-send-email-chenhui.zhao@freescale.com>", "X-EOPAttributedMessage": "0", "Received-SPF": "Fail (protection.outlook.com: domain of freescale.com does not\n\tdesignate 192.88.158.2 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.158.2; helo=az84smr01.freescale.net;", "Authentication-Results": "spf=fail (sender IP is 192.88.158.2)\n\tsmtp.mailfrom=chenhui.zhao@freescale.com;\n\tfreescale.mail.onmicrosoft.com; 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charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>", "Errors-To": "linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org", "List-Id": "linux-imx-kernel.lists.patchwork.ozlabs.org" }, "content": "If a device works as a wakeup source, it will keep working in the period of\nsleep/deep sleep. This patch sets the wakeup devices according to the wakeup\nattribute of device.\n\nSigned-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>\n---\n arch/arm/boot/dts/ls1021a.dtsi | 2 +\n arch/arm/mach-imx/pm-ls1.c | 101 +++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 103 insertions(+)", "diff": "diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi\nindex 0c51ce0..64534c0 100644\n--- a/arch/arm/boot/dts/ls1021a.dtsi\n+++ b/arch/arm/boot/dts/ls1021a.dtsi\n@@ -136,6 +136,7 @@\n \t\t\tsdhci,auto-cmd12;\n \t\t\tbig-endian;\n \t\t\tbus-width = <4>;\n+\t\t\tsleep = <&rcpm 0x00000080 0x0>;\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n@@ -289,6 +290,7 @@\n \t\t\tinterrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\tclocks = <&sysclk>;\n \t\t\tclock-names = \"ipg\";\n+\t\t\tsleep = <&rcpm 0x0 0x40000000>;\n \t\t\tstatus = \"disabled\";\n \t\t};\n \ndiff --git a/arch/arm/mach-imx/pm-ls1.c b/arch/arm/mach-imx/pm-ls1.c\nindex 4f9ca80..b11fcb2 100644\n--- a/arch/arm/mach-imx/pm-ls1.c\n+++ b/arch/arm/mach-imx/pm-ls1.c\n@@ -35,6 +35,13 @@\n #define CCSR_SCFG_DPSLPCR\t0\n #define CCSR_SCFG_DPSLPCR_VAL\t0x1\n #define CCSR_SCFG_PMCINTECR\t0x160\n+#define CCSR_SCFG_PMCINTECR_LPUART\t0x40000000\n+#define CCSR_SCFG_PMCINTECR_FTM\t\t0x20000000\n+#define CCSR_SCFG_PMCINTECR_GPIO\t0x10000000\n+#define CCSR_SCFG_PMCINTECR_IRQ0\t0x08000000\n+#define CCSR_SCFG_PMCINTECR_IRQ1\t0x04000000\n+#define CCSR_SCFG_PMCINTECR_ETSECRXG0\t0x00800000\n+#define CCSR_SCFG_PMCINTECR_ETSECRXG1\t0x00400000\n #define CCSR_SCFG_PMCINTLECR\t0x164\n #define CCSR_SCFG_PMCINTSR\t0x168\n #define CCSR_SCFG_SPARECR2\t0x504\n@@ -50,7 +57,11 @@\n #define CCSR_RCPM_CLPCL10SETR\t\t0x1c4\n #define CCSR_RCPM_CLPCL10SETR_C0\t0x1\n #define CCSR_RCPM_IPPDEXPCR0\t\t0x140\n+#define CCSR_RCPM_IPPDEXPCR0_ETSEC\t0x80000000\n+#define CCSR_RCPM_IPPDEXPCR0_GPIO\t0x00000040\n #define CCSR_RCPM_IPPDEXPCR1\t\t0x144\n+#define CCSR_RCPM_IPPDEXPCR1_LPUART\t0x40000000\n+#define CCSR_RCPM_IPPDEXPCR1_FLEXTIMER\t0x20000000\n \n #define QIXIS_CTL_SYS\t\t\t0x5\n #define QIXIS_CTL_SYS_EVTSW_MASK\t0x0c\n@@ -64,6 +75,10 @@\n /* use the last page of SRAM */\n #define SRAM_CODE_BASE_PHY\t(OCRAM_BASE + OCRAM_SIZE - PAGE_SIZE)\n \n+#define SLEEP_ARRAY_SIZE\t3\n+\n+static u32 ippdexpcr0, ippdexpcr1;\n+\n struct ls1_pm_baseaddr {\n \tvoid __iomem *rcpm;\n \tvoid __iomem *epu;\n@@ -242,6 +257,49 @@ static void ls1_board_resume(void)\n \tiowrite8(tmp, ls1_pm_base.fpga + QIXIS_CTL_SYS);\n }\n \n+static void ls1_setup_pmc_int(void)\n+{\n+\tu32 pmcintecr;\n+\n+\tpmcintecr = 0;\n+\tif (ippdexpcr0 & CCSR_RCPM_IPPDEXPCR0_ETSEC)\n+\t\tpmcintecr |= CCSR_SCFG_PMCINTECR_ETSECRXG0 |\n+\t\t\t\tCCSR_SCFG_PMCINTECR_ETSECRXG1;\n+\n+\tif (ippdexpcr0 & CCSR_RCPM_IPPDEXPCR0_GPIO)\n+\t\tpmcintecr |= CCSR_SCFG_PMCINTECR_GPIO;\n+\n+\tif (ippdexpcr1 & CCSR_RCPM_IPPDEXPCR1_LPUART)\n+\t\tpmcintecr |= CCSR_SCFG_PMCINTECR_LPUART;\n+\n+\tif (ippdexpcr1 & CCSR_RCPM_IPPDEXPCR1_FLEXTIMER)\n+\t\tpmcintecr |= CCSR_SCFG_PMCINTECR_FTM;\n+\n+\t/* always set external IRQ pins as wakeup source */\n+\tpmcintecr |= CCSR_SCFG_PMCINTECR_IRQ0 | CCSR_SCFG_PMCINTECR_IRQ1;\n+\n+\t/* enable wakeup interrupt during deep sleep */\n+\tiowrite32be(pmcintecr, ls1_pm_base.scfg + CCSR_SCFG_PMCINTECR);\n+\tiowrite32be(0, ls1_pm_base.scfg + CCSR_SCFG_PMCINTLECR);\n+\t/* clear PMC interrupt status */\n+\tiowrite32be(0xffffffff, ls1_pm_base.scfg + CCSR_SCFG_PMCINTSR);\n+}\n+\n+static void ls1_clear_pmc_int(void)\n+{\n+\t/* disable wakeup interrupt during deep sleep */\n+\tiowrite32be(0, ls1_pm_base.scfg + CCSR_SCFG_PMCINTECR);\n+\t/* clear PMC interrupt status */\n+\tiowrite32be(0xffffffff, ls1_pm_base.scfg + CCSR_SCFG_PMCINTSR);\n+}\n+\n+/* set IP powerdown exception, make them work during sleep/deep sleep */\n+static void ls1_set_powerdown(void)\n+{\n+\tiowrite32be(ippdexpcr0, ls1_pm_base.rcpm + CCSR_RCPM_IPPDEXPCR0);\n+\tiowrite32be(ippdexpcr1, ls1_pm_base.rcpm + CCSR_RCPM_IPPDEXPCR1);\n+}\n+\n static void ls1_enter_deepsleep(void)\n {\n \t/* save DDR data */\n@@ -265,8 +323,12 @@ static void ls1_enter_deepsleep(void)\n \t/* copy the last stage code to sram */\n \tls1_copy_sram_code();\n \n+\tls1_setup_pmc_int();\n+\n \tcpu_suspend(SRAM_CODE_BASE_PHY, ls1_start_deepsleep);\n \n+\tls1_clear_pmc_int();\n+\n \t/* disable Warm Device Reset */\n \tls1_clrsetbits_be32(ls1_pm_base.scfg + CCSR_SCFG_DPSLPCR,\n \t\t\t CCSR_SCFG_DPSLPCR_VAL, 0);\n@@ -274,10 +336,45 @@ static void ls1_enter_deepsleep(void)\n \tls1_board_resume();\n }\n \n+static void ls1_set_power_except(struct device *dev, int on)\n+{\n+\tint ret;\n+\tu32 value[SLEEP_ARRAY_SIZE];\n+\n+\t/*\n+\t * Get the values in the \"sleep\" property. There are three values.\n+\t * The first points to the RCPM node, the second is the value of\n+\t * the ippdexpcr0 register, and the third is the value of\n+\t * the ippdexpcr1 register.\n+\t */\n+\tret = of_property_read_u32_array(dev->of_node, \"sleep\",\n+\t\t\t\t\t\tvalue, SLEEP_ARRAY_SIZE);\n+\tif (ret) {\n+\t\tdev_err(dev, \"%s: Can not find the \\\"sleep\\\" property.\\n\",\n+\t\t\t__func__);\n+\t\treturn;\n+\t}\n+\n+\tippdexpcr0 |= value[1];\n+\tippdexpcr1 |= value[2];\n+\n+\tpr_debug(\"%s: set %s as a wakeup source\", __func__,\n+\t\t dev->of_node->full_name);\n+}\n+\n+static void ls1_set_wakeup_device(struct device *dev, void *enable)\n+{\n+\t/* set each device which can act as wakeup source */\n+\tif (device_may_wakeup(dev))\n+\t\tls1_set_power_except(dev, *((int *)enable));\n+}\n+\n static int ls1_suspend_enter(suspend_state_t state)\n {\n \tint ret = 0;\n \n+\tls1_set_powerdown();\n+\n \tswitch (state) {\n \tcase PM_SUSPEND_STANDBY:\n \t\tflush_cache_louis();\n@@ -316,6 +413,10 @@ static int ls1_suspend_begin(suspend_state_t state)\n \n \tls1_pm_state = state;\n \n+\tippdexpcr0 = 0;\n+\tippdexpcr1 = 0;\n+\tdpm_for_each_dev(NULL, ls1_set_wakeup_device);\n+\n \tif (ls1_pm_state == PM_SUSPEND_MEM)\n \t\tret = ls1_pm_iomap();\n \n", "prefixes": [ "4/4" ] }