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GET /api/patches/434833/?format=api
{ "id": 434833, "url": "http://patchwork.ozlabs.org/api/patches/434833/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/patch/1422620541-6843-3-git-send-email-chenhui.zhao@freescale.com/", "project": { "id": 19, "url": "http://patchwork.ozlabs.org/api/projects/19/?format=api", "name": "Linux IMX development", "link_name": "linux-imx", "list_id": "linux-imx-kernel.lists.patchwork.ozlabs.org", "list_email": "linux-imx-kernel@lists.patchwork.ozlabs.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1422620541-6843-3-git-send-email-chenhui.zhao@freescale.com>", "list_archive_url": null, "date": "2015-01-30T12:22:20", "name": "[3/4] arm: ls1021a: add deep sleep support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7521041b87e9e8d3446ae1c9a2bcd2027d117f25", "submitter": { "id": 8974, "url": "http://patchwork.ozlabs.org/api/people/8974/?format=api", "name": "chenhui zhao", "email": "chenhui.zhao@freescale.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-imx/patch/1422620541-6843-3-git-send-email-chenhui.zhao@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/434833/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/434833/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming-imx@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-imx@bilbo.ozlabs.org", "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n\t[IPv6:2001:1868:205::9])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id A4C4D1402AE\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tFri, 30 Jan 2015 23:25:17 +1100 (AEDT)", "from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux))\n\tid 1YHAbK-0002WW-RF; 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Fri, 30 Jan 2015 05:22:21 -0700" ], "From": "Chenhui Zhao <chenhui.zhao@freescale.com>", "To": "<linux-kernel@vger.kernel.org>, <kernel@pengutronix.de>,\n\t<linux-arm-kernel@lists.infradead.org>", "Subject": "[PATCH 3/4] arm: ls1021a: add deep sleep support", "Date": "Fri, 30 Jan 2015 20:22:20 +0800", "Message-ID": "<1422620541-6843-3-git-send-email-chenhui.zhao@freescale.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1422620541-6843-1-git-send-email-chenhui.zhao@freescale.com>", "References": "<1422620541-6843-1-git-send-email-chenhui.zhao@freescale.com>", "X-EOPAttributedMessage": "0", "Received-SPF": "Fail (protection.outlook.com: domain of freescale.com does not\n\tdesignate 192.88.158.2 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.158.2; helo=az84smr01.freescale.net;", "Authentication-Results": "spf=fail (sender IP is 192.88.158.2)\n\tsmtp.mailfrom=chenhui.zhao@freescale.com;\n\tfreescale.mail.onmicrosoft.com; \n\tdkim=none (message not signed) header.d=none;\n\tfreescale.mail.onmicrosoft.com; \n\tdmarc=permerror action=none header.from=freescale.com;", "X-Forefront-Antispam-Report": "CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI;\n\tSFV:NSPM;\n\tSFS:(10019020)(6009001)(87936001)(105606002)(49486002)(85426001)(50226001)(86362001)(229853001)(575784001)(106466001)(104016003)(6806004)(19580405001)(77156002)(19580395003)(33646002)(62966003)(47776003)(2201001)(92566002)(50466002)(76176999)(50986999)(46102003)(36756003)(77096005)(48376002)(2950100001)(2004002);\n\tDIR:OUT; SFP:1102; SCL:1; SRVR:BN3PR0301MB1284;\n\tH:az84smr01.freescale.net; \n\tFPR:; SPF:None; MLV:sfv; LANG:en; ", "MIME-Version": "1.0", "X-DmarcAction-Test": "None", "X-Microsoft-Antispam": [ "UriScan:;", "BCL:0;PCL:0;RULEID:(3005004);SRVR:BN3PR0301MB1284;" ], "X-Exchange-Antispam-Report-Test": "UriScan:;", "X-Exchange-Antispam-Report-CFA-Test": [ "BCL:0; PCL:0; RULEID:(601004);\n\tSRVR:BN3PR0301MB1284; ", "BCL:0; PCL:0; RULEID:;\n\tSRVR:BN3PR0301MB1284; " ], "X-Forefront-PRVS": "04724A515E", "X-OriginatorOrg": "freescale.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Jan 2015 12:22:24.4009\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "710a03f5-10f6-4d38-9ff4-a80b81da590d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d;\n\tIp=[192.88.158.2]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN3PR0301MB1284", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20150130_042248_754025_C947FF9D ", "X-CRM114-Status": "GOOD ( 19.83 )", "X-Spam-Score": "-0.0 (/)", "X-Spam-Report": "SpamAssassin version 3.4.0 on bombadil.infradead.org summary:\n\tContent analysis details: (-0.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [157.56.111.133 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 SPF_HELO_PASS SPF: HELO matches SPF record\n\t-0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2)\n\t[157.56.111.133 listed in wl.mailspike.net]", "Cc": "leoli@freescale.com, Jason.Jin@freescale.com", "X-BeenThere": "linux-arm-kernel@lists.infradead.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-arm-kernel/>", "List-Post": "<mailto:linux-arm-kernel@lists.infradead.org>", "List-Help": "<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>", "Errors-To": "linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org", "List-Id": "linux-imx-kernel.lists.patchwork.ozlabs.org" }, "content": "The ls1021a SoC supports deep sleep feature that can switch off most\nparts of the SoC when it is in deep sleep state.\n\nThe DDR controller will also be powered off in deep sleep. Therefore,\ncopy the last stage code to enter deep sleep to SRAM and run it\nwith disabling MMU and caches.\n\nSigned-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>\n---\n arch/arm/mach-imx/Kconfig | 1 +\n arch/arm/mach-imx/Makefile | 2 +\n arch/arm/mach-imx/pm-ls1.c | 374 ++++++++++++++++++++++++++++++++++++++++++\n arch/arm/mach-imx/sleep-ls1.S | 137 ++++++++++++++++\n arch/arm/mach-imx/sleep-ls1.h | 19 +++\n 5 files changed, 533 insertions(+)\n create mode 100644 arch/arm/mach-imx/pm-ls1.c\n create mode 100644 arch/arm/mach-imx/sleep-ls1.S\n create mode 100644 arch/arm/mach-imx/sleep-ls1.h", "diff": "diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig\nindex e8627e0..c10acff 100644\n--- a/arch/arm/mach-imx/Kconfig\n+++ b/arch/arm/mach-imx/Kconfig\n@@ -664,6 +664,7 @@ config SOC_LS1021A\n \tselect HAVE_ARM_ARCH_TIMER\n \tselect PCI_DOMAINS if PCI\n \tselect ZONE_DMA if ARM_LPAE\n+\tselect FSL_SLEEP_FSM if PM\n \n \thelp\n \t This enable support for Freescale LS1021A processor.\ndiff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile\nindex f5ac685..358adf4 100644\n--- a/arch/arm/mach-imx/Makefile\n+++ b/arch/arm/mach-imx/Makefile\n@@ -101,6 +101,8 @@ obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o mach-imx6sx.o\n ifeq ($(CONFIG_SUSPEND),y)\n AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a\n obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o\n+AFLAGS_sleep-ls1.o :=-Wa,-march=armv7-a\n+obj-$(CONFIG_SOC_LS1021A) += pm-ls1.o sleep-ls1.o\n endif\n obj-$(CONFIG_SOC_IMX6) += pm-imx6.o\n \ndiff --git a/arch/arm/mach-imx/pm-ls1.c b/arch/arm/mach-imx/pm-ls1.c\nnew file mode 100644\nindex 0000000..4f9ca80\n--- /dev/null\n+++ b/arch/arm/mach-imx/pm-ls1.c\n@@ -0,0 +1,374 @@\n+/*\n+ * Support deep sleep feature for LS1\n+ *\n+ * Copyright 2014-2015 Freescale Semiconductor Inc.\n+ *\n+ * This program is free software; you can redistribute\tit and/or modify it\n+ * under the terms of\tthe GNU General\t Public License as published by the\n+ * Free Software Foundation; either version 2 of the License, or (at your\n+ * option) any later version.\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/suspend.h>\n+#include <linux/io.h>\n+#include <linux/of_platform.h>\n+#include <linux/of_address.h>\n+#include <linux/cpu_pm.h>\n+#include <asm/suspend.h>\n+#include <asm/delay.h>\n+#include <asm/cp15.h>\n+#include <asm/cacheflush.h>\n+#include <asm/idmap.h>\n+\n+#include \"common.h\"\n+#include \"sleep-ls1.h\"\n+\n+#define FSL_SLEEP\t\t0x1\n+#define FSL_DEEP_SLEEP\t\t0x2\n+\n+#define DCSR_EPU_EPSMCR15\t0x278\n+#define DCSR_EPU_EPECR0\t\t0x300\n+#define DCSR_RCPM_CG1CR0\t0x31c\n+#define DCSR_RCPM_CSTTACR0\t0xb00\n+\n+#define CCSR_SCFG_DPSLPCR\t0\n+#define CCSR_SCFG_DPSLPCR_VAL\t0x1\n+#define CCSR_SCFG_PMCINTECR\t0x160\n+#define CCSR_SCFG_PMCINTLECR\t0x164\n+#define CCSR_SCFG_PMCINTSR\t0x168\n+#define CCSR_SCFG_SPARECR2\t0x504\n+#define CCSR_SCFG_SPARECR3\t0x508\n+\n+#define CCSR_DCFG_CRSTSR\t0x400\n+#define CCSR_DCFG_CRSTSR_VAL\t0x00000008\n+\n+#define CCSR_RCPM_POWMGTCSR\t\t0x130\n+#define CCSR_RCPM_POWMGTCSR_LPM20_REQ\t0x00100000\n+#define CCSR_RCPM_POWMGTCSR_LPM20_ST\t0x00000200\n+#define CCSR_RCPM_POWMGTCSR_P_LPM20_ST\t0x00000100\n+#define CCSR_RCPM_CLPCL10SETR\t\t0x1c4\n+#define CCSR_RCPM_CLPCL10SETR_C0\t0x1\n+#define CCSR_RCPM_IPPDEXPCR0\t\t0x140\n+#define CCSR_RCPM_IPPDEXPCR1\t\t0x144\n+\n+#define QIXIS_CTL_SYS\t\t\t0x5\n+#define QIXIS_CTL_SYS_EVTSW_MASK\t0x0c\n+#define QIXIS_CTL_SYS_EVTSW_IRQ\t\t0x04\n+\n+#define QIXIS_PWR_CTL2\t\t0x21\n+#define QIXIS_PWR_CTL2_PCTL\t0x2\n+\n+#define OCRAM_BASE\t0x10000000\n+#define OCRAM_SIZE\t0x10000\t\t/* 64K */\n+/* use the last page of SRAM */\n+#define SRAM_CODE_BASE_PHY\t(OCRAM_BASE + OCRAM_SIZE - PAGE_SIZE)\n+\n+struct ls1_pm_baseaddr {\n+\tvoid __iomem *rcpm;\n+\tvoid __iomem *epu;\n+\tvoid __iomem *dcsr_rcpm1;\n+\tvoid __iomem *scfg;\n+\tvoid __iomem *dcfg;\n+\tvoid __iomem *fpga;\n+\tvoid __iomem *sram;\n+};\n+\n+/* 128 bytes buffer for restoring data broke by DDR training initialization */\n+#define DDR_BUF_SIZE\t128\n+static u8 ddr_buff[DDR_BUF_SIZE] __aligned(64);\n+static struct ls1_pm_baseaddr ls1_pm_base;\n+/* supported sleep modes by the present platform */\n+static unsigned int sleep_modes;\n+static suspend_state_t ls1_pm_state;\n+\n+static inline void ls1_clrsetbits_be32(void __iomem *addr, u32 mask, u32 val)\n+{\n+\tu32 tmp;\n+\n+\ttmp = ioread32be(addr);\n+\ttmp = (tmp & ~mask) | val;\n+\tiowrite32be(tmp, addr);\n+}\n+\n+static void __iomem *of_iomap_str(const char *compatible)\n+{\n+\tstruct device_node *np;\n+\tvoid __iomem *base;\n+\n+\tnp = of_find_compatible_node(NULL, NULL, compatible);\n+\tif (!np) {\n+\t\tpr_err(\"%s: can not find the compatible \\\"%s\\\"\\n\",\n+\t\t\t__func__, compatible);\n+\t\treturn NULL;\n+\t}\n+\n+\tbase = of_iomap(np, 0);\n+\tof_node_put(np);\n+\tif (!base)\n+\t\treturn NULL;\n+\n+\treturn base;\n+}\n+\n+static int ls1_pm_iomap(void)\n+{\n+\tls1_pm_base.epu = of_iomap_str(\"fsl,ls1021a-dcsr-epu\");\n+\tls1_pm_base.scfg = of_iomap_str(\"fsl,ls1021a-scfg\");\n+\tls1_pm_base.dcfg = of_iomap_str(\"fsl,ls1021a-dcfg\");\n+\tls1_pm_base.fpga = of_iomap_str(\"fsl,ls1021aqds-fpga\");\n+\tls1_pm_base.dcsr_rcpm1 = of_iomap_str(\"fsl,ls1021a-dcsr-rcpm\");\n+\tls1_pm_base.sram = ioremap(SRAM_CODE_BASE_PHY, PAGE_SIZE);\n+\tif (!ls1_pm_base.epu || !ls1_pm_base.scfg || !ls1_pm_base.dcfg ||\n+\t !ls1_pm_base.fpga || !ls1_pm_base.dcsr_rcpm1 || !ls1_pm_base.sram)\n+\t\treturn -ENOMEM;\n+\n+\treturn 0;\n+}\n+\n+static void ls1_pm_uniomap(void)\n+{\n+\tiounmap(ls1_pm_base.epu);\n+\tiounmap(ls1_pm_base.dcsr_rcpm1);\n+\tiounmap(ls1_pm_base.scfg);\n+\tiounmap(ls1_pm_base.dcfg);\n+\tiounmap(ls1_pm_base.sram);\n+\tiounmap(ls1_pm_base.fpga);\n+}\n+\n+static void ls1_save_ddr(void __iomem *base)\n+{\n+\tu32 ddr_buff_addr;\n+\n+\t/*\n+\t * DDR training initialization will break 128 bytes at the beginning\n+\t * of DDR, therefore, save them so that the bootloader will restore\n+\t * them. Assume that DDR is mapped to the address space started with\n+\t * CONFIG_PAGE_OFFSET.\n+\t */\n+\tmemcpy(ddr_buff, (void *)CONFIG_PAGE_OFFSET, DDR_BUF_SIZE);\n+\n+\tddr_buff_addr = (u32)__pa(ddr_buff);\n+\n+\t/*\n+\t * the bootloader will restore the first 128 bytes of DDR from\n+\t * the location indicated by the register SPARECR3\n+\t */\n+\tiowrite32(ddr_buff_addr, base + CCSR_SCFG_SPARECR3);\n+}\n+\n+static void ls1_set_resume_entry(void __iomem *base)\n+{\n+\tu32 resume_addr;\n+\n+\t/* the bootloader will finally jump to this address to resume kernel */\n+\tresume_addr = (u32)(__pa(ls1_deepsleep_resume));\n+\n+\t/* use the register SPARECR2 to save the return entry */\n+\tiowrite32(resume_addr, base + CCSR_SCFG_SPARECR2);\n+}\n+\n+static void ls1_copy_sram_code(void)\n+{\n+\tmemcpy(ls1_pm_base.sram, ls1_start_fsm, ls1_sram_code_size);\n+}\n+\n+static int ls1_start_deepsleep(unsigned long addr)\n+{\n+\t/* Switch to the identity mapping */\n+\tsetup_mm_for_reboot();\n+\tv7_exit_coherency_flush(all);\n+\n+\tls1_do_deepsleep(addr);\n+\n+\t/* never get here */\n+\tBUG();\n+\n+\treturn 0;\n+}\n+\n+static void ls1_fsm_setup(void)\n+{\n+\t/* Request to put cluster 0 in PCL10 state */\n+\tls1_clrsetbits_be32(ls1_pm_base.rcpm + CCSR_RCPM_CLPCL10SETR,\n+\t\t\t CCSR_RCPM_CLPCL10SETR_C0,\n+\t\t\t CCSR_RCPM_CLPCL10SETR_C0);\n+\n+\tiowrite32be(0x00001001, ls1_pm_base.dcsr_rcpm1 + DCSR_RCPM_CSTTACR0);\n+\tiowrite32be(0x00000001, ls1_pm_base.dcsr_rcpm1 + DCSR_RCPM_CG1CR0);\n+\n+\tfsl_epu_setup(ls1_pm_base.epu);\n+\n+\t/*\n+\t * pull the MCKE signal(EVT4_B pin) low before enabling\n+\t * deep sleep signals by FPGA\n+\t */\n+\tiowrite32be(0x5, ls1_pm_base.epu + DCSR_EPU_EPECR0);\n+\n+\tiowrite32be(0x76300000, ls1_pm_base.epu + DCSR_EPU_EPSMCR15);\n+}\n+\n+static void ls1_board_suspend(void)\n+{\n+\tu32 tmp;\n+\n+\t/* connect the EVENT button to IRQ in FPGA */\n+\ttmp = ioread8(ls1_pm_base.fpga + QIXIS_CTL_SYS);\n+\ttmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;\n+\ttmp |= QIXIS_CTL_SYS_EVTSW_IRQ;\n+\tiowrite8(tmp, ls1_pm_base.fpga + QIXIS_CTL_SYS);\n+\n+\t/*\n+\t * enable deep sleep signals in FPGA\n+\t * Note that the MCKE signal(EVT4_B pin) should be pulled low (invalid)\n+\t * before enabling deep sleep signals.\n+\t */\n+\ttmp = ioread8(ls1_pm_base.fpga + QIXIS_PWR_CTL2);\n+\tiowrite8(tmp | QIXIS_PWR_CTL2_PCTL,\n+\t\t\tls1_pm_base.fpga + QIXIS_PWR_CTL2);\n+}\n+\n+static void ls1_board_resume(void)\n+{\n+\tu32 tmp;\n+\n+\t/* disable deep sleep signals in FPGA */\n+\ttmp = ioread8(ls1_pm_base.fpga + QIXIS_PWR_CTL2);\n+\tiowrite8(tmp & ~QIXIS_PWR_CTL2_PCTL,\n+\t\t\tls1_pm_base.fpga + QIXIS_PWR_CTL2);\n+\n+\ttmp = ioread8(ls1_pm_base.fpga + QIXIS_CTL_SYS);\n+\ttmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;\n+\tiowrite8(tmp, ls1_pm_base.fpga + QIXIS_CTL_SYS);\n+}\n+\n+static void ls1_enter_deepsleep(void)\n+{\n+\t/* save DDR data */\n+\tls1_save_ddr(ls1_pm_base.scfg);\n+\n+\t/* save kernel resume entry */\n+\tls1_set_resume_entry(ls1_pm_base.scfg);\n+\n+\t/* setup the registers of the EPU FSM for deep sleep */\n+\tls1_fsm_setup();\n+\n+\tls1_board_suspend();\n+\n+\t/* enable Warm Device Reset */\n+\tls1_clrsetbits_be32(ls1_pm_base.scfg + CCSR_SCFG_DPSLPCR,\n+\t\t\t CCSR_SCFG_DPSLPCR_VAL, CCSR_SCFG_DPSLPCR_VAL);\n+\n+\tls1_clrsetbits_be32(ls1_pm_base.dcfg + CCSR_DCFG_CRSTSR,\n+\t\t\t CCSR_DCFG_CRSTSR_VAL, CCSR_DCFG_CRSTSR_VAL);\n+\n+\t/* copy the last stage code to sram */\n+\tls1_copy_sram_code();\n+\n+\tcpu_suspend(SRAM_CODE_BASE_PHY, ls1_start_deepsleep);\n+\n+\t/* disable Warm Device Reset */\n+\tls1_clrsetbits_be32(ls1_pm_base.scfg + CCSR_SCFG_DPSLPCR,\n+\t\t\t CCSR_SCFG_DPSLPCR_VAL, 0);\n+\n+\tls1_board_resume();\n+}\n+\n+static int ls1_suspend_enter(suspend_state_t state)\n+{\n+\tint ret = 0;\n+\n+\tswitch (state) {\n+\tcase PM_SUSPEND_STANDBY:\n+\t\tflush_cache_louis();\n+\t\tls1_clrsetbits_be32(ls1_pm_base.rcpm + CCSR_RCPM_POWMGTCSR,\n+\t\t\t\t CCSR_RCPM_POWMGTCSR_LPM20_REQ,\n+\t\t\t\t CCSR_RCPM_POWMGTCSR_LPM20_REQ);\n+\n+\t\tcpu_do_idle();\n+\t\tbreak;\n+\n+\tcase PM_SUSPEND_MEM:\n+\t\tls1_enter_deepsleep();\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tret = -EINVAL;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int ls1_suspend_valid(suspend_state_t state)\n+{\n+\tif ((state == PM_SUSPEND_STANDBY) && (sleep_modes & FSL_SLEEP))\n+\t\treturn 1;\n+\n+\tif ((state == PM_SUSPEND_MEM) && (sleep_modes & FSL_DEEP_SLEEP))\n+\t\treturn 1;\n+\n+\treturn 0;\n+}\n+\n+static int ls1_suspend_begin(suspend_state_t state)\n+{\n+\tint ret = 0;\n+\n+\tls1_pm_state = state;\n+\n+\tif (ls1_pm_state == PM_SUSPEND_MEM)\n+\t\tret = ls1_pm_iomap();\n+\n+\treturn ret;\n+}\n+\n+static void ls1_suspend_end(void)\n+{\n+\tif (ls1_pm_state == PM_SUSPEND_MEM)\n+\t\tls1_pm_uniomap();\n+}\n+\n+static const struct platform_suspend_ops ls1_suspend_ops = {\n+\t.valid = ls1_suspend_valid,\n+\t.enter = ls1_suspend_enter,\n+\t.begin = ls1_suspend_begin,\n+\t.end = ls1_suspend_end,\n+};\n+\n+static const struct of_device_id rcpm_matches[] = {\n+\t{ .compatible = \"fsl,ls1021a-rcpm\", },\n+\t{}\n+};\n+\n+static int __init ls1_pm_init(void)\n+{\n+\tstruct device_node *np;\n+\tstruct property *prop;\n+\tvoid __iomem *base;\n+\n+\tnp = of_find_matching_node_and_match(NULL, rcpm_matches, NULL);\n+\tif (!np) {\n+\t\tpr_err(\"%s: can't find the RCPM node.\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tsleep_modes = FSL_SLEEP;\n+\tbase = of_iomap(np, 0);\n+\tif (!base) {\n+\t\tof_node_put(np);\n+\t\tpr_err(\"%s: failed to map the register set of RCPM node.\\n\",\n+\t\t\t__func__);\n+\t\treturn -ENOMEM;\n+\t}\n+\tls1_pm_base.rcpm = base;\n+\n+\tprop = of_find_property(np, \"fsl,deep-sleep\", NULL);\n+\tif (prop)\n+\t\tsleep_modes |= FSL_DEEP_SLEEP;\n+\tof_node_put(np);\n+\n+\tsuspend_set_ops(&ls1_suspend_ops);\n+\n+\treturn 0;\n+}\n+arch_initcall(ls1_pm_init);\ndiff --git a/arch/arm/mach-imx/sleep-ls1.S b/arch/arm/mach-imx/sleep-ls1.S\nnew file mode 100644\nindex 0000000..2020da6\n--- /dev/null\n+++ b/arch/arm/mach-imx/sleep-ls1.S\n@@ -0,0 +1,137 @@\n+/*\n+ * Support deep sleep feature for LS1\n+ *\n+ * Copyright 2014-2015 Freescale Semiconductor Inc.\n+ *\n+ * This program is free software; you can redistribute\tit and/or modify it\n+ * under the terms of\tthe GNU General\t Public License as published by the\n+ * Free Software Foundation; either version 2 of the License, or (at your\n+ * option) any later version.\n+ */\n+\n+#include <linux/linkage.h>\n+#include <asm/assembler.h>\n+#include <asm/cache.h>\n+#include <asm/cp15.h>\n+\n+#define CCSR_DDR_BASE\t\t\t0x01080000\n+#define CCSR_DDR_SDRAM_CFG_2\t\t0x114\n+\n+#define CCSR_SCFG_BASE\t\t\t0x01570000\n+#define CCSR_SCFG_HRSTCR\t\t0x1a8\n+\n+#define DCSR_EPU_BASE\t\t\t0x20000000\n+#define\tDCSR_EPU_EPGCR\t\t\t0x0\n+#define DCSR_EPU_EPECR0\t\t\t0x300\n+#define DCSR_EPU_EPECR15\t\t0x33c\n+\n+/* for big endian registers */\n+.macro ls1_set_bits, addr, value\n+\tldr\tr4, \\addr\n+\tldr\tr5, [r4]\n+\tldr\tr6, \\value\n+\trev\tr6, r6\n+\torr\tr5, r5, r6\n+\tstr\tr5, [r4]\n+.endm\n+\n+/* 1000 loops per round */\n+.macro ls1_delay, count\n+\tmov\tr0, \\count\n+11:\tmov\tr7, #1000\n+12:\tsubs\tr7, r7, #1\n+\tbne\t12b\n+\tsubs\tr0, r0, #1\n+\tbne\t11b\n+.endm\n+\n+/*\n+ * r0: the physical entry address of SRAM code\n+ */\n+\t.align L1_CACHE_SHIFT\n+\t.pushsection\t.idmap.text,\"ax\"\n+ENTRY(ls1_do_deepsleep)\n+\t/* disable MMU, M bit in SCTLR */\n+\tmrc\tp15, 0, r3, c1, c0, 0\n+\tbic\tr3, r3, #CR_M\n+\tmcr\tp15, 0, r3, c1, c0, 0\n+\tisb\n+\n+\t/* jump to the code in SRAM using physical address */\n+ THUMB( orr r0, r0, #1 )\n+\tbx\tr0\n+ENDPROC(ls1_do_deepsleep)\n+\t.popsection\n+\n+/*\n+ * The code will run in SRAM.\n+ */\n+\t.align L1_CACHE_SHIFT\n+ENTRY(ls1_start_fsm)\n+\t/* set HRSTCR */\n+\tls1_set_bits\tls1_ccsr_scfg_hrstcr_addr, ls1_ccsr_scfg_hrstcr_val\n+\n+\t/* Place DDR controller in self refresh mode */\n+\tls1_set_bits\tls1_ddr_cfg2_addr, ls1_ddr_cfg2_val\n+\n+\tls1_delay\t#2000\n+\n+\t/* Set EVT4_B to lock the signal MCKE down */\n+\tldr\tr4, ls1_dcsr_epu_epecr0\n+\tldr\tr5, ls1_dcsr_epu_epecr0_val\n+\trev\tr5, r5\n+\tstr\tr5, [r4]\n+\n+\tls1_delay\t#2000\n+\n+\t/* Enable all EPU Counters */\n+\tls1_set_bits\tls1_dcsr_epu_epgcr_addr, ls1_dcsr_epu_epgcr_val\n+\n+\t/* Set SCU15 */\n+\tldr\tr4, ls1_dcsr_epu_epecr15\n+\tldr\tr5, ls1_dcsr_epu_epecr15_val\n+\trev\tr5, r5\n+\tstr\tr5, [r4]\n+\n+\n+\t/* Enter WFI mode, and EPU FSM will start */\n+20:\twfi\n+\tb\t20b\n+\n+ls1_ccsr_scfg_hrstcr_addr:\n+\t.word\tCCSR_SCFG_BASE + CCSR_SCFG_HRSTCR\n+ls1_ccsr_scfg_hrstcr_val:\n+\t.word\t0x80000000\n+\n+ls1_ddr_cfg2_addr:\n+\t.word\tCCSR_DDR_BASE + CCSR_DDR_SDRAM_CFG_2\n+ls1_ddr_cfg2_val:\n+\t.word\t(1 << 31)\n+\n+ls1_dcsr_epu_epecr0:\n+\t.word\tDCSR_EPU_BASE + DCSR_EPU_EPECR0\n+ls1_dcsr_epu_epecr0_val:\n+\t.word\t0\n+\n+ls1_dcsr_epu_epgcr_addr:\n+\t.word\tDCSR_EPU_BASE + DCSR_EPU_EPGCR\n+ls1_dcsr_epu_epgcr_val:\n+\t.word\t0x80000000\n+\n+ls1_dcsr_epu_epecr15:\n+\t.word\tDCSR_EPU_BASE + DCSR_EPU_EPECR15\n+ls1_dcsr_epu_epecr15_val:\n+\t.word\t0x90000004\n+\n+ENTRY(ls1_sram_code_size)\n+\t.word\t. - ls1_start_fsm\n+\n+/* the bootloader will jump to here after wakeup from deep sleep */\n+\t.arm\n+\t.align L1_CACHE_SHIFT\n+ENTRY(ls1_deepsleep_resume)\n+ THUMB(\tadr\tr6, BSYM(1f)\t)\n+ THUMB(\tbx\tr6\t\t)\n+ THUMB(\t.thumb\t\t\t)\n+ THUMB(1:\t\t\t)\n+\tb cpu_resume\ndiff --git a/arch/arm/mach-imx/sleep-ls1.h b/arch/arm/mach-imx/sleep-ls1.h\nnew file mode 100644\nindex 0000000..2d694ac\n--- /dev/null\n+++ b/arch/arm/mach-imx/sleep-ls1.h\n@@ -0,0 +1,19 @@\n+/*\n+ * Copyright 2014-2015 Freescale Semiconductor, Inc.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ */\n+#ifndef __ARM_SLEEP_LS1_H\n+#define __ARM_SLEEP_LS1_H\n+\n+void ls1_do_deepsleep(unsigned long addr);\n+void ls1_start_fsm(void);\n+void ls1_deepsleep_resume(void);\n+void fsl_epu_setup(void __iomem *epu_base);\n+\n+extern int ls1_sram_code_size;\n+\n+#endif\n", "prefixes": [ "3/4" ] }