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GET /api/patches/428130/?format=api
{ "id": 428130, "url": "http://patchwork.ozlabs.org/api/patches/428130/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1421096205-27732-1-git-send-email-arnab_basu@rocketmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1421096205-27732-1-git-send-email-arnab_basu@rocketmail.com>", "list_archive_url": null, "date": "2015-01-12T20:56:45", "name": "[U-Boot,v2,6/9] ARMv8: PCSI: Add generic ARMv8 PSCI code", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "cb2c9aaeb4614e9950a918508183bb69d47a08c5", "submitter": { "id": 65465, "url": "http://patchwork.ozlabs.org/api/people/65465/?format=api", "name": "Arnab Basu", "email": "arnab_basu@rocketmail.com" }, "delegate": { "id": 1694, "url": "http://patchwork.ozlabs.org/api/users/1694/?format=api", "username": "aaribaud", "first_name": "Albert", "last_name": "ARIBAUD", "email": "albert.aribaud@free.fr" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1421096205-27732-1-git-send-email-arnab_basu@rocketmail.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/428130/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/428130/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id D8867140146\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 13 Jan 2015 08:02:25 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 505674B686;\n\tMon, 12 Jan 2015 22:01:58 +0100 (CET)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id F26IxaSaAvFS; Mon, 12 Jan 2015 22:01:58 +0100 (CET)", "from theia.denx.de (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id DEA0C4B688;\n\tMon, 12 Jan 2015 22:01:32 +0100 (CET)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id F27C54B608\n\tfor <u-boot@lists.denx.de>; Mon, 12 Jan 2015 22:00:23 +0100 (CET)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 7jw4yMhGRNCk for <u-boot@lists.denx.de>;\n\tMon, 12 Jan 2015 22:00:23 +0100 (CET)", "from nm42-vm7.bullet.mail.ne1.yahoo.com\n\t(nm42-vm7.bullet.mail.ne1.yahoo.com [98.138.121.63])\n\tby theia.denx.de (Postfix) with ESMTPS id 6DD294B605\n\tfor <u-boot@lists.denx.de>; Mon, 12 Jan 2015 22:00:19 +0100 (CET)", "from [127.0.0.1] by nm42.bullet.mail.ne1.yahoo.com with NNFMP;\n\t12 Jan 2015 21:00:17 -0000", "from [98.138.226.180] by nm42.bullet.mail.ne1.yahoo.com with NNFMP;\n\t12 Jan 2015 20:56:53 -0000", "from [106.10.166.116] by tm15.bullet.mail.ne1.yahoo.com with NNFMP;\n\t12 Jan 2015 20:56:52 -0000", "from [106.10.167.161] by tm5.bullet.mail.sg3.yahoo.com with NNFMP; \n\t12 Jan 2015 20:56:52 -0000", "from [127.0.0.1] by smtp134.mail.sg3.yahoo.com with NNFMP;\n\t12 Jan 2015 20:56:52 -0000" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=rocketmail.com;\n\ts=s2048; \n\tt=1421096417; bh=CX1lQClOhdBZuZ0pl1/WpPRXsOx4yR6eqRfRWee1sw4=;\n\th=From:To:Cc:Subject:Date:From:Subject;\n\tb=jZ5G52eMP0a6SEyNeWS9U4qyFp1WJ8krhW/XCRmtcZf41T45sy+pQ1ENRLkGIptwq76zNcNNFDnsZ84+wCcWaNjpD0ysnfaGHoquoziI2FrzaDaSl93lDQ4O02iR6svDzD5/UIOvMwE84lHmr6X1JfmB/nb0rZ/XBxLJ0U+2SWSqX7Ob5o9sD1f2R/q78/XxMIY0MxcXK5UUiLcr64cHw/T9CXO5JagVI2RSAUNq4JQ3EaUofrP0FiArSaO4THFFtPc25QXhgsbhHhB7E7DCKRwX5b6LG13sF0GQkw3rXJ4vlAgs/u1hLcBadXe0NWzqHAFHaciInmNRkOOyTZfs9Q==", "DomainKey-Signature": "a=rsa-sha1; q=dns; c=nofws; s=s2048; d=rocketmail.com; \n\tb=L/aJ41LoFu5FKhuNlNFQwhIyGkbeQXGKguXmmyXLkj+skVMnIyNoU8erGS+vi6caERtPVDEaW/fXIjETPx/CWdc3n80OGMmpCJ0s6/uW6cO26xZ6aAi7o6r42QJxGnEfamfZKixn6zBPKWtxbuq8S4+HkDR+oW0QRn7EWHrfPhl6aXUdzUx2q/k4Z0EO8RIRuRaWOyqAwdfleCNqcqyi10drqojncfi9QRkH+xmjemMJSvFkU8Hei26LuJbdrRbEKA3adsP7WBsuAzGRrRCRd68iNsPzcLP5w2p9VnspOsitstdt1OEnLfavKbnyPlYFvN4ELHqp2ZIE0FP6FvovZg==;", "X-Yahoo-Newman-Id": "510843.33026.bm@smtp134.mail.sg3.yahoo.com", "X-Yahoo-Newman-Property": "ymail-4", "X-YMail-OSG": "p8ykKTwVM1lAM99uB3nGznz5.PEpI2xzOIo.YTjnYObtyH8\n\t4ufXGQMHa9C0RtadNosiyw2SdFyAti2VP0X8lK516OGD_wBxUo5hLNcv_JkE\n\tdxkTXGDN6TbN5bAhbnExstyItYRPU3Y8DUncxvW2kGN8d5xKZUoCWPMjAmAU\n\t_ztYXYdQgN5cD55Gg8l1_utnty7D7sTe.ia3emOAyKmaAPyoDtEbcTVmgLQ_\n\t6gGYaSJM9blvn1apd4MenF3TZf.bBhlJ61OG3jX9MGjc9RUZH3YjutcTJiqr\n\tVhzo8n1eXMGFEaeb3TUl4KdHw8insthUmzX0cnuURgxH2.cKEZPapwJdou.c\n\t0RjyC3p2ZaacoteCzkVqlLNgcwYdBPMY1meMPbp3r0e75__810v4lVHN7grw\n\tzdJKzO9BjsiHvypTui9JKnhxgXk7gVi6GEp6aLYQi2VRwRl68ToaugYkwpZF\n\t5QYpHS2l3N1YfrPcf.jjQ4YqKyhcECqn9EhbiQ9fToDXs0TO8UFh7L4uEEkt\n\t7G4i7GdNAWJSseoN.m9xWKwiepLfCFd6LjSPulD0hWE.Oxt_.EIWnTEXVQCK\n\tt474sVkXi80W6HXcx", "X-Yahoo-SMTP": "crLrLjSswBAdKO_oWys7UTWLvPXPfbdd3XtEOYM5nEof1j3oy80-", "From": "Arnab Basu <arnab_basu@rocketmail.com>", "To": "u-boot@lists.denx.de,\n\tAlbert Aribaud <albert.u.boot@aribaud.net>", "Date": "Tue, 13 Jan 2015 02:26:45 +0530", "Message-Id": "<1421096205-27732-1-git-send-email-arnab_basu@rocketmail.com>", "X-Mailer": "git-send-email 1.9.1", "X-Mailman-Approved-At": "Mon, 12 Jan 2015 22:01:16 +0100", "Cc": "stuart.yoder@freescale.com, Marc Zyngier <marc.zyngier@arm.com>,\n\tyorksun@freescale.com", "Subject": "[U-Boot] [PATCH v2 6/9] ARMv8: PCSI: Add generic ARMv8 PSCI code", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.13", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "u-boot-bounces@lists.denx.de", "Errors-To": "u-boot-bounces@lists.denx.de" }, "content": "Implement core support for PSCI. As this is generic code, it doesn't\nimplement anything really useful (all the functions are returning\nNot Implemented).\n\nThis is largely ported from the similar code that exists for ARMv7\n\nSigned-off-by: Arnab Basu <arnab_basu@rocketmail.com>\nCc: Bhupesh Sharma <bhupesh.sharma@freescale.com>\nCc: Marc Zyngier <marc.zyngier@arm.com>\n---\n arch/arm/cpu/armv8/Makefile | 3 +-\n arch/arm/cpu/armv8/psci.S | 162 +++++++++++++++++++++++++++++++++++++++\n arch/arm/include/asm/armv8/esr.h | 12 +++\n 3 files changed, 176 insertions(+), 1 deletion(-)\n create mode 100644 arch/arm/cpu/armv8/psci.S\n create mode 100644 arch/arm/include/asm/armv8/esr.h", "diff": "diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile\nindex 74c32b2..1c696ea 100644\n--- a/arch/arm/cpu/armv8/Makefile\n+++ b/arch/arm/cpu/armv8/Makefile\n@@ -16,4 +16,5 @@ obj-y\t+= tlb.o\n obj-y\t+= transition.o\n obj-y\t+= cpu-dt.o\n \n-obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/\n+obj-$(CONFIG_ARMV8_PSCI)\t+= psci.o\n+obj-$(CONFIG_FSL_LSCH3) \t+= fsl-lsch3/\ndiff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S\nnew file mode 100644\nindex 0000000..6028020\n--- /dev/null\n+++ b/arch/arm/cpu/armv8/psci.S\n@@ -0,0 +1,162 @@\n+/*\n+ * (C) Copyright 2014\n+ * Arnab Basu <arnab.basu@freescale.com>\n+ * (C) Copyright 2015\n+ * Arnab Basu <arnab_basu@rocketmail.com>\n+ *\n+ * Based on arch/arm/cpu/armv7/psci.S\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <linux/linkage.h>\n+#include <asm/psci.h>\n+#include <asm/armv8/esr.h>\n+\n+#define PSCI_FN(__id, __fn) \\\n+ .quad __id; \\\n+ .quad __fn\n+\n+.pushsection ._secure.text, \"ax\"\n+\n+ENTRY(psci_0_2_cpu_suspend_64)\n+ENTRY(psci_0_2_cpu_on_64)\n+ENTRY(psci_0_2_affinity_info_64)\n+ENTRY(psci_0_2_migrate_64)\n+ENTRY(psci_0_2_migrate_info_up_cpu_64)\n+\tmov\tx0, #ARM_PSCI_RET_NI\t/* Return -1 (Not Implemented) */\n+\tret\n+ENDPROC(psci_0_2_cpu_suspend_64)\n+ENDPROC(psci_0_2_cpu_on_64)\n+ENDPROC(psci_0_2_affinity_info_64)\n+ENDPROC(psci_0_2_migrate_64)\n+ENDPROC(psci_0_2_migrate_info_up_cpu_64)\n+.weak psci_0_2_cpu_suspend_64\n+.weak psci_0_2_cpu_on_64\n+.weak psci_0_2_affinity_info_64\n+.weak psci_0_2_migrate_64\n+.weak psci_0_2_migrate_info_up_cpu_64\n+\n+ENTRY(psci_0_2_psci_version)\n+\tmov\tx0, #2\t\t\t/* Return Major = 0, Minor = 2*/\n+\tret\n+ENDPROC(psci_0_2_psci_version)\n+\n+.align 4\n+_psci_0_2_table:\n+\tPSCI_FN(PSCI_0_2_FN_PSCI_VERSION, psci_0_2_psci_version)\n+\tPSCI_FN(PSCI_0_2_FN64_CPU_SUSPEND, psci_0_2_cpu_suspend_64)\n+\tPSCI_FN(PSCI_0_2_FN64_CPU_ON, psci_0_2_cpu_on_64)\n+\tPSCI_FN(PSCI_0_2_FN64_AFFINITY_INFO, psci_0_2_affinity_info_64)\n+\tPSCI_FN(PSCI_0_2_FN64_MIGRATE, psci_0_2_migrate_64)\n+\tPSCI_FN(PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU, psci_0_2_migrate_info_up_cpu_64)\n+\tPSCI_FN(0, 0)\n+\n+.macro\tpsci_enter\n+\tstp\tx29, x30, [sp, #-16]!\n+\tstp\tx27, x28, [sp, #-16]!\n+\tstp\tx25, x26, [sp, #-16]!\n+\tstp\tx23, x24, [sp, #-16]!\n+\tstp\tx21, x22, [sp, #-16]!\n+\tstp\tx19, x20, [sp, #-16]!\n+ str x18, [sp, #-8]!\n+ mrs x16, sp_el0\n+ mrs x15, elr_el3\n+\tstp\tx15, x16, [sp, #-16]!\n+\n+\t/* Switching to Secure State to Execute U-Boot */\n+\tmrs\tx4, scr_el3\n+\tbic\tx4, x4, #1\n+\tmsr\tscr_el3, x4\n+.endm\n+\n+.macro\tpsci_return\n+\t/* Switching to Non-Secure State to Execute OS */\n+\tmrs\tx4, scr_el3\n+\torr\tx4, x4, #1\n+\tmsr\tscr_el3, x4\n+\n+ ldp x15, x16, [sp], #16\n+ msr elr_el3, x15\n+ msr sp_el0, x16\n+ ldr x18, [sp], #8\n+\tldp\tx19, x20, [sp], #16\n+\tldp\tx21, x22, [sp], #16\n+\tldp\tx23, x24, [sp], #16\n+\tldp\tx25, x26, [sp], #16\n+\tldp\tx27, x28, [sp], #16\n+\tldp\tx29, x30, [sp], #16\n+\teret\n+.endm\n+\n+ENTRY(_smc_psci)\n+\tpsci_enter\n+\tadr\tx4, _psci_0_2_table\n+1:\tldp\tx5, x6, [x4]\t /* Load PSCI function ID and target PC */\n+\tcbz\tx5, fn_not_found /* If reach the end, bail out */\n+\tcmp\tx0, x5\t\t /* If not matching, try next entry */\n+\tb.eq\tfn_call\n+\tadd\tx4, x4, #16\n+\tb\t1b\n+\n+fn_call:\n+\tblr\tx6\n+\tpsci_return\n+\n+fn_not_found:\n+\tmov\tx0, #ARM_PSCI_RET_NI /* Return -1 (Not Supported) */\n+\tpsci_return\n+ENDPROC(_smc_psci)\n+\n+ENTRY(unhandled_exception)\n+/* Returning to the place that caused the exception has the potential to cause\n+ * an endless loop of taking the same exception over and over again. Looping\n+ * here seems marginally better\n+ */\n+1: b 1b\n+ENDPROC(unhandled_exception)\n+\n+__handle_sync:\n+\tstr \tx4, [sp, #-8]!\n+\tmrs\tx4, esr_el3\n+\tubfx\tx4, x4, #26, #6\n+\tcmp\tx4, #ESR_EC_SMC64\n+\tb.eq\tsmc_found\n+\tldr\tx4, [sp], #8\n+\tb\tunhandled_exception\n+smc_found:\n+\tldr x4, [sp], #8\n+\tb\t_smc_psci\n+\n+/*\n+ * PSCI Exception vectors.\n+ */\n+\t.align\t11\n+\t.globl\tpsci_vectors\n+psci_vectors:\n+\t.align\t7\n+\tb\tunhandled_exception\t/* Current EL Synchronous Thread */\n+\t.align\t7\n+\tb\tunhandled_exception\t/* Current EL IRQ Thread */\n+\t.align\t7\n+\tb\tunhandled_exception\t/* Current EL FIQ Thread */\n+\t.align\t7\n+\tb\tunhandled_exception\t/* Current EL Error Thread */\n+\t.align\t7\n+\tb\tunhandled_exception\t/* Current EL Synchronous Handler */\n+\t.align\t7\n+\tb\tunhandled_exception\t/* Current EL IRQ Handler */\n+\t.align\t7\n+\tb\tunhandled_exception\t/* Current EL FIQ Handler */\n+\t.align\t7\n+\tb\tunhandled_exception\t/* Current EL Error Handler */\n+\t.align\t7\n+\tb\t__handle_sync\t\t/* Lower EL Synchronous (64b) */\n+\t.align\t7\n+\tb\tunhandled_exception\t/* Lower EL IRQ (64b) */\n+\t.align\t7\n+\tb\tunhandled_exception\t/* Lower EL FIQ (64b) */\n+\t.align\t7\n+\tb\tunhandled_exception\t/* Lower EL Error (64b) */\n+\n+.popsection\ndiff --git a/arch/arm/include/asm/armv8/esr.h b/arch/arm/include/asm/armv8/esr.h\nnew file mode 100644\nindex 0000000..59d4289\n--- /dev/null\n+++ b/arch/arm/include/asm/armv8/esr.h\n@@ -0,0 +1,12 @@\n+/*\n+ * Copyright 2015, Arnab Basu <arnab_basu@rocketmail.com>\n+ *\n+ * SPDX-License-Identifier: GPL-2.0+\n+ */\n+\n+#ifndef _ARMV8_ESR_H\n+#define _ARMV8_ESR_H\n+\n+#define ESR_EC_SMC64\t(0x17)\n+\n+#endif /* _ARMV8_ESR_H */\n", "prefixes": [ "U-Boot", "v2", "6/9" ] }