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GET /api/patches/428127/?format=api
{ "id": 428127, "url": "http://patchwork.ozlabs.org/api/patches/428127/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1421096171-27644-1-git-send-email-arnab_basu@rocketmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1421096171-27644-1-git-send-email-arnab_basu@rocketmail.com>", "list_archive_url": null, "date": "2015-01-12T20:56:11", "name": "[U-Boot,v2,4/9] vexpress_aemv8a: Add spin table handling with per cpu release addresses", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "a4b9077a7cfe0523ed34b6ab5af4de56b0305c0b", "submitter": { "id": 65465, "url": "http://patchwork.ozlabs.org/api/people/65465/?format=api", "name": "Arnab Basu", "email": "arnab_basu@rocketmail.com" }, "delegate": { "id": 1694, "url": "http://patchwork.ozlabs.org/api/users/1694/?format=api", "username": "aaribaud", "first_name": "Albert", "last_name": "ARIBAUD", "email": "albert.aribaud@free.fr" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1421096171-27644-1-git-send-email-arnab_basu@rocketmail.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/428127/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/428127/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id A777F140146\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 13 Jan 2015 08:01:59 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 5DEEA4B6AF;\n\tMon, 12 Jan 2015 22:01:49 +0100 (CET)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id RDlHyMFp67lT; Mon, 12 Jan 2015 22:01:49 +0100 (CET)", "from theia.denx.de (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id A27AF4B60F;\n\tMon, 12 Jan 2015 22:01:25 +0100 (CET)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id C09E04B608\n\tfor <u-boot@lists.denx.de>; Mon, 12 Jan 2015 21:59:20 +0100 (CET)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id NN3341Fztf0R for <u-boot@lists.denx.de>;\n\tMon, 12 Jan 2015 21:59:20 +0100 (CET)", "from nm41-vm4.bullet.mail.ne1.yahoo.com\n\t(nm41-vm4.bullet.mail.ne1.yahoo.com [98.138.120.220])\n\tby theia.denx.de (Postfix) with ESMTPS id 3CB944B605\n\tfor <u-boot@lists.denx.de>; Mon, 12 Jan 2015 21:59:17 +0100 (CET)", "from [127.0.0.1] by nm41.bullet.mail.ne1.yahoo.com with NNFMP;\n\t12 Jan 2015 20:59:15 -0000", "from [98.138.100.117] by nm41.bullet.mail.ne1.yahoo.com with NNFMP;\n\t12 Jan 2015 20:56:20 -0000", "from [106.10.166.123] by tm108.bullet.mail.ne1.yahoo.com with\n\tNNFMP; 12 Jan 2015 20:56:19 -0000", "from [106.10.167.172] by tm12.bullet.mail.sg3.yahoo.com with NNFMP;\n\t12 Jan 2015 20:56:19 -0000", "from [127.0.0.1] by smtp145.mail.sg3.yahoo.com with NNFMP;\n\t12 Jan 2015 20:56:19 -0000" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=rocketmail.com;\n\ts=s2048; \n\tt=1421096355; bh=lY7WxlAK41UBcEA26PbT5zZU53E94mEmb8UfCLVSz3Y=;\n\th=From:To:Cc:Subject:Date:From:Subject;\n\tb=j0MF9teHGj3OuMeN6gwfubMrfCpaGreXW27af7cEgv112/bT9c/OuazxWdKwviIOy9SJOoahlT2Tpwi6bpRnkl5c8TdO45VAz/TsQqS72LY5BvvRqbYicF+wAin05ge6eqCigu2bLjLw3IFSeYc8IlQ6RSM/4Gy2AnAIlpulfP1xnexT4Q0PqWxsgOEUWvT/l/tOngFLp7qxcM4c4S1n+L50uI9Hg8CkSajWUIlLK7vIBTrufmaxErG6FvKI6M4imBeBmQ50mWTvNUz3AkIKQ3m51urVZUtiOxKCYWU/A0Dwdjss6wnS6OkjzKFyJx7XmXmNJp9X7oSHjW9DNJU0RA==", "DomainKey-Signature": "a=rsa-sha1; q=dns; c=nofws; s=s2048; d=rocketmail.com; \n\tb=qeP6ski1tL/w7BwecyxcKlimVgon2/n7IgWf5vDylWN/RDm1JinvhmI5wdFNsUK8PqJLsCWmVTZqYLIXL8OYrFsrAPpPxNSBoKfv2L1RZMO8ZeqF3dxNA2c97hn7s9DhvfaOzcwD6szar6T8ZXlu1yy9ETocSaBgBVDD92/0l2p9ePFc6/n7Ktx3CGpwTlxzM+Ee1FJtY/ufDSpsi+YGuywbZWxidgC6q2/DJsOFPTH7ac2rBH2+sRXap4N0SMPgsAHFJSdmXC6IhwMHefUFWa/TlW8AG3OKWHDDLF4kzUsAv0GWQSYNhQpPtgOc5TrZvpt6VK+Ziv3SldqLRouLGA==;", "X-Yahoo-Newman-Id": "152216.59308.bm@smtp145.mail.sg3.yahoo.com", "X-Yahoo-Newman-Property": "ymail-4", "X-YMail-OSG": "11ze2GYVM1kEdQW6V_EisymoBG4ISrSBvohqPuF3PhWGsXd\n\tgJPoG5GEViZ3fGkYw5ynrRIrTNnfe2HxRnji.0_ptn65PEZR7XfVQHnOcmar\n\tUK8vg.3RpePWCK4R77fnkYRtkWkCnNp4UHrPdgKCi.XSaA9mvicJ3pySQlHZ\n\t5pgLA8NlncI9EHTnbWQjH7yeHSdZTs4IxuaJHWv50xIjQczN8t5Ov5.ZwFpX\n\tEFcgmF9ePc3_TVEUF2LuOf2wkkT6h0jGybKZi9K3dvUH8FIB7mPK3DslPO8N\n\tDiFfRP6G5m2KHOOVDCrSWvDT881m_miQljGnS96ey8CvDozSDGZ3CkpleRT9\n\t48v39GLpVJqsG.FLYsL2PbD4o.JTtSQLgVls6F1tkYDxOQJLtNgk_npOQ71z\n\ty8oOKy1sDwYaIXmz9RhN8YiqP_3aE94gHyyWeDr.b4pEueAPj75R3wX0BCkz\n\tfTZkckJJkFAAXONrbfQkgq5.eWvOAEba2iaVuERypnJ_K4F7sgavuBIZrh7i\n\tgGNf8FqVV.C_MsVOi86rVp0t1qd9e6zrkboo7Z3A3hVgHSB8aPgt5kWPgfkp\n\th_vwyWB9Hu4Mt9mNy", "X-Yahoo-SMTP": "crLrLjSswBAdKO_oWys7UTWLvPXPfbdd3XtEOYM5nEof1j3oy80-", "From": "Arnab Basu <arnab_basu@rocketmail.com>", "To": "u-boot@lists.denx.de,\n\tAlbert Aribaud <albert.u.boot@aribaud.net>", "Date": "Tue, 13 Jan 2015 02:26:11 +0530", "Message-Id": "<1421096171-27644-1-git-send-email-arnab_basu@rocketmail.com>", "X-Mailer": "git-send-email 1.9.1", "X-Mailman-Approved-At": "Mon, 12 Jan 2015 22:01:16 +0100", "Cc": "stuart.yoder@freescale.com, Marc.Zyngier@arm.com, yorksun@freescale.com", "Subject": "[U-Boot] [PATCH v2 4/9] vexpress_aemv8a: Add spin table handling\n\twith per cpu release addresses", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.13", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "u-boot-bounces@lists.denx.de", "Errors-To": "u-boot-bounces@lists.denx.de" }, "content": "Signed-off-by: Arnab Basu <arnab_basu@rocketmail.com>\n---\n arch/arm/cpu/armv8/cpu-dt.c | 16 ++++-\n arch/arm/cpu/armv8/cpu.c | 113 ++++++++++++++++++++++++++++++\n arch/arm/cpu/armv8/start.S | 141 +++++++++++++++++++++++++++++---------\n arch/arm/include/asm/armv8/mp.h | 36 ++++++++++\n arch/arm/include/asm/config.h | 1 +\n include/configs/vexpress_aemv8a.h | 2 +\n 6 files changed, 275 insertions(+), 34 deletions(-)\n create mode 100644 arch/arm/include/asm/armv8/mp.h", "diff": "diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c\nindex 8833e6a..ce0e3c6 100644\n--- a/arch/arm/cpu/armv8/cpu-dt.c\n+++ b/arch/arm/cpu/armv8/cpu-dt.c\n@@ -7,16 +7,30 @@\n #include <common.h>\n #include <libfdt.h>\n #include <fdt_support.h>\n+#include <asm/armv8/mp.h>\n \n #ifdef CONFIG_MP\n+DECLARE_GLOBAL_DATA_PTR;\n \n __weak u64 arch_get_release_addr(u64 cpu_id)\n {\n-\treturn 0;\n+\tu64 val;\n+\tu64 spin_table_loc = (u64)get_spin_tbl_addr();\n+\n+\tval = spin_table_loc;\n+\tval += id_to_core(cpu_id) * SPIN_TABLE_ELEM_SIZE;\n+\n+\treturn val;\n }\n \n __weak void arch_spin_table_reserve_mem(void *fdt)\n {\n+\tsize_t *boot_code_size = &(__secondary_boot_code_size);\n+\tu64 boot_code_loc = ((u64)&secondary_boot_code - gd->relocaddr\n+\t\t\t+ CONFIG_SYS_TEXT_BASE);\n+\n+\tfdt_add_mem_rsv(fdt, (uintptr_t)boot_code_loc,\n+\t\t\t*boot_code_size);\n }\n \n static void cpu_update_dt_spin_table(void *blob)\ndiff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c\nindex e06c3cc..2c8be1c 100644\n--- a/arch/arm/cpu/armv8/cpu.c\n+++ b/arch/arm/cpu/armv8/cpu.c\n@@ -16,6 +16,119 @@\n #include <asm/system.h>\n #include <linux/compiler.h>\n \n+#ifdef CONFIG_MP\n+#include <asm/armv8/mp.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+static u32 active_cores;\n+\n+void *get_spin_tbl_addr(void)\n+{\n+\treturn (void *)((u64)__spin_table - gd->relocaddr\n+\t\t\t+ CONFIG_SYS_TEXT_BASE);\n+}\n+\n+static void init_active_cores(void)\n+{\n+\tint i;\n+\n+\n+\tactive_cores = 1; /* The 0th (boot) core must be up */\n+\n+\tfor (i = 1; i < CONFIG_MAX_CPUS; i++) {\n+\t\tu64 *spin_table_entry = ((u64 *)get_spin_tbl_addr() +\n+\t\t\t\t(i * WORDS_PER_SPIN_TABLE_ENTRY));\n+\n+\t\tif (spin_table_entry[SPIN_TABLE_ELEM_STATUS_IDX])\n+\t\t\tactive_cores |= (1 << i);\n+\t}\n+}\n+\n+u32 cpu_mask(void)\n+{\n+\tif (!active_cores)\n+\t\tinit_active_cores();\n+\n+\treturn active_cores;\n+}\n+\n+int is_core_valid(unsigned int core)\n+{\n+\treturn !!((1 << core) & cpu_mask());\n+}\n+\n+int cpu_reset(int nr)\n+{\n+\tputs(\"Feature is not implemented.\\n\");\n+\n+\treturn 0;\n+}\n+\n+int cpu_disable(int nr)\n+{\n+\tputs(\"Feature is not implemented.\\n\");\n+\n+\treturn 0;\n+}\n+\n+int core_to_pos(int nr)\n+{\n+\tu32 cores = cpu_mask();\n+\tint i, count = 0;\n+\n+\tif (nr == 0) {\n+\t\treturn 0;\n+\t} else if (nr >= hweight32(cores)) {\n+\t\tputs(\"Not a valid core number.\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\tfor (i = 1; i < 32; i++) {\n+\t\tif (is_core_valid(i)) {\n+\t\t\tcount++;\n+\t\t\tif (count == nr)\n+\t\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn count;\n+}\n+\n+int cpu_status(int nr)\n+{\n+\tu64 *table;\n+\tint pos;\n+\n+\tif (nr == 0) {\n+\t\ttable = (u64 *)get_spin_tbl_addr();\n+\t\tprintf(\"table base @ 0x%p\\n\", table);\n+\t} else {\n+\t\tpos = core_to_pos(nr);\n+\t\tif (pos < 0)\n+\t\t\treturn -1;\n+\t\ttable = (u64 *)get_spin_tbl_addr() + pos *\n+\t\t\tWORDS_PER_SPIN_TABLE_ENTRY;\n+\t\tprintf(\"table @ 0x%p\\n\", table);\n+\t\tprintf(\" addr - 0x%016llx\\n\",\n+\t\t table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]);\n+\t\tprintf(\" status - 0x%016llx\\n\",\n+\t\t table[SPIN_TABLE_ELEM_STATUS_IDX]);\n+\t\tprintf(\" lpid - 0x%016llx\\n\",\n+\t\t table[SPIN_TABLE_ELEM_LPID_IDX]);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int cpu_release(int nr, int argc, char * const argv[])\n+{\n+\tputs(\"Feature is not implemented.\\n\");\n+\n+\treturn 0;\n+}\n+#endif\n+\n int cleanup_before_linux(void)\n {\n \t/*\ndiff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S\nindex 4b11aa4..e985ede 100644\n--- a/arch/arm/cpu/armv8/start.S\n+++ b/arch/arm/cpu/armv8/start.S\n@@ -9,8 +9,10 @@\n #include <config.h>\n #include <version.h>\n #include <linux/linkage.h>\n+#include <asm/gic.h>\n #include <asm/macro.h>\n #include <asm/armv8/mmu.h>\n+#include <asm/armv8/mp.h>\n \n /*************************************************************************\n *\n@@ -77,22 +79,9 @@ reset:\n \t/* Processor specific initialization */\n \tbl\tlowlevel_init\n \n-\tbranch_if_master x0, x1, master_cpu\n-\n-\t/*\n-\t * Slave CPUs\n-\t */\n-slave_cpu:\n-\twfe\n-\tldr\tx1, =CPU_RELEASE_ADDR\n-\tldr\tx0, [x1]\n-\tcbz\tx0, slave_cpu\n-\tbr\tx0\t\t\t/* branch to the given address */\n-\n \t/*\n-\t * Master CPU\n+\t * Only Master CPU will get here\n \t */\n-master_cpu:\n \tbl\t_main\n \n /*-----------------------------------------------------------------------*/\n@@ -117,25 +106,8 @@ WEAK(lowlevel_init)\n \n \tbranch_if_master x0, x1, 2f\n \n-\t/*\n-\t * Slave should wait for master clearing spin table.\n-\t * This sync prevent salves observing incorrect\n-\t * value of spin table and jumping to wrong place.\n-\t */\n-#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)\n-#ifdef CONFIG_GICV2\n-\tldr\tx0, =GICC_BASE\n-#endif\n-\tbl\tgic_wait_for_interrupt\n-#endif\n-\n-\t/*\n-\t * All slaves will enter EL2 and optionally EL1.\n-\t */\n-\tbl\tarmv8_switch_to_el2\n-#ifdef CONFIG_ARMV8_SWITCH_TO_EL1\n-\tbl\tarmv8_switch_to_el1\n-#endif\n+\tldr\tx0, =secondary_boot_func\n+\tblr\tx0\n \n 2:\n \tmov\tlr, x29\t\t\t/* Restore LR */\n@@ -168,3 +140,106 @@ ENTRY(c_runtime_cpu_setup)\n \n \tret\n ENDPROC(c_runtime_cpu_setup)\n+\n+\t/* Keep literals not used by the secondary boot code outside it */\n+\t.ltorg\n+\n+\t/* Using 64 bit alignment since the spin table is accessed as data */\n+\t.align 4\n+\t.global secondary_boot_code\n+\t/* Secondary Boot Code starts here */\n+secondary_boot_code:\n+\t.global __spin_table\n+__spin_table:\n+\t.zero CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE\n+\n+\t.align 2\n+ENTRY(secondary_boot_func)\n+\t/*\n+\t * MPIDR_EL1 Fields:\n+\t * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)\n+\t * MPIDR[7:2] = AFF0_RES\n+\t * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)\n+\t * MPIDR[23:16] = AFF2_CLUSTERID\n+\t * MPIDR[24] = MT\n+\t * MPIDR[29:25] = RES0\n+\t * MPIDR[30] = U\n+\t * MPIDR[31] = ME\n+\t * MPIDR[39:32] = AFF3\n+\t *\n+\t * Linear Processor ID (LPID) calculation from MPIDR_EL1:\n+\t * (We only use AFF0_CPUID and AFF1_CLUSTERID for now\n+\t * until AFF2_CLUSTERID and AFF3 have non-zero values)\n+\t *\n+\t * LPID = MPIDR[15:8] | MPIDR[1:0]\n+\t */\n+\tmrs\tx0, mpidr_el1\n+\tubfm\tx1, x0, #8, #15\n+\tubfm\tx2, x0, #0, #1\n+\torr\tx10, x2, x1, lsl #2\t/* x10 has LPID */\n+\tubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */\n+\t/*\n+\t * offset of the spin table element for this core from start of spin\n+\t * table (each elem is padded to 64 bytes)\n+\t */\n+\tlsl\tx1, x10, #6\n+\tldr\tx0, =__spin_table\n+\t/* physical address of this cpus spin table element */\n+\tadd\tx11, x1, x0\n+\n+\tstr\tx9, [x11, #16]\t/* LPID */\n+\tmov\tx4, #1\n+\tstr\tx4, [x11, #8]\t/* STATUS */\n+\tdsb\tsy\n+#if defined(CONFIG_GICV3)\n+\tgic_wait_for_interrupt_m x0\n+#elif defined(CONFIG_GICV2)\n+ ldr x0, =GICC_BASE\n+ gic_wait_for_interrupt_m x0, w1\n+#endif\n+\n+\tbl secondary_switch_to_el2\n+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1\n+\tbl secondary_switch_to_el1\n+#endif\n+\n+slave_cpu:\n+\twfe\n+\tldr\tx0, [x11]\n+\tcbz\tx0, slave_cpu\n+#ifndef CONFIG_ARMV8_SWITCH_TO_EL1\n+\tmrs x1, sctlr_el2\n+#else\n+\tmrs x1, sctlr_el1\n+#endif\n+\ttbz x1, #25, cpu_is_le\n+\trev x0, x0 /* BE to LE conversion */\n+cpu_is_le:\n+\tbr\tx0\t\t\t/* branch to the given address */\n+ENDPROC(secondary_boot_func)\n+\n+ENTRY(secondary_switch_to_el2)\n+\tswitch_el x0, 1f, 0f, 0f\n+0:\tret\n+1:\tarmv8_switch_to_el2_m x0\n+ENDPROC(secondary_switch_to_el2)\n+\n+ENTRY(secondary_switch_to_el1)\n+\tswitch_el x0, 0f, 1f, 0f\n+0:\tret\n+1:\tarmv8_switch_to_el1_m x0, x1\n+ENDPROC(secondary_switch_to_el1)\n+\n+\t/* Ensure that the literals used by the secondary boot code are\n+\t * assembled within it (this is required so that we can protect\n+\t * this area with a single memreserve region\n+\t */\n+\t.ltorg\n+\n+\t/* 64 bit alignment for elements accessed as data */\n+\t.align 4\n+\t.globl __secondary_boot_code_size\n+\t.type __secondary_boot_code_size, %object\n+\t/* Secondary Boot Code ends here */\n+__secondary_boot_code_size:\n+\t.quad .-secondary_boot_code\ndiff --git a/arch/arm/include/asm/armv8/mp.h b/arch/arm/include/asm/armv8/mp.h\nnew file mode 100644\nindex 0000000..77e79cb\n--- /dev/null\n+++ b/arch/arm/include/asm/armv8/mp.h\n@@ -0,0 +1,36 @@\n+/*\n+ * Copyright 2014, Freescale Semiconductor\n+ * Copyright 2015, Arnab Basu <arnab_basu@rocketmail.com>\n+ * (modified version of arch/arm/cpu/armv8/fsl-lsch3/mp.h)\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef _ARMV8_MP_H\n+#define _ARMV8_MP_H\n+\n+/*\n+* Each spin table element is defined as\n+* struct {\n+* uint64_t entry_addr;\n+* uint64_t status;\n+* uint64_t lpid;\n+* };\n+* we pad this struct to 64 bytes so each entry is in its own cacheline\n+* the actual spin table is an array of these structures\n+*/\n+#define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX\t0\n+#define SPIN_TABLE_ELEM_STATUS_IDX\t1\n+#define SPIN_TABLE_ELEM_LPID_IDX\t2\n+#define WORDS_PER_SPIN_TABLE_ENTRY\t8\t/* pad to 64 bytes */\n+#define SPIN_TABLE_ELEM_SIZE\t\t64\n+\n+#define id_to_core(x)\t((x & 3) | (x >> 6))\n+#ifndef __ASSEMBLY__\n+extern u64 __spin_table[];\n+extern phys_addr_t secondary_boot_code;\n+extern size_t __secondary_boot_code_size;\n+void *get_spin_tbl_addr(void);\n+void secondary_boot_func(void);\n+#endif\n+#endif /* _ARMV8_MP_H */\ndiff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h\nindex be80434..97544fb 100644\n--- a/arch/arm/include/asm/config.h\n+++ b/arch/arm/include/asm/config.h\n@@ -15,6 +15,7 @@\n #define CONFIG_SYS_BOOT_RAMDISK_HIGH\n \n #ifdef CONFIG_ARM64\n+#define CONFIG_MP\n #define CONFIG_PHYS_64BIT\n #define CONFIG_STATIC_RELA\n #endif\ndiff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h\nindex 027d78b..9c4f06b 100644\n--- a/include/configs/vexpress_aemv8a.h\n+++ b/include/configs/vexpress_aemv8a.h\n@@ -8,6 +8,8 @@\n #ifndef __VEXPRESS_AEMV8A_H\n #define __VEXPRESS_AEMV8A_H\n \n+#define CONFIG_MAX_CPUS 4\n+\n /* We use generic board for v8 Versatile Express */\n #define CONFIG_SYS_GENERIC_BOARD\n \n", "prefixes": [ "U-Boot", "v2", "4/9" ] }