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GET /api/patches/422512/?format=api
{ "id": 422512, "url": "http://patchwork.ozlabs.org/api/patches/422512/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/patch/1418891092-14591-1-git-send-email-Zhuoyu.Zhang@freescale.com/", "project": { "id": 19, "url": "http://patchwork.ozlabs.org/api/projects/19/?format=api", "name": "Linux IMX development", "link_name": "linux-imx", "list_id": "linux-imx-kernel.lists.patchwork.ozlabs.org", "list_email": "linux-imx-kernel@lists.patchwork.ozlabs.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1418891092-14591-1-git-send-email-Zhuoyu.Zhang@freescale.com>", "list_archive_url": null, "date": "2014-12-18T08:24:52", "name": "[v3,1/1] arm: ls1: add CPU hotplug platform support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "663c34d3cf911300cac1022af7433fa9893984d5", "submitter": { "id": 42926, "url": "http://patchwork.ozlabs.org/api/people/42926/?format=api", "name": "Zhuoyu Zhang", "email": "Zhuoyu.Zhang@freescale.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-imx/patch/1418891092-14591-1-git-send-email-Zhuoyu.Zhang@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/422512/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/422512/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming-imx@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-imx@bilbo.ozlabs.org", "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n\t[IPv6:2001:1868:205::9])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 2849F140100\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tThu, 18 Dec 2014 19:29:38 +1100 (AEDT)", "from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux))\n\tid 1Y1WQI-0000f8-8s; Thu, 18 Dec 2014 08:27:02 +0000", "from mail-by2on0119.outbound.protection.outlook.com\n\t([207.46.100.119] helo=na01-by2-obe.outbound.protection.outlook.com)\n\tby bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat\n\tLinux)) id 1Y1WQF-0000aS-0N\n\tfor linux-arm-kernel@lists.infradead.org;\n\tThu, 18 Dec 2014 08:26:59 +0000", "from BN3PR0301CA0013.namprd03.prod.outlook.com (25.160.180.151) by\n\tDM2PR0301MB1294.namprd03.prod.outlook.com (25.160.222.148) with\n\tMicrosoft\n\tSMTP Server (TLS) id 15.1.31.17; Thu, 18 Dec 2014 08:26:36 +0000", "from BN1BFFO11FD015.protection.gbl (2a01:111:f400:7c10::1:172) by\n\tBN3PR0301CA0013.outlook.office365.com (2a01:111:e400:4000::23)\n\twith Microsoft\n\tSMTP Server (TLS) id 15.1.36.23 via Frontend Transport;\n\tThu, 18 Dec 2014 08:26:35 +0000", "from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBN1BFFO11FD015.mail.protection.outlook.com (10.58.144.78) with\n\tMicrosoft SMTP Server (TLS) id 15.1.26.17 via Frontend Transport;\n\tThu, 18 Dec 2014 08:26:35 +0000", "from titan.ap.freescale.net ([10.192.208.233])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tsBI8QU2B021074; Thu, 18 Dec 2014 01:26:31 -0700" ], "From": "Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com>", "To": "<linux-kernel@vger.kernel.org>, <kernel@pengutronix.de>,\n\t<linux-arm-kernel@lists.infradead.org>", "Subject": "[PATCH v3 1/1] arm: ls1: add CPU hotplug platform support", "Date": "Thu, 18 Dec 2014 16:24:52 +0800", "Message-ID": "<1418891092-14591-1-git-send-email-Zhuoyu.Zhang@freescale.com>", "X-Mailer": "git-send-email 2.1.0.27.g96db324", "X-EOPAttributedMessage": "0", "Received-SPF": "Fail (protection.outlook.com: domain of freescale.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=Zhuoyu.Zhang@freescale.com; ", "X-Forefront-Antispam-Report": "CIP:192.88.168.50; CTRY:US; IPV:NLI; EFV:NLI;\n\tSFV:NSPM;\n\tSFS:(10019020)(6009001)(339900001)(199003)(189002)(50466002)(92566001)(21056001)(50226001)(229853001)(120916001)(106466001)(36756003)(19580395003)(575784001)(46102003)(86362001)(107046002)(62966003)(4396001)(64706001)(105606002)(87936001)(97736003)(20776003)(6806004)(77096005)(19580405001)(84676001)(85426001)(104016003)(31966008)(50986999)(68736005)(77156002)(89996001)(47776003)(48376002)(2201001);\n\tDIR:OUT; SFP:1102; SCL:1; SRVR:DM2PR0301MB1294;\n\tH:tx30smr01.am.freescale.net; \n\tFPR:; SPF:Fail; MLV:sfv; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en;", "MIME-Version": "1.0", "X-Microsoft-Antispam": [ "UriScan:;", "BCL:0;PCL:0;RULEID:;SRVR:DM2PR0301MB1294;" ], "X-Exchange-Antispam-Report-Test": "UriScan:;", "X-Exchange-Antispam-Report-CFA-Test": [ "BCL:0; PCL:0; RULEID:(601004);\n\tSRVR:DM2PR0301MB1294; ", "BCL:0; PCL:0; RULEID:;\n\tSRVR:DM2PR0301MB1294; " ], "X-Forefront-PRVS": "042957ACD7", "X-OriginatorOrg": "freescale.com", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20141218_002659_112163_62270E4A ", "X-CRM114-Status": "GOOD ( 16.94 )", "X-Spam-Score": "-0.0 (/)", "X-Spam-Report": "SpamAssassin version 3.4.0 on bombadil.infradead.org summary:\n\tContent analysis details: (-0.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [207.46.100.119 listed in list.dnswl.org]\n\t-0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2)\n\t[207.46.100.119 listed in wl.mailspike.net]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 SPF_HELO_PASS SPF: HELO matches SPF record", "Cc": "leoli@freescale.com, chenhui.zhao@freescale.com, Jason.Jin@freescale.com", "X-BeenThere": "linux-arm-kernel@lists.infradead.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-arm-kernel/>", "List-Post": "<mailto:linux-arm-kernel@lists.infradead.org>", "List-Help": "<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>", "Errors-To": "linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org", "List-Id": "linux-imx-kernel.lists.patchwork.ozlabs.org" }, "content": "From: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com>\n\nThis implements CPU hotplug for ls1. When cpu is down, it will be put\nin boot holdoff state. When cpu is up, it will always soft reset and\nboots up the same path as a cold boot.\n\nSigned-off-by: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com>\n---\n arch/arm/mach-imx/common.h | 16 +++++\n arch/arm/mach-imx/hotplug.c | 29 +++++++++\n arch/arm/mach-imx/platsmp.c | 153 ++++++++++++++++++++++++++++++++++++++++----\n 3 files changed, 186 insertions(+), 12 deletions(-)", "diff": "diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h\nindex cfcdb62..c2acb81 100644\n--- a/arch/arm/mach-imx/common.h\n+++ b/arch/arm/mach-imx/common.h\n@@ -13,6 +13,17 @@\n \n #include <linux/reboot.h>\n \n+#define\tSCFG_CORE0_SFT_RST\t0x130\n+#define\tSCFG_CORESRENCR\t\t0x204\n+#define\tDCFG_CCSR_BRR\t\t0x0E4\n+#define\tDCFG_CCSR_SCRATCHRW1\t0x200\n+#define\tCCSR_TWAITSR0\t\t0x04C\n+\n+#define\tSTRIDE_4B\t\t4\n+\n+#define\tSCFG_CORE_SOFT_RST_EN\t0x80000000\n+#define\tSCFG_CORE_SOFT_RST\t0x80000000\n+\n struct irq_data;\n struct platform_device;\n struct pt_regs;\n@@ -92,6 +103,7 @@ void imx_print_silicon_rev(const char *cpu, int srev);\n void imx_enable_cpu(int cpu, bool enable);\n void imx_set_cpu_jump(int cpu, void *jump_addr);\n u32 imx_get_cpu_arg(int cpu);\n+u32 ls1_get_cpu_arg(int cpu);\n void imx_set_cpu_arg(int cpu, u32 arg);\n #ifdef CONFIG_SMP\n void v7_secondary_startup(void);\n@@ -134,6 +146,10 @@ void imx6sl_pm_init(void);\n void imx6sx_pm_init(void);\n void imx6q_pm_set_ccm_base(void __iomem *base);\n \n+extern int ls1021a_holdoff(unsigned int cpu);\n+extern void ls1021a_cpu_die(unsigned int cpu);\n+extern int ls1021a_cpu_kill(unsigned int cpu);\n+\n #ifdef CONFIG_PM\n void imx51_pm_init(void);\n void imx53_pm_init(void);\ndiff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c\nindex b35e99c..8f5f082 100644\n--- a/arch/arm/mach-imx/hotplug.c\n+++ b/arch/arm/mach-imx/hotplug.c\n@@ -14,6 +14,7 @@\n #include <linux/jiffies.h>\n #include <asm/cp15.h>\n #include <asm/proc-fns.h>\n+#include <asm/cacheflush.h>\n \n #include \"common.h\"\n \n@@ -68,3 +69,31 @@ int imx_cpu_kill(unsigned int cpu)\n \timx_set_cpu_arg(cpu, 0);\n \treturn 1;\n }\n+\n+void __ref ls1021a_cpu_die(unsigned int cpu)\n+{\n+\tv7_exit_coherency_flush(louis);\n+\n+\t/* LS1021a platform can't really power down an offline CPU.\n+\t * So we put offline core into WFI, then reset it and put it into\n+\t * boot holdoff state as a workaround method. It is a little tricky,\n+\t * but we have no better choice due to hardware limitation for now.\n+\t */\n+\twfi();\n+\n+\t/* We should never get here. */\n+\tBUG();\n+\n+}\n+\n+int ls1021a_cpu_kill(unsigned int cpu)\n+{\n+\tunsigned long timeout = jiffies + msecs_to_jiffies(50);\n+\n+\twhile (!ls1_get_cpu_arg(cpu))\n+\t\tif (time_after(jiffies, timeout))\n+\t\t\treturn 0;\n+\n+\t/* Reset offline core and put it into boot holdoff state */\n+\treturn ls1021a_holdoff(cpu);\n+}\ndiff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c\nindex 7f27001..6bc1320 100644\n--- a/arch/arm/mach-imx/platsmp.c\n+++ b/arch/arm/mach-imx/platsmp.c\n@@ -14,17 +14,23 @@\n #include <linux/of_address.h>\n #include <linux/of.h>\n #include <linux/smp.h>\n+#include <linux/delay.h>\n \n #include <asm/cacheflush.h>\n #include <asm/page.h>\n #include <asm/smp_scu.h>\n #include <asm/mach/map.h>\n+#include <asm/smp_plat.h>\n \n #include \"common.h\"\n #include \"hardware.h\"\n \n u32 g_diag_reg;\n static void __iomem *scu_base;\n+static void __iomem *dcfg_base;\n+static void __iomem *scfg_base;\n+static void __iomem *rcpm_base;\n+static u32 secondary_pre_boot_entry;\n \n static struct map_desc scu_io_desc __initdata = {\n \t/* .virtual and .pfn are run-time assigned */\n@@ -98,32 +104,155 @@ struct smp_operations imx_smp_ops __initdata = {\n #endif\n };\n \n-#define DCFG_CCSR_SCRATCHRW1\t0x200\n+static int ls1021a_secondary_iomap(void)\n+{\n+\tstruct device_node *np;\n+\tint ret;\n+\n+\tnp = of_find_compatible_node(NULL, NULL, \"fsl,ls1021a-dcfg\");\n+\tif (!np) {\n+\t\tpr_err(\"%s: failed to find dcfg node.\\n\", __func__);\n+\t\tret = -ENODEV;\n+\t\tgoto dcfg_err;\n+\t}\n+\n+\tdcfg_base = of_iomap(np, 0);\n+\tof_node_put(np);\n+\tif (!dcfg_base) {\n+\t\tpr_err(\"%s: failed to map dcfg.\\n\", __func__);\n+\t\tret = -ENOMEM;\n+\t\tgoto dcfg_err;\n+\t}\n+\n+\tnp = of_find_compatible_node(NULL, NULL, \"fsl,ls1021a-scfg\");\n+\tif (!np) {\n+\t\tpr_err(\"%s: failed to find scfg node.\\n\", __func__);\n+\t\tret = -ENODEV;\n+\t\tgoto scfg_err;\n+\t}\n+\n+\tscfg_base = of_iomap(np, 0);\n+\tof_node_put(np);\n+\tif (!scfg_base) {\n+\t\tpr_err(\"%s: failed to map scfg.\\n\", __func__);\n+\t\tret = -ENOMEM;\n+\t\tgoto scfg_err;\n+\t}\n+\n+\tnp = of_find_compatible_node(NULL, NULL, \"fsl,qoriq-rcpm-2.1\");\n+\tif (!np) {\n+\t\tpr_err(\"%s(): failed to find rcpm node.\\n\", __func__);\n+\t\treturn -ENODEV;\n+\t\tgoto rcpm_err;\n+\t}\n+\n+\trcpm_base = of_iomap(np, 0);\n+\tof_node_put(np);\n+\tif (!rcpm_base) {\n+\t\tpr_err(\"%s: failed to map rcpm.\\n\", __func__);\n+\t\tret = -ENOMEM;\n+\t\tgoto rcpm_err;\n+\t}\n+\n+\treturn 0;\n+\n+rcpm_err:\n+\tiounmap(scfg_base);\n+scfg_err:\n+\tiounmap(dcfg_base);\n+dcfg_err:\n+\treturn ret;\n+}\n+\n+u32 ls1_get_cpu_arg(int cpu)\n+{\n+\tcpu = cpu_logical_map(cpu);\n+\treturn ioread32be(rcpm_base + CCSR_TWAITSR0) & (1 << cpu);\n+}\n+\n+int ls1021a_holdoff(unsigned int cpu)\n+{\n+\tif (!scfg_base || !dcfg_base)\n+\t\treturn -ENOMEM;\n+\n+\tiowrite32be(0, dcfg_base + DCFG_CCSR_SCRATCHRW1);\n+\n+\t/* Soft reset secondary core, put it into boot holdoff state */\n+\tsetbits32(scfg_base + SCFG_CORESRENCR, SCFG_CORE_SOFT_RST_EN);\n+\tsetbits32(scfg_base + SCFG_CORE0_SFT_RST + STRIDE_4B * cpu,\n+\t\t\t\t\t\t\tSCFG_CORE_SOFT_RST);\n+\n+\t/* Disable core soft reset register */\n+\tclrbits32(scfg_base + SCFG_CORESRENCR, SCFG_CORE_SOFT_RST_EN);\n+\n+\treturn 1;\n+}\n+\n+void ls1021a_set_secondary_entry(void)\n+{\n+\tunsigned long paddr;\n+\n+\tif (dcfg_base) {\n+\t\tpaddr = virt_to_phys(secondary_startup);\n+\t\tiowrite32be(paddr, dcfg_base + DCFG_CCSR_SCRATCHRW1);\n+\t}\n+}\n+\n+static int ls1021a_reset_secondary(unsigned int cpu)\n+{\n+\tif (!scfg_base || !dcfg_base)\n+\t\treturn -ENOMEM;\n+\n+\tiowrite32be(secondary_pre_boot_entry, dcfg_base + DCFG_CCSR_SCRATCHRW1);\n+\n+\t/* Soft reset secondary core */\n+\tsetbits32(scfg_base + SCFG_CORESRENCR, SCFG_CORE_SOFT_RST_EN);\n+\tsetbits32(scfg_base + SCFG_CORE0_SFT_RST + STRIDE_4B * cpu,\n+\t\t\t\t\t\t\tSCFG_CORE_SOFT_RST);\n+\tmdelay(15);\n+\n+\t/* Release secondary core */\n+\tsetbits32(dcfg_base + DCFG_CCSR_BRR, 1 << cpu);\n+\n+\tmdelay(1);\n+\n+\tls1021a_set_secondary_entry();\n+\n+\t/* Disable core soft reset register */\n+\tclrbits32(scfg_base + SCFG_CORESRENCR, SCFG_CORE_SOFT_RST_EN);\n+\n+\treturn 0;\n+}\n \n static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)\n {\n+\tint ret = 0;\n+\n+\tif (system_state == SYSTEM_RUNNING)\n+\t\tret = ls1021a_reset_secondary(cpu);\n+\n+\tudelay(1);\n+\n \tarch_send_wakeup_ipi_mask(cpumask_of(cpu));\n \n-\treturn 0;\n+\treturn ret;\n }\n \n static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)\n {\n-\tstruct device_node *np;\n-\tvoid __iomem *dcfg_base;\n-\tunsigned long paddr;\n+\tls1021a_secondary_iomap();\n \n-\tnp = of_find_compatible_node(NULL, NULL, \"fsl,ls1021a-dcfg\");\n-\tdcfg_base = of_iomap(np, 0);\n-\tBUG_ON(!dcfg_base);\n-\n-\tpaddr = virt_to_phys(secondary_startup);\n-\twritel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);\n+\tsecondary_pre_boot_entry = ioread32be(dcfg_base +\n+\t\t\t\t\t\tDCFG_CCSR_SCRATCHRW1);\n \n-\tiounmap(dcfg_base);\n+\tls1021a_set_secondary_entry();\n }\n \n struct smp_operations ls1021a_smp_ops __initdata = {\n \t.smp_prepare_cpus\t= ls1021a_smp_prepare_cpus,\n \t.smp_boot_secondary\t= ls1021a_boot_secondary,\n+#ifdef CONFIG_HOTPLUG_CPU\n+\t.cpu_die = ls1021a_cpu_die,\n+\t.cpu_kill = ls1021a_cpu_kill,\n+#endif\n };\n", "prefixes": [ "v3", "1/1" ] }