Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/418986/?format=api
{ "id": 418986, "url": "http://patchwork.ozlabs.org/api/patches/418986/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1418117882-43525-1-git-send-email-b18965@freescale.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1418117882-43525-1-git-send-email-b18965@freescale.com>", "list_archive_url": null, "date": "2014-12-09T09:38:02", "name": "[U-Boot,v2] arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR board", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "1342abdefa4d0d937a5563efdf095e2728a43d33", "submitter": { "id": 13010, "url": "http://patchwork.ozlabs.org/api/people/13010/?format=api", "name": "Alison Wang", "email": "b18965@freescale.com" }, "delegate": { "id": 2666, "url": "http://patchwork.ozlabs.org/api/users/2666/?format=api", "username": "yorksun", "first_name": "York", "last_name": "Sun", "email": "yorksun@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1418117882-43525-1-git-send-email-b18965@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/418986/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/418986/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id CDF2C140082\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 9 Dec 2014 20:39:53 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 047314B622;\n\tTue, 9 Dec 2014 10:39:50 +0100 (CET)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id W+BSa2WARHzH; Tue, 9 Dec 2014 10:39:49 +0100 (CET)", "from theia.denx.de (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id F2C574B600;\n\tTue, 9 Dec 2014 10:39:48 +0100 (CET)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id AD1304B600\n\tfor <u-boot@lists.denx.de>; Tue, 9 Dec 2014 10:39:42 +0100 (CET)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id pTplPvfTO5Um for <u-boot@lists.denx.de>;\n\tTue, 9 Dec 2014 10:39:42 +0100 (CET)", "from na01-bn1-obe.outbound.protection.outlook.com\n\t(mail-bn1bon0138.outbound.protection.outlook.com [157.56.111.138])\n\tby theia.denx.de (Postfix) with ESMTPS id 13B8D4B5FD\n\tfor <u-boot@lists.denx.de>; Tue, 9 Dec 2014 10:39:38 +0100 (CET)", "from BY2PR03CA008.namprd03.prod.outlook.com (10.255.93.25) by\n\tBLUPR03MB152.namprd03.prod.outlook.com (10.255.212.28) with Microsoft\n\tSMTP Server (TLS) id 15.1.31.17; Tue, 9 Dec 2014 09:39:36 +0000", "from BL2FFO11FD026.protection.gbl (10.255.93.4) by\n\tBY2PR03CA008.outlook.office365.com (10.255.93.25) with Microsoft SMTP\n\tServer (TLS) id 15.1.31.17 via Frontend Transport;\n\tTue, 9 Dec 2014 09:39:35 +0000", "from az84smr01.freescale.net (192.88.158.2) by\n\tBL2FFO11FD026.mail.protection.outlook.com (10.173.161.105) with\n\tMicrosoft SMTP Server (TLS) id 15.1.26.17 via Frontend Transport;\n\tTue, 9 Dec 2014 09:39:34 +0000", "from titan.ap.freescale.net ([10.192.208.233])\n\tby az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tsB99dSF6020826; Tue, 9 Dec 2014 02:39:29 -0700" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "Alison Wang <b18965@freescale.com>", "To": "<yorksun@freescale.com>, <u-boot@lists.denx.de>,\n\t<jason.jin@freescale.com>", "Date": "Tue, 9 Dec 2014 17:38:02 +0800", "Message-ID": "<1418117882-43525-1-git-send-email-b18965@freescale.com>", "X-Mailer": "git-send-email 2.1.0.27.g96db324", "X-EOPAttributedMessage": "0", "X-Forefront-Antispam-Report": "CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI;\n\tSFV:NSPM;\n\tSFS:(10019020)(6009001)(189002)(199003)(21056001)(104016003)(50466002)(450100001)(77156002)(62966003)(68736005)(120916001)(50226001)(46102003)(107046002)(97736003)(48376002)(4396001)(107886001)(77096005)(33646002)(99396003)(19580405001)(19580395003)(229853001)(69596002)(31966008)(84676001)(106466001)(81156004)(50986999)(551934003)(105606002)(6806004)(64706001)(47776003)(20776003)(87936001)(92566001)(36756003)(575784001)(2201001)(89996001)(42262002);\n\tDIR:OUT; SFP:1102; SCL:1; SRVR:BLUPR03MB152;\n\tH:az84smr01.freescale.net; FPR:; SPF:Fail; MLV:sfv;\n\tPTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; ", "MIME-Version": "1.0", "X-Microsoft-Antispam": [ "UriScan:;", "BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB152;" ], "X-Exchange-Antispam-Report-Test": "UriScan:;", "X-Exchange-Antispam-Report-CFA-Test": [ "BCL:0; PCL:0; RULEID:(602002);\n\tSRVR:BLUPR03MB152; ", "BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB152;" ], "X-Forefront-PRVS": "0420213CCD", "Received-SPF": "Fail (protection.outlook.com: domain of freescale.com does not\n\tdesignate 192.88.158.2 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.158.2; helo=az84smr01.freescale.net;", "Authentication-Results": "spf=fail (sender IP is 192.88.158.2)\n\tsmtp.mailfrom=alison.wang@freescale.com; ", "X-OriginatorOrg": "freescale.com", "Subject": "[U-Boot] [PATCH v2] arm: ls102xa: Add QSPI boot support for\n\tLS1021AQDS/TWR board", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.13", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "u-boot-bounces@lists.denx.de", "Errors-To": "u-boot-bounces@lists.denx.de" }, "content": "This patch adds QSPI boot support for LS1021AQDS/TWR board.\nThe QSPI boot image need to be programmed into the QSPI flash\nfirst. Then the booting will start from QSPI memory space.\n\nSigned-off-by: Alison Wang <alison.wang@freescale.com>\n---\nChange log:\n v2: Rebase the patch.\n\n arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 +\n board/freescale/ls1021aqds/MAINTAINERS | 1 +\n board/freescale/ls1021aqds/ls1021aqds.c | 8 ++++++\n board/freescale/ls1021atwr/MAINTAINERS | 1 +\n board/freescale/ls1021atwr/ls1021atwr.c | 14 ++++++++++\n configs/ls1021aqds_qspi_defconfig | 3 ++\n configs/ls1021atwr_qspi_defconfig | 3 ++\n include/configs/ls1021aqds.h | 34 +++++++++++++++++++++++\n include/configs/ls1021atwr.h | 28 +++++++++++++++++++\n 9 files changed, 93 insertions(+)\n create mode 100644 configs/ls1021aqds_qspi_defconfig\n create mode 100644 configs/ls1021atwr_qspi_defconfig", "diff": "diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\nindex 44a2c86..d965426 100644\n--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\n+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\n@@ -101,6 +101,7 @@ struct ccsr_gur {\n #define SCFG_ETSECDMAMCR_LE_BD_FR\t0xf8001a0f\n #define SCFG_ETSECCMCR_GE2_CLK125\t0x04000000\n #define SCFG_PIXCLKCR_PXCKEN\t\t0x80000000\n+#define SCFG_QSPI_CLKSEL\t\t0xc0100000\n \n /* Supplemental Configuration Unit */\n struct ccsr_scfg {\ndiff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS\nindex 962176b..7a704cf 100644\n--- a/board/freescale/ls1021aqds/MAINTAINERS\n+++ b/board/freescale/ls1021aqds/MAINTAINERS\n@@ -7,3 +7,4 @@ F:\tconfigs/ls1021aqds_nor_defconfig\n F:\tconfigs/ls1021aqds_ddr4_nor_defconfig\n F:\tconfigs/ls1021aqds_nor_SECURE_BOOT_defconfig\n F:\tconfigs/ls1021aqds_sdcard_defconfig\n+F:\tconfigs/ls1021aqds_qspi_defconfig\ndiff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c\nindex 3d6292e..56635f9 100644\n--- a/board/freescale/ls1021aqds/ls1021aqds.c\n+++ b/board/freescale/ls1021aqds/ls1021aqds.c\n@@ -50,7 +50,9 @@ enum {\n \n int checkboard(void)\n {\n+#ifndef CONFIG_QSPI_BOOT\n \tchar buf[64];\n+#endif\n #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)\n \tu8 sw;\n #endif\n@@ -77,12 +79,14 @@ int checkboard(void)\n \t\tprintf(\"invalid setting of SW%u\\n\", QIXIS_LBMAP_SWITCH);\n #endif\n \n+#ifndef CONFIG_QSPI_BOOT\n \tprintf(\"Sys ID:0x%02x, Sys Ver: 0x%02x\\n\",\n \t QIXIS_READ(id), QIXIS_READ(arch));\n \n \tprintf(\"FPGA: v%d (%s), build %d\\n\",\n \t (int)QIXIS_READ(scver), qixis_read_tag(buf),\n \t (int)qixis_read_minor());\n+#endif\n \n \treturn 0;\n }\n@@ -180,6 +184,10 @@ int board_early_init_f(void)\n \tinit_early_memctl_regs();\n #endif\n \n+#ifdef CONFIG_FSL_QSPI\n+\tout_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);\n+#endif\n+\n \t/* Workaround for the issue that DDR could not respond to\n \t * barrier transaction which is generated by executing DSB/ISB\n \t * instruction. Set CCI-400 control override register to\ndiff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS\nindex 2312e00..9176706 100644\n--- a/board/freescale/ls1021atwr/MAINTAINERS\n+++ b/board/freescale/ls1021atwr/MAINTAINERS\n@@ -6,3 +6,4 @@ F:\tinclude/configs/ls1021atwr.h\n F:\tconfigs/ls1021atwr_nor_defconfig\n F:\tconfigs/ls1021atwr_nor_SECURE_BOOT_defconfig\n F:\tconfigs/ls1021atwr_sdcard_defconfig\n+F:\tconfigs/ls1021atwr_qspi_defconfig\ndiff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c\nindex 6f6196b..8ab229d 100644\n--- a/board/freescale/ls1021atwr/ls1021atwr.c\n+++ b/board/freescale/ls1021atwr/ls1021atwr.c\n@@ -74,6 +74,7 @@ struct cpld_data {\n \tu8 rev2;\t\t/* Reserved */\n };\n \n+#ifndef CONFIG_QSPI_BOOT\n static void convert_serdes_mux(int type, int need_reset);\n \n void cpld_show(void)\n@@ -109,11 +110,14 @@ void cpld_show(void)\n \t in_8(&cpld_data->serdes_mux));\n #endif\n }\n+#endif\n \n int checkboard(void)\n {\n \tputs(\"Board: LS1021ATWR\\n\");\n+#ifndef CONFIG_QSPI_BOOT\n \tcpld_show();\n+#endif\n \n \treturn 0;\n }\n@@ -222,6 +226,7 @@ int board_eth_init(bd_t *bis)\n }\n #endif\n \n+#ifndef CONFIG_QSPI_BOOT\n int config_serdes_mux(void)\n {\n \tstruct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);\n@@ -253,6 +258,7 @@ int config_serdes_mux(void)\n \n \treturn 0;\n }\n+#endif\n \n int board_early_init_f(void)\n {\n@@ -271,6 +277,10 @@ int board_early_init_f(void)\n \tout_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);\n #endif\n \n+#ifdef CONFIG_FSL_QSPI\n+\tout_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);\n+#endif\n+\n \treturn 0;\n }\n \n@@ -410,8 +420,10 @@ int board_init(void)\n \n #ifndef CONFIG_SYS_FSL_NO_SERDES\n \tfsl_serdes_init();\n+#ifndef CONFIG_QSPI_BOOT\n \tconfig_serdes_mux();\n #endif\n+#endif\n \n \tls102xa_config_smmu_stream_id(dev_stream_id,\n \t\t\t\t ARRAY_SIZE(dev_stream_id));\n@@ -466,6 +478,7 @@ u16 flash_read16(void *addr)\n \treturn (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);\n }\n \n+#ifndef CONFIG_QSPI_BOOT\n static void convert_flash_bank(char bank)\n {\n \tstruct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);\n@@ -648,3 +661,4 @@ U_BOOT_CMD(\n \t\"\t-change lane C & lane D to PCIeX2\\n\"\n \t\"\\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\\n\"\n );\n+#endif\ndiff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig\nnew file mode 100644\nindex 0000000..05ec8e6\n--- /dev/null\n+++ b/configs/ls1021aqds_qspi_defconfig\n@@ -0,0 +1,3 @@\n+CONFIG_SYS_EXTRA_OPTIONS=\"QSPI_BOOT\"\n++S:CONFIG_ARM=y\n++S:CONFIG_TARGET_LS1021AQDS=y\ndiff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig\nnew file mode 100644\nindex 0000000..611f6e8\n--- /dev/null\n+++ b/configs/ls1021atwr_qspi_defconfig\n@@ -0,0 +1,3 @@\n+CONFIG_SYS_EXTRA_OPTIONS=\"QSPI_BOOT\"\n++S:CONFIG_ARM=y\n++S:CONFIG_TARGET_LS1021ATWR=y\ndiff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h\nindex 6a6f620..653dbef 100644\n--- a/include/configs/ls1021aqds.h\n+++ b/include/configs/ls1021aqds.h\n@@ -37,8 +37,14 @@ unsigned long get_board_sys_clk(void);\n unsigned long get_board_ddr_clk(void);\n #endif\n \n+#ifdef CONFIG_QSPI_BOOT\n+#define CONFIG_SYS_CLK_FREQ\t\t100000000\n+#define CONFIG_DDR_CLK_FREQ\t\t100000000\n+#define CONFIG_QIXIS_I2C_ACCESS\n+#else\n #define CONFIG_SYS_CLK_FREQ\t\tget_board_sys_clk()\n #define CONFIG_DDR_CLK_FREQ\t\tget_board_ddr_clk()\n+#endif\n \n #ifdef CONFIG_RAMBOOT_PBL\n #define CONFIG_SYS_FSL_PBL_PBI\tboard/freescale/ls1021aqds/ls102xa_pbi.cfg\n@@ -73,6 +79,11 @@ unsigned long get_board_ddr_clk(void);\n #define CONFIG_SYS_MONITOR_LEN\t\t0x80000\n #endif\n \n+#ifdef CONFIG_QSPI_BOOT\n+#define CONFIG_SYS_TEXT_BASE\t\t0x40010000\n+#define CONFIG_SYS_NO_FLASH\n+#endif\n+\n #ifndef CONFIG_SYS_TEXT_BASE\n #define CONFIG_SYS_TEXT_BASE\t\t0x67f80000\n #endif\n@@ -112,6 +123,7 @@ unsigned long get_board_ddr_clk(void);\n /*\n * IFC Definitions\n */\n+#ifndef CONFIG_QSPI_BOOT\n #define CONFIG_FSL_IFC\n #define CONFIG_SYS_FLASH_BASE\t\t0x60000000\n #define CONFIG_SYS_FLASH_BASE_PHYS\tCONFIG_SYS_FLASH_BASE\n@@ -204,6 +216,7 @@ unsigned long get_board_ddr_clk(void);\n #define CONFIG_CMD_NAND\n \n #define CONFIG_SYS_NAND_BLOCK_SIZE\t(128 * 1024)\n+#endif\n \n /*\n * QIXIS Definitions\n@@ -316,6 +329,18 @@ unsigned long get_board_ddr_clk(void);\n #define CONFIG_CMD_FAT\n #define CONFIG_DOS_PARTITION\n \n+/* QSPI */\n+#ifdef CONFIG_QSPI_BOOT\n+#define CONFIG_FSL_QSPI\n+#define QSPI0_AMBA_BASE\t\t\t0x40000000\n+#define FSL_QSPI_FLASH_SIZE\t\t(1 << 24)\n+#define FSL_QSPI_FLASH_NUM\t\t2\n+\n+#define CONFIG_CMD_SF\n+#define CONFIG_SPI_FLASH\n+#define CONFIG_SPI_FLASH_SPANSION\n+#endif\n+\n /*\n * USB\n */\n@@ -394,7 +419,11 @@ unsigned long get_board_ddr_clk(void);\n #define CONFIG_CMDLINE_TAG\n #define CONFIG_CMDLINE_EDITING\n \n+#ifdef CONFIG_QSPI_BOOT\n+#undef CONFIG_CMD_IMLS\n+#else\n #define CONFIG_CMD_IMLS\n+#endif\n \n #define CONFIG_ARMV7_NONSEC\n #define CONFIG_ARMV7_VIRT\n@@ -468,6 +497,11 @@ unsigned long get_board_ddr_clk(void);\n #define CONFIG_ENV_IS_IN_MMC\n #define CONFIG_SYS_MMC_ENV_DEV\t\t0\n #define CONFIG_ENV_SIZE\t\t\t0x2000\n+#elif defined(CONFIG_QSPI_BOOT)\n+#define CONFIG_ENV_IS_IN_SPI_FLASH\n+#define CONFIG_ENV_SIZE\t\t\t0x2000 /* 8KB */\n+#define CONFIG_ENV_OFFSET\t\t0x100000 /* 1MB */\n+#define CONFIG_ENV_SECT_SIZE\t\t0x10000\n #else\n #define CONFIG_ENV_IS_IN_FLASH\n #define CONFIG_ENV_ADDR\t\t(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)\ndiff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h\nindex 9a497a6..2713ae4 100644\n--- a/include/configs/ls1021atwr.h\n+++ b/include/configs/ls1021atwr.h\n@@ -95,6 +95,11 @@\n #define CONFIG_SYS_MONITOR_LEN\t\t0x80000\n #endif\n \n+#ifdef CONFIG_QSPI_BOOT\n+#define CONFIG_SYS_TEXT_BASE\t\t0x40010000\n+#define CONFIG_SYS_NO_FLASH\n+#endif\n+\n #ifndef CONFIG_SYS_TEXT_BASE\n #define CONFIG_SYS_TEXT_BASE\t\t0x67f80000\n #endif\n@@ -118,6 +123,7 @@\n /*\n * IFC Definitions\n */\n+#ifndef CONFIG_QSPI_BOOT\n #define CONFIG_FSL_IFC\n #define CONFIG_SYS_FLASH_BASE\t\t0x60000000\n #define CONFIG_SYS_FLASH_BASE_PHYS\tCONFIG_SYS_FLASH_BASE\n@@ -161,6 +167,7 @@\n \n #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS\n #define CONFIG_SYS_WRITE_SWAPPED_DATA\n+#endif\n \n /* CPLD */\n \n@@ -244,6 +251,18 @@\n #define CONFIG_CMD_FAT\n #define CONFIG_DOS_PARTITION\n \n+/* QSPI */\n+#ifdef CONFIG_QSPI_BOOT\n+#define CONFIG_FSL_QSPI\n+#define QSPI0_AMBA_BASE\t\t\t0x40000000\n+#define FSL_QSPI_FLASH_SIZE\t\t(1 << 24)\n+#define FSL_QSPI_FLASH_NUM\t\t2\n+\n+#define CONFIG_CMD_SF\n+#define CONFIG_SPI_FLASH\n+#define CONFIG_SPI_FLASH_STMICRO\n+#endif\n+\n /*\n * Video\n */\n@@ -315,7 +334,11 @@\n #define CONFIG_CMDLINE_TAG\n #define CONFIG_CMDLINE_EDITING\n \n+#ifdef CONFIG_QSPI_BOOT\n+#undef CONFIG_CMD_IMLS\n+#else\n #define CONFIG_CMD_IMLS\n+#endif\n \n #define CONFIG_ARMV7_NONSEC\n #define CONFIG_ARMV7_VIRT\n@@ -388,6 +411,11 @@\n #define CONFIG_ENV_IS_IN_MMC\n #define CONFIG_SYS_MMC_ENV_DEV\t\t0\n #define CONFIG_ENV_SIZE\t\t\t0x20000\n+#elif defined(CONFIG_QSPI_BOOT)\n+#define CONFIG_ENV_IS_IN_SPI_FLASH\n+#define CONFIG_ENV_SIZE\t\t\t0x2000\n+#define CONFIG_ENV_OFFSET\t\t0x100000\n+#define CONFIG_ENV_SECT_SIZE\t\t0x10000\n #else\n #define CONFIG_ENV_IS_IN_FLASH\n #define CONFIG_ENV_ADDR\t\t(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)\n", "prefixes": [ "U-Boot", "v2" ] }