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GET /api/patches/418908/?format=api
{ "id": 418908, "url": "http://patchwork.ozlabs.org/api/patches/418908/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1418081455-2192-1-git-send-email-yorksun@freescale.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1418081455-2192-1-git-send-email-yorksun@freescale.com>", "list_archive_url": null, "date": "2014-12-08T23:30:55", "name": "[U-Boot] arm/ls1021a: Add workaround for DDR erratum A008378", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "b69e2cc594352960446fe097820b4381b55c577d", "submitter": { "id": 3777, "url": "http://patchwork.ozlabs.org/api/people/3777/?format=api", "name": "York Sun", "email": "yorksun@freescale.com" }, "delegate": { "id": 2666, "url": "http://patchwork.ozlabs.org/api/users/2666/?format=api", "username": "yorksun", "first_name": "York", "last_name": "Sun", "email": "yorksun@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1418081455-2192-1-git-send-email-yorksun@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/418908/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/418908/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id 609F71400D5\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 9 Dec 2014 10:31:19 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 650944B622;\n\tTue, 9 Dec 2014 00:31:15 +0100 (CET)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id YjQdtFHOWWhQ; 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Mon, 8 Dec 2014 16:31:01 -0700" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "York Sun <yorksun@freescale.com>", "To": "<u-boot@lists.denx.de>", "Date": "Mon, 8 Dec 2014 15:30:55 -0800", "Message-ID": "<1418081455-2192-1-git-send-email-yorksun@freescale.com>", "X-Mailer": "git-send-email 1.7.9.5", "X-EOPAttributedMessage": "0", "X-Forefront-Antispam-Report": "CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI;\n\tSFV:NSPM;\n\tSFS:(10019020)(6009001)(199003)(189002)(69596002)(64706001)(68736005)(62966003)(77156002)(77096005)(450100001)(36756003)(19580395003)(92566001)(97736003)(6806004)(20776003)(50226001)(48376002)(47776003)(89996001)(87936001)(50466002)(31966008)(21056001)(86362001)(105606002)(104016003)(33646002)(99396003)(19580405001)(4396001)(110136001)(46102003)(2351001)(229853001)(107046002)(106466001)(120916001)(81156004)(50986999)(84676001);\n\tDIR:OUT; SFP:1102; SCL:1; SRVR:BL2PR03MB147;\n\tH:az84smr01.freescale.net; FPR:; SPF:Fail; MLV:sfv;\n\tPTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; ", "MIME-Version": "1.0", "X-Microsoft-Antispam": [ "UriScan:;", "BCL:0;PCL:0;RULEID:;SRVR:BL2PR03MB147;" ], "X-Exchange-Antispam-Report-Test": "UriScan:;", "X-Exchange-Antispam-Report-CFA-Test": [ "BCL:0; PCL:0; RULEID:(602002);\n\tSRVR:BL2PR03MB147; ", "BCL:0;PCL:0;RULEID:;SRVR:BL2PR03MB147;" ], "X-Forefront-PRVS": "041963B986", "Received-SPF": "Fail (protection.outlook.com: domain of freescale.com does not\n\tdesignate 192.88.158.2 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.158.2; helo=az84smr01.freescale.net;", "Authentication-Results": "spf=fail (sender IP is 192.88.158.2)\n\tsmtp.mailfrom=yorksun@freescale.com; ", "X-OriginatorOrg": "freescale.com", "Cc": "York Sun <yorksun@freescale.com>", "Subject": "[U-Boot] [PATCH] arm/ls1021a: Add workaround for DDR erratum A008378", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.13", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "u-boot-bounces@lists.denx.de", "Errors-To": "u-boot-bounces@lists.denx.de" }, "content": "Internal memory controller counters can reach a bad state after\ntraining in DDR4 mode if accumulated ECC or DBI mode is eanbled.\n\nSigned-off-by: York Sun <yorksun@freescale.com>\n---\n arch/arm/include/asm/arch-ls102xa/config.h | 1 +\n drivers/ddr/fsl/fsl_ddr_gen4.c | 8 ++++++++\n 2 files changed, 9 insertions(+)", "diff": "diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h\nindex ba86eea..7bd3d2f 100644\n--- a/arch/arm/include/asm/arch-ls102xa/config.h\n+++ b/arch/arm/include/asm/arch-ls102xa/config.h\n@@ -88,6 +88,7 @@\n #define CONFIG_SYS_FSL_DDR_VER\t\t\tFSL_DDR_VER_5_0\n #define CONFIG_SYS_FSL_SEC_COMPAT\t\t5\n #define CONFIG_USB_MAX_CONTROLLER_COUNT\t\t1\n+#define CONFIG_SYS_FSL_ERRATUM_A008378\n #else\n #error SoC not defined\n #endif\ndiff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c\nindex e024db9..43b454a 100644\n--- a/drivers/ddr/fsl/fsl_ddr_gen4.c\n+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c\n@@ -157,6 +157,14 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,\n \t\t\tddr_out32(&ddr->debug[i], regs->debug[i]);\n \t\t}\n \t}\n+#ifdef CONFIG_SYS_FSL_ERRATUM_A008378\n+\t/* Erratum applies when accumulated ECC is used, or DBI is enabled */\n+#define IS_ACC_ECC_EN(v) (v & 0x4)\n+#define IS_DBI(v) ((v >> 12) & 0x3 == 0x2)\n+\tif (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||\n+\t IS_DBI(regs->ddr_sdram_cfg_3))\n+\t\tddr_setbits32(ddr->debug[28], 0x9 << 20);\n+#endif\n \n \t/*\n \t * For RDIMMs, JEDEC spec requires clocks to be stable before reset is\n", "prefixes": [ "U-Boot" ] }