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GET /api/patches/413548/?format=api
{ "id": 413548, "url": "http://patchwork.ozlabs.org/api/patches/413548/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/patch/1416806890-26920-1-git-send-email-Zhuoyu.Zhang@freescale.com/", "project": { "id": 19, "url": "http://patchwork.ozlabs.org/api/projects/19/?format=api", "name": "Linux IMX development", "link_name": "linux-imx", "list_id": "linux-imx-kernel.lists.patchwork.ozlabs.org", "list_email": "linux-imx-kernel@lists.patchwork.ozlabs.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1416806890-26920-1-git-send-email-Zhuoyu.Zhang@freescale.com>", "list_archive_url": null, "date": "2014-11-24T05:28:09", "name": "[v2,1/2] arm: ls1: add CPU hotplug platform support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "79c8eb597f5a5d98052ed46d76907cf6b6738d83", "submitter": { "id": 42926, "url": "http://patchwork.ozlabs.org/api/people/42926/?format=api", "name": "Zhuoyu Zhang", "email": "Zhuoyu.Zhang@freescale.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-imx/patch/1416806890-26920-1-git-send-email-Zhuoyu.Zhang@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/413548/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/413548/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming-imx@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-imx@bilbo.ozlabs.org", "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n\t[IPv6:2001:1868:205::9])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 1B8B4140161\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tMon, 24 Nov 2014 16:32:48 +1100 (AEDT)", "from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux))\n\tid 1XsmDk-0001Mb-2N; Mon, 24 Nov 2014 05:29:56 +0000", "from mail-bn1on0132.outbound.protection.outlook.com\n\t([157.56.110.132] helo=na01-bn1-obe.outbound.protection.outlook.com)\n\tby bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat\n\tLinux)) id 1XsmDg-0001M0-Ii\n\tfor linux-arm-kernel@lists.infradead.org;\n\tMon, 24 Nov 2014 05:29:53 +0000", "from BY2PR03CA048.namprd03.prod.outlook.com (10.141.249.21) by\n\tBLUPR03MB392.namprd03.prod.outlook.com (10.141.78.28) with Microsoft\n\tSMTP Server (TLS) id 15.1.26.15; Mon, 24 Nov 2014 05:29:29 +0000", "from BY2FFO11FD013.protection.gbl (2a01:111:f400:7c0c::155) by\n\tBY2PR03CA048.outlook.office365.com (2a01:111:e400:2c5d::21) with\n\tMicrosoft SMTP Server (TLS) id 15.1.26.15 via Frontend Transport;\n\tMon, 24 Nov 2014 05:29:28 +0000", "from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBY2FFO11FD013.mail.protection.outlook.com (10.1.14.75) with Microsoft\n\tSMTP Server (TLS) id 15.1.6.13 via Frontend Transport;\n\tMon, 24 Nov 2014 05:29:28 +0000", "from titan.ap.freescale.net ([10.192.208.233])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tsAO5TNdD026676; Sun, 23 Nov 2014 22:29:24 -0700" ], "From": "Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com>", "To": "<linux-kernel@vger.kernel.org>, <kernel@pengutronix.de>,\n\t<linux-arm-kernel@lists.infradead.org>", "Subject": "[PATCH v2 1/2] arm: ls1: add CPU hotplug platform support", "Date": "Mon, 24 Nov 2014 13:28:09 +0800", "Message-ID": "<1416806890-26920-1-git-send-email-Zhuoyu.Zhang@freescale.com>", "X-Mailer": "git-send-email 2.1.0.27.g96db324", "X-EOPAttributedMessage": "0", "Received-SPF": "Fail (protection.outlook.com: domain of freescale.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=Zhuoyu.Zhang@freescale.com; ", "X-Forefront-Antispam-Report": "CIP:192.88.168.50; CTRY:US; IPV:NLI; EFV:NLI;\n\tSFV:NSPM;\n\tSFS:(10019020)(6009001)(199003)(189002)(229853001)(105606002)(36756003)(62966003)(77156002)(107046002)(120916001)(99396003)(50466002)(106466001)(104016003)(21056001)(95666004)(87936001)(88136002)(4396001)(64706001)(89996001)(102836001)(31966008)(92726001)(92566001)(104166001)(2201001)(85426001)(93916002)(86362001)(84676001)(575784001)(87286001)(46102003)(97736003)(50986999)(6806004)(50226001)(19580405001)(19580395003)(47776003)(44976005)(68736004)(20776003);\n\tDIR:OUT; SFP:1102; SCL:1; SRVR:BLUPR03MB392;\n\tH:tx30smr01.am.freescale.net; \n\tFPR:; SPF:Fail; MLV:sfv; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en;", "MIME-Version": "1.0", "X-Microsoft-Antispam": [ "UriScan:;", "BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB392;" ], "X-Exchange-Antispam-Report-Test": "UriScan:;", "X-Exchange-Antispam-Report-CFA-Test": [ "BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB392;", "BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB392;" ], "X-Forefront-PRVS": "040513D301", "X-OriginatorOrg": "freescale.com", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20141123_212952_846332_06E7F15D ", "X-CRM114-Status": "GOOD ( 15.97 )", "X-Spam-Score": "-0.0 (/)", "X-Spam-Report": "SpamAssassin version 3.4.0 on bombadil.infradead.org summary:\n\tContent analysis details: (-0.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [157.56.110.132 listed in list.dnswl.org]\n\t-0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2)\n\t[157.56.110.132 listed in wl.mailspike.net]\n\t-0.0 SPF_HELO_PASS SPF: HELO matches SPF record\n\t-0.0 SPF_PASS SPF: sender matches SPF record", "Cc": "Zhuoyu.Zhang@freescale.com, leoli@freescale.com,\n\tlinuxppc-release@linux.freescale.net, Jason.Jin@freescale.com,\n\tchenhui.zhao@freescale.com", "X-BeenThere": "linux-arm-kernel@lists.infradead.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-arm-kernel/>", "List-Post": "<mailto:linux-arm-kernel@lists.infradead.org>", "List-Help": "<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>", "Errors-To": "linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org", "List-Id": "linux-imx-kernel.lists.patchwork.ozlabs.org" }, "content": "From: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com>\n\nThis implements CPU hotplug for ls1. When cpu is down, it will be put\nin WFI state. When cpu is up, it will always soft reset and boots up\nthe same path as a cold boot.\n\nSigned-off-by: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com>\n---\n arch/arm/mach-imx/common.h | 4 ++\n arch/arm/mach-imx/hotplug.c | 25 +++++++++\n arch/arm/mach-imx/platsmp.c | 132 +++++++++++++++++++++++++++++++++++++++-----\n arch/arm/mach-imx/src.c | 21 +++++++\n 4 files changed, 169 insertions(+), 13 deletions(-)", "diff": "diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h\nindex 59ce8f3..f7d2be5 100644\n--- a/arch/arm/mach-imx/common.h\n+++ b/arch/arm/mach-imx/common.h\n@@ -92,6 +92,7 @@ void imx_print_silicon_rev(const char *cpu, int srev);\n void imx_enable_cpu(int cpu, bool enable);\n void imx_set_cpu_jump(int cpu, void *jump_addr);\n u32 imx_get_cpu_arg(int cpu);\n+u32 ls1_get_cpu_arg(int cpu);\n void imx_set_cpu_arg(int cpu, u32 arg);\n #ifdef CONFIG_SMP\n void v7_secondary_startup(void);\n@@ -134,6 +135,9 @@ void imx6sl_pm_init(void);\n void imx6sx_pm_init(void);\n void imx6q_pm_set_ccm_base(void __iomem *base);\n \n+extern void ls1021a_cpu_die(unsigned int cpu);\n+extern int ls1021a_cpu_kill(unsigned int cpu);\n+\n #ifdef CONFIG_PM\n void imx51_pm_init(void);\n void imx53_pm_init(void);\ndiff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c\nindex b35e99c..2ee5e46 100644\n--- a/arch/arm/mach-imx/hotplug.c\n+++ b/arch/arm/mach-imx/hotplug.c\n@@ -14,6 +14,7 @@\n #include <linux/jiffies.h>\n #include <asm/cp15.h>\n #include <asm/proc-fns.h>\n+#include <asm/cacheflush.h>\n \n #include \"common.h\"\n \n@@ -68,3 +69,27 @@ int imx_cpu_kill(unsigned int cpu)\n \timx_set_cpu_arg(cpu, 0);\n \treturn 1;\n }\n+\n+/*\n+ * For LS102x platforms, shutdowning a CPU is not supported by hardware.\n+ * So we just put the offline CPU into lower-power state here.\n+ */\n+void __ref ls1021a_cpu_die(unsigned int cpu)\n+{\n+\tv7_exit_coherency_flush(louis);\n+\n+\t/* LS1021a platform can't really power down a CPU, so we\n+\t * just put it into WFI state here.\n+\t */\n+\twfi();\n+}\n+\n+int ls1021a_cpu_kill(unsigned int cpu)\n+{\n+\tunsigned long timeout = jiffies + msecs_to_jiffies(50);\n+\n+\twhile (!ls1_get_cpu_arg(cpu))\n+\t\tif (time_after(jiffies, timeout))\n+\t\t\treturn 0;\n+\treturn 1;\n+}\ndiff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c\nindex 7f27001..7735ebb 100644\n--- a/arch/arm/mach-imx/platsmp.c\n+++ b/arch/arm/mach-imx/platsmp.c\n@@ -14,6 +14,7 @@\n #include <linux/of_address.h>\n #include <linux/of.h>\n #include <linux/smp.h>\n+#include <linux/delay.h>\n \n #include <asm/cacheflush.h>\n #include <asm/page.h>\n@@ -23,8 +24,24 @@\n #include \"common.h\"\n #include \"hardware.h\"\n \n+#define\tSCFG_CORE0_SFT_RST\t0x130\n+#define\tSCFG_REVCR\t\t0x200\n+#define\tSCFG_CORESRENCR\t\t0x204\n+#define\tSCFG_SPARECR4\t\t0x50C\n+\n+#define\tDCFG_CCSR_BRR\t\t0x0E4\n+#define\tDCFG_CCSR_SCRATCHRW1\t0x200\n+\n+#define\tDCSR_RCPM2_DEBUG1\t0x400\n+#define\tDCSR_RCPM2_DEBUG2\t0x414\n+\n+#define\tSTRIDE_4B\t\t4\n+\n u32 g_diag_reg;\n static void __iomem *scu_base;\n+static void __iomem *dcfg_base;\n+static void __iomem *scfg_base;\n+static u32 secondary_pre_boot_entry;\n \n static struct map_desc scu_io_desc __initdata = {\n \t/* .virtual and .pfn are run-time assigned */\n@@ -98,32 +115,121 @@ struct smp_operations imx_smp_ops __initdata = {\n #endif\n };\n \n-#define DCFG_CCSR_SCRATCHRW1\t0x200\n-\n-static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)\n+static int ls1021a_secondary_iomap(void)\n {\n-\tarch_send_wakeup_ipi_mask(cpumask_of(cpu));\n+\tstruct device_node *np;\n+\tint ret;\n+\n+\tnp = of_find_compatible_node(NULL, NULL, \"fsl,ls1021a-dcfg\");\n+\tif (!np) {\n+\t\tpr_err(\"%s: failed to find dcfg node.\\n\", __func__);\n+\t\tret = -EINVAL;\n+\t\tgoto dcfg_err;\n+\t}\n+\n+\tdcfg_base = of_iomap(np, 0);\n+\tof_node_put(np);\n+\tif (!dcfg_base) {\n+\t\tpr_err(\"%s: failed to map dcfg.\\n\", __func__);\n+\t\tret = -ENOMEM;\n+\t\tgoto dcfg_err;\n+\t}\n+\n+\tnp = of_find_compatible_node(NULL, NULL, \"fsl,ls1021a-scfg\");\n+\tif (!np) {\n+\t\tpr_err(\"%s: failed to find scfg node.\\n\", __func__);\n+\t\tret = -EINVAL;\n+\t\tgoto scfg_err;\n+\t}\n+\n+\tscfg_base = of_iomap(np, 0);\n+\tof_node_put(np);\n+\tif (!scfg_base) {\n+\t\tpr_err(\"%s: failed to map scfg.\\n\", __func__);\n+\t\tret = -ENOMEM;\n+\t\tgoto scfg_err;\n+\t}\n \n \treturn 0;\n+\n+scfg_err:\n+\tiounmap(dcfg_base);\n+dcfg_err:\n+\treturn ret;\n }\n \n-static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)\n+void ls1021a_set_secondary_entry(void)\n {\n-\tstruct device_node *np;\n-\tvoid __iomem *dcfg_base;\n \tunsigned long paddr;\n \n-\tnp = of_find_compatible_node(NULL, NULL, \"fsl,ls1021a-dcfg\");\n-\tdcfg_base = of_iomap(np, 0);\n-\tBUG_ON(!dcfg_base);\n+\tsecondary_pre_boot_entry = readl_relaxed(dcfg_base +\n+\t\t\t\t\t\tDCFG_CCSR_SCRATCHRW1);\n \n-\tpaddr = virt_to_phys(secondary_startup);\n-\twritel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);\n+\tif (dcfg_base) {\n+\t\tpaddr = virt_to_phys(secondary_startup);\n+\t\twritel_relaxed(cpu_to_be32(paddr),\n+\t\t\t\tdcfg_base + DCFG_CCSR_SCRATCHRW1);\n+\t}\n+}\n \n-\tiounmap(dcfg_base);\n+static int ls1021a_reset_secondary(unsigned int cpu)\n+{\n+\tu32 tmp;\n+\n+\tif (!scfg_base || !dcfg_base)\n+\t\treturn -ENOMEM;\n+\n+\twritel_relaxed(secondary_pre_boot_entry,\n+\t\t\tdcfg_base + DCFG_CCSR_SCRATCHRW1);\n+\n+\t/* Apply LS1021A specific to write to the BE SCFG space */\n+\ttmp = ioread32be(scfg_base + SCFG_REVCR);\n+\tiowrite32be(0xffffffff, scfg_base + SCFG_REVCR);\n+\n+\t/* Soft reset secondary core */\n+\tiowrite32be(0x80000000, scfg_base + SCFG_CORESRENCR);\n+\tiowrite32be(0x80000000, scfg_base +\n+\t\t\t\tSCFG_CORE0_SFT_RST + STRIDE_4B * cpu);\n+\n+\t/* Release secondary core */\n+\tiowrite32be(1 << cpu, dcfg_base + DCFG_CCSR_BRR);\n+\n+\tls1021a_set_secondary_entry();\n+\n+\t/* Disable core soft reset register */\n+\tiowrite32be(0x0, scfg_base + SCFG_CORESRENCR);\n+\n+\t/* Revert back to the default */\n+\tiowrite32be(tmp, scfg_base + SCFG_REVCR);\n+\n+\treturn 0;\n+}\n+\n+static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)\n+{\n+\tint ret = 0;\n+\n+\tif (system_state == SYSTEM_RUNNING)\n+\t\tret = ls1021a_reset_secondary(cpu);\n+\n+\tudelay(1);\n+\n+\tarch_send_wakeup_ipi_mask(cpumask_of(cpu));\n+\n+\treturn ret;\n+}\n+\n+static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)\n+{\n+\tls1021a_secondary_iomap();\n+\tls1021a_set_secondary_entry();\n }\n \n struct smp_operations ls1021a_smp_ops __initdata = {\n \t.smp_prepare_cpus\t= ls1021a_smp_prepare_cpus,\n \t.smp_boot_secondary\t= ls1021a_boot_secondary,\n+#ifdef CONFIG_HOTPLUG_CPU\n+\t.cpu_die = ls1021a_cpu_die,\n+\t.cpu_kill = ls1021a_cpu_kill,\n+#endif\n };\ndiff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c\nindex 45f7f4e..7bd403a 100644\n--- a/arch/arm/mach-imx/src.c\n+++ b/arch/arm/mach-imx/src.c\n@@ -30,6 +30,8 @@\n #define BP_SRC_SCR_CORE1_RST\t\t14\n #define BP_SRC_SCR_CORE1_ENABLE\t\t22\n \n+#define CCSR_TWAITSR0 0x04C\n+\n static void __iomem *src_base;\n static DEFINE_SPINLOCK(scr_lock);\n \n@@ -115,6 +117,25 @@ void imx_set_cpu_arg(int cpu, u32 arg)\n \twritel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4);\n }\n \n+u32 ls1_get_cpu_arg(int cpu)\n+{\n+\tstruct device_node *np;\n+\tvoid __iomem *ls1_rcpm_base;\n+\n+\tnp = of_find_compatible_node(NULL, NULL, \"fsl,qoriq-rcpm-2.1\");\n+\tif (!np) {\n+\t\tpr_err(\"%s(): Can not find the RCPM node.\\n\", __func__);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tls1_rcpm_base = of_iomap(np, 0);\n+\tof_node_put(np);\n+\tWARN_ON(!ls1_rcpm_base);\n+\n+\tcpu = cpu_logical_map(cpu);\n+\treturn ioread32be(ls1_rcpm_base + CCSR_TWAITSR0) & (1 << cpu);\n+}\n+\n void __init imx_src_init(void)\n {\n \tstruct device_node *np;\n", "prefixes": [ "v2", "1/2" ] }