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GET /api/patches/404895/?format=api
{ "id": 404895, "url": "http://patchwork.ozlabs.org/api/patches/404895/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1414650411-13365-1-git-send-email-b44548@freescale.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1414650411-13365-1-git-send-email-b44548@freescale.com>", "list_archive_url": null, "date": "2014-10-30T06:26:51", "name": "[U-Boot] arm:ls1021a:configure ls1021 scfg for QSPI", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "95c4713478c788bdc3676ee2b40e21675f7df707", "submitter": { "id": 46493, "url": "http://patchwork.ozlabs.org/api/people/46493/?format=api", "name": "Chao Fu", "email": "b44548@freescale.com" }, "delegate": { "id": 2666, "url": "http://patchwork.ozlabs.org/api/users/2666/?format=api", "username": "yorksun", "first_name": "York", "last_name": "Sun", "email": "yorksun@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1414650411-13365-1-git-send-email-b44548@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/404895/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/404895/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id D8192140080\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 30 Oct 2014 18:16:35 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 3C3204B9C3;\n\tThu, 30 Oct 2014 08:16:33 +0100 (CET)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id ariIgaM4v2Fj; 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Thu, 30 Oct 2014 00:16:15 -0700" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "Chao Fu <b44548@freescale.com>", "To": "<albert.u.boot@aribaud.net>, <yorksun@freescale.com>", "Date": "Thu, 30 Oct 2014 14:26:51 +0800", "Message-ID": "<1414650411-13365-1-git-send-email-b44548@freescale.com>", "X-Mailer": "git-send-email 1.8.4", "X-EOPAttributedMessage": "0", "X-Forefront-Antispam-Report": "CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI;\n\tEFV:NLI; SFV:NSPM;\n\tSFS:(10019020)(6009001)(189002)(199003)(88136002)(89996001)(92566001)(92726001)(93916002)(575784001)(86362001)(106466001)(87286001)(48376002)(84676001)(76482002)(64706001)(85852003)(36756003)(85306004)(50466002)(87936001)(105606002)(104166001)(77156001)(229853001)(47776003)(62966002)(120916001)(31966008)(95666004)(4396001)(50986999)(21056001)(44976005)(99396003)(6806004)(19580405001)(46102003)(107046002)(80022003)(68736004)(20776003)(551934003)(26826002)(102836001)(104016003)(97736003)(33646002)(19580395003)(50226001);\n\tDIR:OUT; SFP:1102; SCL:1; SRVR:BL2PR03MB148;\n\tH:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm;\n\tPTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; ", "MIME-Version": "1.0", "X-Microsoft-Antispam": [ "UriScan:;", "BCL:0;PCL:0;RULEID:;SRVR:BL2PR03MB148;" ], "X-Forefront-PRVS": "038002787A", "Received-SPF": "Fail (protection.outlook.com: domain of freescale.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=B44548@freescale.com; ", "X-OriginatorOrg": "freescale.com", "Cc": "u-boot@lists.denx.de, Alison Wang <alison.wang@freescale.com>", "Subject": "[U-Boot] [PATCH] arm:ls1021a:configure ls1021 scfg for QSPI", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.13", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "u-boot-bounces@lists.denx.de", "Errors-To": "u-boot-bounces@lists.denx.de" }, "content": "From: Chao Fu <B44548@freescale.com>\n\nConfigure ls1021a scfg register for QSPI clock initalization.\n\nSigned-off-by: Chao Fu <B44548@freescale.com>\nSigned-off-by: Alison Wang <alison.wang@freescale.com>\n---\n arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 +\n board/freescale/ls1021aqds/ls1021aqds.c | 4 ++++\n board/freescale/ls1021atwr/ls1021atwr.c | 4 ++++\n 3 files changed, 9 insertions(+)", "diff": "diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\nindex 7995fe2..cdee199 100644\n--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\n+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\n@@ -100,6 +100,7 @@ struct ccsr_gur {\n #define SCFG_ETSECDMAMCR_LE_BD_FR\t0xf8001a0f\n #define SCFG_ETSECCMCR_GE2_CLK125\t0x04000000\n #define SCFG_PIXCLKCR_PXCKEN\t\t0x80000000\n+#define SCFG_QSPI_CLKSEL\t\t0xc0100000\n \n /* Supplemental Configuration Unit */\n struct ccsr_scfg {\ndiff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c\nindex 32e0fef..70da686 100644\n--- a/board/freescale/ls1021aqds/ls1021aqds.c\n+++ b/board/freescale/ls1021aqds/ls1021aqds.c\n@@ -146,6 +146,10 @@ int board_early_init_f(void)\n \tinit_early_memctl_regs();\n #endif\n \n+#ifdef CONFIG_FSL_QSPI\n+\tout_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);\n+#endif\n+\n \t/* Workaround for the issue that DDR could not respond to\n \t * barrier transaction which is generated by executing DSB/ISB\n \t * instruction. Set CCI-400 control override register to\ndiff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c\nindex 50d5640..25b1eb9 100644\n--- a/board/freescale/ls1021atwr/ls1021atwr.c\n+++ b/board/freescale/ls1021atwr/ls1021atwr.c\n@@ -278,6 +278,10 @@ int board_init(void)\n \tconfig_serdes_mux();\n #endif\n \n+#ifdef CONFIG_FSL_QSPI\n+\tout_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);\n+#endif\n+\n \treturn 0;\n }\n \n", "prefixes": [ "U-Boot" ] }