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{
    "id": 402797,
    "url": "http://patchwork.ozlabs.org/api/patches/402797/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1414145327-23541-5-git-send-email-jingchang.lu@freescale.com/",
    "project": {
        "id": 37,
        "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api",
        "name": "Devicetree Bindings",
        "link_name": "devicetree-bindings",
        "list_id": "devicetree.vger.kernel.org",
        "list_email": "devicetree@vger.kernel.org",
        "web_url": "",
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    "msgid": "<1414145327-23541-5-git-send-email-jingchang.lu@freescale.com>",
    "list_archive_url": null,
    "date": "2014-10-24T10:08:45",
    "name": "[PATCHv5,RESEND,4/6] dt-bindings: arm: add Freescale LS1021A SoC device tree binding",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "c85e23995c09d588758e5fcafbcb8ca996d4353a",
    "submitter": {
        "id": 46273,
        "url": "http://patchwork.ozlabs.org/api/people/46273/?format=api",
        "name": "Jingchang Lu",
        "email": "jingchang.lu@freescale.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1414145327-23541-5-git-send-email-jingchang.lu@freescale.com/mbox/",
    "series": [],
    "comments": "http://patchwork.ozlabs.org/api/patches/402797/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/402797/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<devicetree-owner@vger.kernel.org>",
        "X-Original-To": "incoming-dt@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org",
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            "from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBN1AFFO11FD026.mail.protection.outlook.com (10.58.52.86) with\n\tMicrosoft SMTP\n\tServer (TLS) id 15.0.1049.20 via Frontend Transport; Fri, 24 Oct 2014\n\t10:57:21 +0000",
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        ],
        "From": "Jingchang Lu <jingchang.lu@freescale.com>",
        "To": "<shawn.guo@linaro.org>",
        "CC": "<arnd@arndb.de>, <mark.rutland@arm.com>,\n\t<linux-arm-kernel@lists.infradead.org>, <devicetree@vger.kernel.org>, \n\tJingchang Lu <jingchang.lu@freescale.com>",
        "Subject": "[PATCHv5 RESEND 4/6] dt-bindings: arm: add Freescale LS1021A SoC\n\tdevice tree binding",
        "Date": "Fri, 24 Oct 2014 18:08:45 +0800",
        "Message-ID": "<1414145327-23541-5-git-send-email-jingchang.lu@freescale.com>",
        "X-Mailer": "git-send-email 1.8.0",
        "In-Reply-To": "<1414145327-23541-1-git-send-email-jingchang.lu@freescale.com>",
        "References": "<1414145327-23541-1-git-send-email-jingchang.lu@freescale.com>",
        "X-EOPAttributedMessage": "0",
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        "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=jingchang.lu@freescale.com; ",
        "X-OriginatorOrg": "freescale.com",
        "Sender": "devicetree-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<devicetree.vger.kernel.org>",
        "X-Mailing-List": "devicetree@vger.kernel.org"
    },
    "content": "Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>\n---\n Documentation/devicetree/bindings/arm/fsl.txt | 38 +++++++++++++++++++++++++++\n 1 file changed, 38 insertions(+)",
    "diff": "diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt\nindex e935d7d..4e8b7df 100644\n--- a/Documentation/devicetree/bindings/arm/fsl.txt\n+++ b/Documentation/devicetree/bindings/arm/fsl.txt\n@@ -74,3 +74,41 @@ Required root node properties:\n i.MX6q generic board\n Required root node properties:\n     - compatible = \"fsl,imx6q\";\n+\n+\n+Freescale LS1021A Platform Device Tree Bindings\n+------------------------------------------------\n+\n+Required root node compatible properties:\n+  - compatible = \"fsl,ls1021a\";\n+\n+Freescale LS1021A SoC-specific Device Tree Bindings\n+-------------------------------------------\n+\n+Freescale SCFG\n+  SCFG is the supplemental configuration unit, that provides SoC specific\n+configuration and status registers for the chip. Such as getting PEX port\n+status.\n+  Required properties:\n+  - compatible: should be \"fsl,ls1021a-scfg\"\n+  - reg: should contain base address and length of SCFG memory-mapped registers\n+\n+Example:\n+\tscfg: scfg@1570000 {\n+\t\tcompatible = \"fsl,ls1021a-scfg\";\n+\t\treg = <0x0 0x1570000 0x0 0x10000>;\n+\t};\n+\n+Freescale DCFG\n+  DCFG is the device configuration unit, that provides general purpose\n+configuration and status for the device. Such as setting the secondary\n+core start address and release the secondary core from holdoff and startup.\n+  Required properties:\n+  - compatible: should be \"fsl,ls1021a-dcfg\"\n+  - reg : should contain base address and length of DCFG memory-mapped registers\n+\n+Example:\n+\tdcfg: dcfg@1ee0000 {\n+\t\tcompatible = \"fsl,ls1021a-dcfg\";\n+\t\treg = <0x0 0x1ee0000 0x0 0x10000>;\n+\t};\n",
    "prefixes": [
        "PATCHv5",
        "RESEND",
        "4/6"
    ]
}