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GET /api/patches/402377/?format=api
{ "id": 402377, "url": "http://patchwork.ozlabs.org/api/patches/402377/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/patch/1414037773-7735-2-git-send-email-chenhui.zhao@freescale.com/", "project": { "id": 19, "url": "http://patchwork.ozlabs.org/api/projects/19/?format=api", "name": "Linux IMX development", "link_name": "linux-imx", "list_id": "linux-imx-kernel.lists.patchwork.ozlabs.org", "list_email": "linux-imx-kernel@lists.patchwork.ozlabs.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1414037773-7735-2-git-send-email-chenhui.zhao@freescale.com>", "list_archive_url": null, "date": "2014-10-23T04:16:13", "name": "[v2,2/2] arm: pm: add deep sleep support for LS1", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7630521841e7c697cebb42a28a8e5fd1eff1a942", "submitter": { "id": 8974, "url": "http://patchwork.ozlabs.org/api/people/8974/?format=api", "name": "chenhui zhao", "email": "chenhui.zhao@freescale.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-imx/patch/1414037773-7735-2-git-send-email-chenhui.zhao@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/402377/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/402377/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming-imx@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-imx@bilbo.ozlabs.org", "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n\t[IPv6:2001:1868:205::9])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 6C2C714007F\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tThu, 23 Oct 2014 15:21:56 +1100 (AEDT)", "from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux))\n\tid 1Xh9pe-0006F1-J6; Thu, 23 Oct 2014 04:17:02 +0000", "from mail-by2on0121.outbound.protection.outlook.com\n\t([207.46.100.121] helo=na01-by2-obe.outbound.protection.outlook.com)\n\tby bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat\n\tLinux)) id 1Xh9pO-0006C4-Po\n\tfor linux-arm-kernel@lists.infradead.org;\n\tThu, 23 Oct 2014 04:16:49 +0000", "from BN3PR0301CA0027.namprd03.prod.outlook.com (25.160.180.165) by\n\tDM2PR0301MB0734.namprd03.prod.outlook.com (25.160.97.142) with\n\tMicrosoft SMTP\n\tServer (TLS) id 15.0.1054.13; Thu, 23 Oct 2014 04:16:24 +0000", "from BN1BFFO11FD022.protection.gbl (2a01:111:f400:7c10::1:107) by\n\tBN3PR0301CA0027.outlook.office365.com (2a01:111:e400:4000::37)\n\twith Microsoft\n\tSMTP Server (TLS) id 15.1.6.9 via Frontend Transport; Thu, 23 Oct 2014\n\t04:16:24 +0000", "from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBN1BFFO11FD022.mail.protection.outlook.com (10.58.144.85) with\n\tMicrosoft SMTP\n\tServer (TLS) id 15.0.1049.20 via Frontend Transport; Thu, 23 Oct 2014\n\t04:16:23 +0000", "from udp189498uds.ap.freescale.net ([10.193.20.174])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\ts9N4GFeY006017; Wed, 22 Oct 2014 21:16:20 -0700" ], "From": "Chenhui Zhao <chenhui.zhao@freescale.com>", "To": "<linux-kernel@vger.kernel.org>, <kernel@pengutronix.de>,\n\t<linux-arm-kernel@lists.infradead.org>", "Subject": "[PATCH v2 2/2] arm: pm: add deep sleep support for LS1", "Date": "Thu, 23 Oct 2014 12:16:13 +0800", "Message-ID": "<1414037773-7735-2-git-send-email-chenhui.zhao@freescale.com>", "X-Mailer": "git-send-email 1.7.3", "In-Reply-To": "<1414037773-7735-1-git-send-email-chenhui.zhao@freescale.com>", "References": "<1414037773-7735-1-git-send-email-chenhui.zhao@freescale.com>", "X-EOPAttributedMessage": "0", "X-Forefront-Antispam-Report": "CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI;\n\tEFV:NLI; SFV:NSPM;\n\tSFS:(10019020)(6009001)(199003)(189002)(62966002)(47776003)(89996001)(105606002)(6806004)(44976005)(19580405001)(106466001)(107046002)(120916001)(20776003)(87286001)(76482002)(64706001)(84676001)(85852003)(50466002)(95666004)(50226001)(99396003)(87936001)(88136002)(48376002)(93916002)(76176999)(85306004)(50986999)(102836001)(26826002)(92726001)(2201001)(86362001)(92566001)(46102003)(31966008)(21056001)(229853001)(80022003)(104166001)(36756003)(68736004)(4396001)(19580395003)(33646002)(97736003)(77156001)(104016003)(2004002);\n\tDIR:OUT; SFP:1102; SCL:1; SRVR:DM2PR0301MB0734;\n\tH:tx30smr01.am.freescale.net; \n\tFPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; ", "MIME-Version": "1.0", "X-Microsoft-Antispam": [ "UriScan:;", "BCL:0;PCL:0;RULEID:;SRVR:DM2PR0301MB0734;" ], "X-Forefront-PRVS": "0373D94D15", "Received-SPF": "Fail (protection.outlook.com: domain of freescale.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "Authentication-Results": "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=chenhui.zhao@freescale.com; ", "X-OriginatorOrg": "freescale.com", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20141022_211647_009130_79F6B298 ", "X-CRM114-Status": "GOOD ( 21.94 )", "X-Spam-Score": "-0.5 (/)", "X-Spam-Report": "SpamAssassin version 3.4.0 on bombadil.infradead.org summary:\n\tContent analysis details: (-0.5 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.5 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2)\n\t[207.46.100.121 listed in wl.mailspike.net]\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [207.46.100.121 listed in list.dnswl.org]\n\t-0.0 SPF_HELO_PASS SPF: HELO matches SPF record\n\t-0.0 SPF_PASS SPF: sender matches SPF record", "Cc": "leoli@freescale.com, Jason.Jin@freescale.com", "X-BeenThere": "linux-arm-kernel@lists.infradead.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-arm-kernel/>", "List-Post": "<mailto:linux-arm-kernel@lists.infradead.org>", "List-Help": "<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>", "Errors-To": "linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org", "List-Id": "linux-imx-kernel.lists.patchwork.ozlabs.org" }, "content": "LS1 supports deep sleep feature that can switch off most parts of\nthe SoC when it is in deep sleep state.\n\nThe DDR controller will also be powered off in deep sleep. Therefore,\ncopy the last stage code to enter deep sleep to SRAM and run it\nwith disabling MMU and caches.\n\nSigned-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>\n---\nChanges for v2:\n * use identity mapping to smooth the process of disabling MMU\n * change the value of registers\n\n arch/arm/mach-imx/Kconfig | 1 +\n arch/arm/mach-imx/Makefile | 1 +\n arch/arm/mach-imx/pm-ls1.c | 341 +++++++++++++++++++++++++++++++++++++++++\n arch/arm/mach-imx/sleep-ls1.S | 132 ++++++++++++++++\n 4 files changed, 475 insertions(+), 0 deletions(-)\n create mode 100644 arch/arm/mach-imx/pm-ls1.c\n create mode 100644 arch/arm/mach-imx/sleep-ls1.S", "diff": "diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig\nindex b85534c..716bb1b 100644\n--- a/arch/arm/mach-imx/Kconfig\n+++ b/arch/arm/mach-imx/Kconfig\n@@ -866,6 +866,7 @@ config SOC_LS1021A\n \tselect HAVE_SMP\n \tselect ARCH_LAYERSCAPE\n \tselect ZONE_DMA if ARM_LPAE\n+\tselect FSL_SLEEP_FSM if PM\n \n \thelp\n \t This enable support for Freescale Layerscape LS1021A processor.\ndiff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile\nindex 41b8044..9931528 100644\n--- a/arch/arm/mach-imx/Makefile\n+++ b/arch/arm/mach-imx/Makefile\n@@ -102,6 +102,7 @@ obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o\n \n ifeq ($(CONFIG_PM),y)\n obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o\n+obj-$(CONFIG_SOC_LS1021A) += pm-ls1.o sleep-ls1.o\n endif\n \n # i.MX5 based machines\ndiff --git a/arch/arm/mach-imx/pm-ls1.c b/arch/arm/mach-imx/pm-ls1.c\nnew file mode 100644\nindex 0000000..8fd7aee\n--- /dev/null\n+++ b/arch/arm/mach-imx/pm-ls1.c\n@@ -0,0 +1,341 @@\n+/*\n+ * Support deep sleep feature for LS1\n+ *\n+ * Copyright 2014 Freescale Semiconductor Inc.\n+ *\n+ * This program is free software; you can redistribute\tit and/or modify it\n+ * under the terms of\tthe GNU General\t Public License as published by the\n+ * Free Software Foundation; either version 2 of the License, or (at your\n+ * option) any later version.\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/suspend.h>\n+#include <linux/io.h>\n+#include <linux/of_platform.h>\n+#include <linux/of_address.h>\n+#include <linux/cpu_pm.h>\n+#include <asm/suspend.h>\n+#include <asm/delay.h>\n+#include <asm/cp15.h>\n+#include <asm/cacheflush.h>\n+#include <asm/idmap.h>\n+\n+#include \"common.h\"\n+\n+#define FSL_SLEEP\t\t0x1\n+#define FSL_DEEP_SLEEP\t\t0x2\n+\n+#define DCSR_EPU_EPSMCR15\t0x278\n+#define DCSR_EPU_EPECR0\t\t0x300\n+#define DCSR_RCPM_CG1CR0\t0x31c\n+#define DCSR_RCPM_CSTTACR0\t0xb00\n+\n+#define CCSR_SCFG_DPSLPCR\t0\n+#define CCSR_SCFG_DPSLPCR_VAL\t0x1\n+#define CCSR_SCFG_SPARECR2\t0x504\n+#define CCSR_SCFG_SPARECR3\t0x508\n+\n+#define CCSR_DCFG_CRSTSR\t0x400\n+#define CCSR_DCFG_CRSTSR_VAL\t0x00000008\n+\n+#define CCSR_RCPM_POWMGTCSR\t\t0x130\n+#define CCSR_RCPM_POWMGTCSR_LPM20_REQ\t0x00100000\n+#define CCSR_RCPM_POWMGTCSR_LPM20_ST\t0x00000200\n+#define CCSR_RCPM_POWMGTCSR_P_LPM20_ST\t0x00000100\n+#define CCSR_RCPM_CLPCL10SETR\t\t0x1c4\n+#define CCSR_RCPM_CLPCL10SETR_C0\t0x1\n+\n+#define OCRAM_BASE\t0x10000000\n+#define OCRAM_SIZE\t0x10000\t\t/* 64K */\n+/* use the last page of SRAM */\n+#define SRAM_CODE_BASE_PHY\t(OCRAM_BASE + OCRAM_SIZE - PAGE_SIZE)\n+\n+struct ls1_pm_baseaddr {\n+\tvoid __iomem *epu;\n+\tvoid __iomem *dcsr_rcpm1;\n+\tvoid __iomem *dcsr_rcpm2;\n+\tvoid __iomem *rcpm;\n+\tvoid __iomem *scfg;\n+\tvoid __iomem *dcfg;\n+\tvoid __iomem *fpga;\n+\tvoid __iomem *sram;\n+};\n+\n+/* 128 bytes buffer for restoring data broke by DDR training initialization */\n+#define DDR_BUF_SIZE\t128\n+static u8 ddr_buff[DDR_BUF_SIZE] __aligned(64);\n+static struct ls1_pm_baseaddr ls1_pm_base;\n+/* supported sleep modes by the present platform */\n+static unsigned int sleep_modes;\n+\n+extern void ls1_do_deepsleep(unsigned long addr);\n+extern void ls1_start_fsm(void);\n+extern void ls1_deepsleep_resume(void);\n+extern void ls1021a_set_secondary_entry(void);\n+extern int ls1_sram_code_size;\n+extern void fsl_epu_setup_default(void __iomem *epu_base);\n+\n+static void ls1_pm_iomap(void)\n+{\n+\tstruct device_node *np;\n+\tvoid *base;\n+\n+\tnp = of_find_compatible_node(NULL, NULL, \"fsl,ls1021a-dcsr-epu\");\n+\tbase = of_iomap(np, 0);\n+\tBUG_ON(!base);\n+\tls1_pm_base.epu = base;\n+\n+\tnp = of_find_compatible_node(NULL, NULL, \"fsl,ls1021a-dcsr-rcpm\");\n+\tbase = of_iomap(np, 0);\n+\tBUG_ON(!base);\n+\tls1_pm_base.dcsr_rcpm1 = base;\n+\tbase = of_iomap(np, 1);\n+\tBUG_ON(!base);\n+\tls1_pm_base.dcsr_rcpm2 = base;\n+\n+\tnp = of_find_compatible_node(NULL, NULL, \"fsl,ls1021a-scfg\");\n+\tbase = of_iomap(np, 0);\n+\tBUG_ON(!base);\n+\tls1_pm_base.scfg = base;\n+\n+\tnp = of_find_compatible_node(NULL, NULL, \"fsl,ls1021a-dcfg\");\n+\tbase = of_iomap(np, 0);\n+\tBUG_ON(!base);\n+\tls1_pm_base.dcfg = base;\n+\n+\tnp = of_find_compatible_node(NULL, NULL, \"fsl,ls1021aqds-fpga\");\n+\tbase = of_iomap(np, 0);\n+\tBUG_ON(!base);\n+\tls1_pm_base.fpga = base;\n+\n+\tbase = ioremap(SRAM_CODE_BASE_PHY, PAGE_SIZE);\n+\tBUG_ON(!base);\n+\tls1_pm_base.sram = base;\n+}\n+\n+static void ls1_pm_uniomap(void)\n+{\n+\tiounmap(ls1_pm_base.epu);\n+\tiounmap(ls1_pm_base.dcsr_rcpm1);\n+\tiounmap(ls1_pm_base.dcsr_rcpm2);\n+\tiounmap(ls1_pm_base.scfg);\n+\tiounmap(ls1_pm_base.dcfg);\n+\tiounmap(ls1_pm_base.fpga);\n+\tiounmap(ls1_pm_base.sram);\n+}\n+\n+static void ls1_save_ddr(void *base)\n+{\n+\tu32 ddr_buff_addr;\n+\n+\t/*\n+\t * DDR training initialization will break 128 bytes at the beginning\n+\t * of DDR, therefore, save them so that the bootloader will restore\n+\t * them. Assume that DDR is mapped to the address space started with\n+\t * CONFIG_PAGE_OFFSET.\n+\t */\n+\tmemcpy(ddr_buff, (void *)CONFIG_PAGE_OFFSET, DDR_BUF_SIZE);\n+\n+\tddr_buff_addr = (u32)__pa(ddr_buff);\n+\n+\t/*\n+\t * the bootloader will restore the first 128 bytes of DDR from\n+\t * the location indicated by the register SPARECR3\n+\t */\n+\tiowrite32(ddr_buff_addr, base + CCSR_SCFG_SPARECR3);\n+}\n+\n+static void ls1_set_resume_entry(void *base)\n+{\n+\tu32 resume_addr;\n+\n+\t/* the bootloader will finally jump to this address to resume kernel */\n+\tresume_addr = (u32)(__pa(ls1_deepsleep_resume));\n+\n+\t/* use the register SPARECR2 to save the return entry */\n+\tiowrite32(resume_addr, base + CCSR_SCFG_SPARECR2);\n+}\n+\n+static void ls1_copy_sram_code(void)\n+{\n+\tmemcpy(ls1_pm_base.sram, ls1_start_fsm, ls1_sram_code_size);\n+}\n+\n+static int ls1_start_deepsleep(unsigned long addr)\n+{\n+\ttypedef void (*ls1_deepsleep_t)(unsigned long);\n+\tls1_deepsleep_t ls1_do_deepsleep_phy;\n+\n+\t/* Switch to the identity mapping */\n+\tsetup_mm_for_reboot();\n+\tv7_exit_coherency_flush(all);\n+\n+\tls1_do_deepsleep_phy =\n+\t\t(ls1_deepsleep_t)(unsigned long)virt_to_phys(ls1_do_deepsleep);\n+\tls1_do_deepsleep_phy(addr);\n+\n+\t/* never get here */\n+\tBUG();\n+\n+\treturn 0;\n+}\n+\n+void ls1_fsm_setup(void)\n+{\n+\tiowrite32be(0x00001001, ls1_pm_base.dcsr_rcpm1 + DCSR_RCPM_CSTTACR0);\n+\tiowrite32be(0x00000001, ls1_pm_base.dcsr_rcpm1 + DCSR_RCPM_CG1CR0);\n+\n+\tfsl_epu_setup_default(ls1_pm_base.epu);\n+\n+\t/*\n+\t * pull the MCKE signal(EVT4_B pin) low before enabling\n+\t * deep sleep signals by FPGA\n+\t */\n+\tiowrite32be(0x5, ls1_pm_base.epu + DCSR_EPU_EPECR0);\n+\n+\tiowrite32be(0x76300000, ls1_pm_base.epu + DCSR_EPU_EPSMCR15);\n+}\n+\n+static inline void ls1_clrsetbits_be32(void __iomem *addr, u32 clear, u32 set)\n+{\n+\tu32 tmp;\n+\n+\ttmp = ioread32be(addr);\n+\ttmp = (tmp & ~clear) | set;\n+\tiowrite32be(tmp, addr);\n+}\n+\n+static void ls1_enter_deepsleep(void)\n+{\n+\tu32 tmp;\n+\n+\t/* save DDR data */\n+\tls1_save_ddr(ls1_pm_base.scfg);\n+\n+\t/* save kernel resume entry */\n+\tls1_set_resume_entry(ls1_pm_base.scfg);\n+\n+\t/* Request to put cluster 0 in PCL10 state */\n+\tls1_clrsetbits_be32(ls1_pm_base.rcpm + CCSR_RCPM_CLPCL10SETR,\n+\t\t\t CCSR_RCPM_CLPCL10SETR_C0,\n+\t\t\t CCSR_RCPM_CLPCL10SETR_C0);\n+\n+\t/* setup the registers of the EPU FSM for deep sleep */\n+\tls1_fsm_setup();\n+\n+\t/* enable deep sleep signals in FPGA */\n+\ttmp = ioread8(ls1_pm_base.fpga + QIXIS_PWR_CTL2);\n+\tiowrite8(tmp | QIXIS_PWR_CTL2_PCTL, ls1_pm_base.fpga + QIXIS_PWR_CTL2);\n+\n+\t/* enable Warm Device Reset */\n+\tls1_clrsetbits_be32(ls1_pm_base.scfg + CCSR_SCFG_DPSLPCR,\n+\t\t\t CCSR_SCFG_DPSLPCR_VAL, CCSR_SCFG_DPSLPCR_VAL);\n+\n+\tls1_clrsetbits_be32(ls1_pm_base.dcfg + CCSR_DCFG_CRSTSR,\n+\t\t\t CCSR_DCFG_CRSTSR_VAL, CCSR_DCFG_CRSTSR_VAL);\n+\n+\t/* copy the last stage code to sram */\n+\tls1_copy_sram_code();\n+\n+\tcpu_suspend(SRAM_CODE_BASE_PHY, ls1_start_deepsleep);\n+\n+\t/* disable Warm Device Reset */\n+\tls1_clrsetbits_be32(ls1_pm_base.scfg + CCSR_SCFG_DPSLPCR,\n+\t\t\t CCSR_SCFG_DPSLPCR_VAL, 0);\n+\n+\t/* disable deep sleep signals in FPGA */\n+\ttmp = ioread8(ls1_pm_base.fpga + QIXIS_PWR_CTL2);\n+\tiowrite8(tmp & ~QIXIS_PWR_CTL2_PCTL, ls1_pm_base.fpga + QIXIS_PWR_CTL2);\n+\n+\t/* call smp_prepare_cpus */\n+\tls1021a_set_secondary_entry();\n+}\n+\n+static int ls1_suspend_enter(suspend_state_t state)\n+{\n+\tint ret = 0;\n+\n+\tswitch (state) {\n+\tcase PM_SUSPEND_STANDBY:\n+\t\tflush_cache_louis();\n+\t\tls1_clrsetbits_be32(ls1_pm_base.rcpm + CCSR_RCPM_POWMGTCSR,\n+\t\t\t\t CCSR_RCPM_POWMGTCSR_LPM20_REQ,\n+\t\t\t\t CCSR_RCPM_POWMGTCSR_LPM20_REQ);\n+\n+\t\tcpu_do_idle();\n+\t\tbreak;\n+\n+\tcase PM_SUSPEND_MEM:\n+\t\tls1_enter_deepsleep();\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tret = -EINVAL;\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int ls1_suspend_valid(suspend_state_t state)\n+{\n+\tif (state == PM_SUSPEND_STANDBY && (sleep_modes & FSL_SLEEP))\n+\t\treturn 1;\n+\n+\tif (state == PM_SUSPEND_MEM && (sleep_modes & FSL_DEEP_SLEEP))\n+\t\treturn 1;\n+\n+\treturn 0;\n+}\n+\n+static int ls1_suspend_begin(suspend_state_t state)\n+{\n+\tls1_pm_iomap();\n+\n+\treturn 0;\n+}\n+\n+static void ls1_suspend_end(void)\n+{\n+\tls1_pm_uniomap();\n+}\n+\n+static const struct platform_suspend_ops ls1_suspend_ops = {\n+\t.valid = ls1_suspend_valid,\n+\t.enter = ls1_suspend_enter,\n+\t.begin = ls1_suspend_begin,\n+\t.end = ls1_suspend_end,\n+};\n+\n+\n+static const struct of_device_id rcpm_matches[] = {\n+\t{\n+\t\t.compatible = \"fsl,ls1021a-rcpm\",\n+\t\t.data = (void *)(FSL_SLEEP | FSL_DEEP_SLEEP),\n+\t},\n+\t{}\n+};\n+\n+static int __init ls1_pm_init(void)\n+{\n+\tconst struct of_device_id *match;\n+\tstruct device_node *np;\n+\tvoid *base;\n+\n+\tnp = of_find_matching_node_and_match(NULL, rcpm_matches, &match);\n+\tif (!np) {\n+\t\tpr_err(\"%s: can't find the rcpm node.\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tbase = of_iomap(np, 0);\n+\tof_node_put(np);\n+\tif (!base)\n+\t\treturn -ENOMEM;\n+\n+\tsleep_modes = (unsigned int)match->data;\n+\tls1_pm_base.rcpm = base;\n+\tsuspend_set_ops(&ls1_suspend_ops);\n+\treturn 0;\n+}\n+arch_initcall(ls1_pm_init);\ndiff --git a/arch/arm/mach-imx/sleep-ls1.S b/arch/arm/mach-imx/sleep-ls1.S\nnew file mode 100644\nindex 0000000..deccfa8\n--- /dev/null\n+++ b/arch/arm/mach-imx/sleep-ls1.S\n@@ -0,0 +1,132 @@\n+/*\n+ * Support deep sleep feature for LS1\n+ *\n+ * Copyright 2014 Freescale Semiconductor Inc.\n+ *\n+ * This program is free software; you can redistribute\tit and/or modify it\n+ * under the terms of\tthe GNU General\t Public License as published by the\n+ * Free Software Foundation; either version 2 of the License, or (at your\n+ * option) any later version.\n+ */\n+\n+#include <linux/linkage.h>\n+#include <asm/assembler.h>\n+#include <asm/cache.h>\n+#include <asm/cp15.h>\n+\n+#define CCSR_DDR_BASE\t\t\t0x01080000\n+#define CCSR_DDR_SDRAM_CFG_2\t\t0x114\n+\n+#define CCSR_SCFG_BASE\t\t\t0x01570000\n+#define CCSR_SCFG_HRSTCR\t\t0x1a8\n+\n+#define DCSR_EPU_BASE\t\t\t0x20000000\n+#define DCSR_EPU_EPGCR\t\t\t0x0\n+#define DCSR_EPU_EPECR0\t\t\t0x300\n+#define DCSR_EPU_EPECR15\t\t0x33c\n+\n+/* for big endian registers */\n+.macro ls1_set_bits, addr, value\n+\tldr\tr4, \\addr\n+\tldr\tr5, [r4]\n+\tldr\tr6, \\value\n+\trev\tr6, r6\n+\torr\tr5, r5, r6\n+\tstr\tr5, [r4]\n+.endm\n+\n+/* 1000 loops per round */\n+.macro ls1_delay, count\n+\tmov\tr0, \\count\n+11:\tmov\tr7, #1000\n+12:\tsubs\tr7, r7, #1\n+\tbne\t12b\n+\tsubs\tr0, r0, #1\n+\tbne\t11b\n+.endm\n+\n+/*\n+ * r0: the physical entry address of SRAM code\n+ *\n+ */\n+\t.align L1_CACHE_SHIFT\n+\t.pushsection\t.idmap.text,\"ax\"\n+ENTRY(ls1_do_deepsleep)\n+\t/* disable MMU, M bit in SCTLR */\n+\tmrc\tp15, 0, r3, c1, c0, 0\n+\tbic\tr3, r3, #CR_M\n+\tmcr\tp15, 0, r3, c1, c0, 0\n+\tisb\n+\n+\t/* jump to sram code using physical address */\n+\tbx\tr0\n+ENDPROC(ls1_do_deepsleep)\n+\t.popsection\n+\n+/*\n+ * The code will be copied to SRAM.\n+ */\n+\t.align L1_CACHE_SHIFT\n+ENTRY(ls1_start_fsm)\n+\t/* set HRSTCR */\n+\tls1_set_bits\tls1_ccsr_scfg_hrstcr_addr, ls1_ccsr_scfg_hrstcr_val\n+\n+\t/* Place DDR controller in self refresh mode */\n+\tls1_set_bits\tls1_ddr_cfg2_addr, ls1_ddr_cfg2_val\n+\n+\tls1_delay\t#2000\n+\n+\t/* Set EVT4_B to lock the signal MCKE down */\n+\tldr\tr4, ls1_dcsr_epu_epecr0\n+\tldr\tr5, ls1_dcsr_epu_epecr0_val\n+\trev\tr5, r5\n+\tstr\tr5, [r4]\n+\n+\tls1_delay\t#2000\n+\n+\t/* Enable all EPU Counters */\n+\tls1_set_bits\tls1_dcsr_epu_epgcr_addr, ls1_dcsr_epu_epgcr_val\n+\n+\t/* Enable SCU15 */\n+\tls1_set_bits\tls1_dcsr_epu_epecr15, ls1_dcsr_epu_epecr15_val\n+\n+\t/* Enter WFI mode, and EPU FSM will start */\n+20:\twfi\n+\tb\t20b\n+\n+ls1_ccsr_scfg_hrstcr_addr:\n+\t.word\tCCSR_SCFG_BASE + CCSR_SCFG_HRSTCR\n+ls1_ccsr_scfg_hrstcr_val:\n+\t.word\t0x80000000\n+\n+ls1_ddr_cfg2_addr:\n+\t.word\tCCSR_DDR_BASE + CCSR_DDR_SDRAM_CFG_2\n+ls1_ddr_cfg2_val:\n+\t.word\t(1 << 31)\n+\n+ls1_dcsr_epu_epgcr_addr:\n+\t.word\tDCSR_EPU_BASE + DCSR_EPU_EPGCR\n+ls1_dcsr_epu_epgcr_val:\n+\t.word\t0x80000000\n+\n+ls1_dcsr_epu_epecr0:\n+\t.word\tDCSR_EPU_BASE + DCSR_EPU_EPECR0\n+ls1_dcsr_epu_epecr0_val:\n+\t.word\t0\n+\n+ls1_dcsr_epu_epecr15:\n+\t.word\tDCSR_EPU_BASE + DCSR_EPU_EPECR15\n+ls1_dcsr_epu_epecr15_val:\n+\t.word\t0x90000004\n+\n+ENTRY(ls1_sram_code_size)\n+\t.word\t. - ls1_start_fsm\n+\n+/* the bootloader will jump to here after wakeup from deep sleep */\n+\t.align L1_CACHE_SHIFT\n+ENTRY(ls1_deepsleep_resume)\n+ THUMB(\tadr\tr6, BSYM(1f)\t)\n+ THUMB(\tbx\tr6\t\t)\n+ THUMB(\t.thumb\t\t\t)\n+ THUMB(1:\t\t\t)\n+\tb cpu_resume\n", "prefixes": [ "v2", "2/2" ] }