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GET /api/patches/400440/?format=api
{ "id": 400440, "url": "http://patchwork.ozlabs.org/api/patches/400440/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1413533203-28747-1-git-send-email-b18965@freescale.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1413533203-28747-1-git-send-email-b18965@freescale.com>", "list_archive_url": null, "date": "2014-10-17T08:06:43", "name": "[U-Boot,v3,8/8] arm: ls102xa: Add NAND boot support for LS1021AQDS board", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "ce03a60ea319814ef96735991111c1b8e403d22a", "submitter": { "id": 13010, "url": "http://patchwork.ozlabs.org/api/people/13010/?format=api", "name": "Alison Wang", "email": "b18965@freescale.com" }, "delegate": { "id": 2666, "url": "http://patchwork.ozlabs.org/api/users/2666/?format=api", "username": "yorksun", "first_name": "York", "last_name": "Sun", "email": "yorksun@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1413533203-28747-1-git-send-email-b18965@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/400440/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/400440/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id F02181400BE\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 17 Oct 2014 19:07:34 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id AFCCE4B5FD;\n\tFri, 17 Oct 2014 10:07:33 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id Ggo-LC9Y1+yQ; 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Fri, 17 Oct 2014 01:07:18 -0700" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "Alison Wang <b18965@freescale.com>", "To": "<yorksun@freescale.com>, <u-boot@lists.denx.de>", "Date": "Fri, 17 Oct 2014 16:06:43 +0800", "Message-ID": "<1413533203-28747-1-git-send-email-b18965@freescale.com>", "X-Mailer": "git-send-email 2.1.0.27.g96db324", "X-EOPAttributedMessage": "0", "X-Forefront-Antispam-Report": "CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI;\n\tEFV:NLI; SFV:NSPM;\n\tSFS:(10019020)(6009001)(189002)(199003)(54534003)(26826002)(104016003)(85852003)(102836001)(99396003)(89996001)(33646002)(88136002)(19580395003)(44976005)(84676001)(85306004)(97736003)(68736004)(105606002)(64706001)(120916001)(21056001)(47776003)(69596002)(62966002)(19580405001)(6806004)(20776003)(106466001)(81156004)(93916002)(92726001)(92566001)(48376002)(50466002)(575784001)(76482002)(104166001)(229853001)(87936001)(50226001)(80022003)(4396001)(50986999)(46102003)(31966008)(77156001)(87286001)(107046002)(36756003)(95666004)(42262002);\n\tDIR:OUT; SFP:1102; SCL:1; SRVR:BY2PR03MB460;\n\tH:az84smr01.freescale.net; FPR:; MLV:ovrnspm;\n\tPTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; ", "MIME-Version": "1.0", "X-Microsoft-Antispam": [ "UriScan:;", "BCL:0;PCL:0;RULEID:;SRVR:BY2PR03MB460;" ], "X-Exchange-Antispam-Report-Test": "UriScan:;", "X-Forefront-PRVS": "0367A50BB1", "Received-SPF": "Fail (protection.outlook.com: domain of freescale.com does not\n\tdesignate 192.88.158.2 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.158.2; helo=az84smr01.freescale.net;", "Authentication-Results": "spf=fail (sender IP is 192.88.158.2)\n\tsmtp.mailfrom=alison.wang@freescale.com; ", "X-OriginatorOrg": "freescale.com", "Cc": "Alison Wang <alison.wang@freescale.com>", "Subject": "[U-Boot] [PATCH v3 8/8] arm: ls102xa: Add NAND boot support for\n\tLS1021AQDS board", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.13", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "u-boot-bounces@lists.denx.de", "Errors-To": "u-boot-bounces@lists.denx.de" }, "content": "This patch adds NAND boot support for LS1021AQDS board. SPL\nframework is used. PBL initialize the internal RAM and copy\nSPL to it, then SPL initialize DDR using SPD and copy u-boot\nfrom NAND flash to DDR, finally SPL transfer control to u-boot.\n\nSigned-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>\nSigned-off-by: Alison Wang <alison.wang@freescale.com>\n---\nChange log:\n v3: New file.\n\n arch/arm/include/asm/arch-ls102xa/config.h | 1 +\n arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +\n board/freescale/ls1021aqds/MAINTAINERS | 1 +\n board/freescale/ls1021aqds/ls1021aqds.c | 16 ++++++\n board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg | 7 +++\n configs/ls1021aqds_nand_defconfig | 4 ++\n drivers/mtd/nand/fsl_ifc_spl.c | 8 +++\n include/configs/ls1021aqds.h | 68 +++++++++++++++++++++++\n 8 files changed, 107 insertions(+)\n create mode 100644 board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg\n create mode 100644 configs/ls1021aqds_nand_defconfig", "diff": "diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h\nindex a500b5b..da7537c 100644\n--- a/arch/arm/include/asm/arch-ls102xa/config.h\n+++ b/arch/arm/include/asm/arch-ls102xa/config.h\n@@ -13,6 +13,7 @@\n #define OCRAM_SIZE\t\t\t\t0x00020000\n \n #define CONFIG_SYS_IMMR\t\t\t\t0x01000000\n+#define CONFIG_SYS_DCSRBAR\t\t\t0x20200000\n \n #define CONFIG_SYS_FSL_DDR_ADDR\t\t\t(CONFIG_SYS_IMMR + 0x00080000)\n #define CONFIG_SYS_CCI400_ADDR\t\t\t(CONFIG_SYS_IMMR + 0x00180000)\ndiff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\nindex 73f335d..f0a652b 100644\n--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\n+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\n@@ -29,6 +29,8 @@\n #define ARCH_TIMER_CTRL_ENABLE\t\t(1 << 0)\n #define SYS_COUNTER_CTRL_ENABLE\t\t(1 << 24)\n \n+#define DCFG_CCSR_PORSR1_RCW_MASK\t0xff800000\n+\n struct sys_info {\n \tunsigned long freq_processor[CONFIG_MAX_CPUS];\n \tunsigned long freq_systembus;\ndiff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS\nindex de11203..f136700 100644\n--- a/board/freescale/ls1021aqds/MAINTAINERS\n+++ b/board/freescale/ls1021aqds/MAINTAINERS\n@@ -6,3 +6,4 @@ F:\tinclude/configs/ls1021aqds.h\n F:\tconfigs/ls1021aqds_nor_defconfig\n F:\tconfigs/ls1021aqds_ddr4_nor_defconfig\n F:\tconfigs/ls1021aqds_sdcard_defconfig\n+F:\tconfigs/ls1021aqds_nand_defconfig\ndiff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c\nindex 34f54ab..053ba70 100644\n--- a/board/freescale/ls1021aqds/ls1021aqds.c\n+++ b/board/freescale/ls1021aqds/ls1021aqds.c\n@@ -164,6 +164,22 @@ void board_init_f(ulong dummy)\n {\n \tstruct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;\n \n+#ifdef CONFIG_NAND_BOOT\n+\tstruct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;\n+\tu32 porsr1, pinctl;\n+\n+\tinit_early_memctl_regs();\n+\n+\t/*\n+\t * There is LS1 SoC issue where NOR, FPGA are inaccessible during\n+\t * NAND boot because IFC signals > IFC_AD7 are not enabled.\n+\t * This workaround changes RCW source to make all signals enabled.\n+\t */\n+\tporsr1 = in_be32(&gur->porsr1);\n+\tpinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) | 0x24800000);\n+\tout_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);\n+#endif\n+\n \t/* Set global data pointer */\n \tgd = &gdata;\n \ndiff --git a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg\nnew file mode 100644\nindex 0000000..222c71d\n--- /dev/null\n+++ b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg\n@@ -0,0 +1,7 @@\n+#PBL preamble and RCW header\n+aa55aa55 01ee0100\n+# serdes protocol\n+0608000a 00000000 00000000 00000000\n+60000000 00407900 e0106a00 21046000\n+00000000 00000000 00000000 00038000\n+00000000 001b7200 00000000 00000000\ndiff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig\nnew file mode 100644\nindex 0000000..dad5274\n--- /dev/null\n+++ b/configs/ls1021aqds_nand_defconfig\n@@ -0,0 +1,4 @@\n+CONFIG_SPL=y\n+CONFIG_SYS_EXTRA_OPTIONS=\"RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT\"\n++S:CONFIG_ARM=y\n++S:CONFIG_TARGET_LS1021AQDS=y\ndiff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c\nindex e336cb1..3d96aaf 100644\n--- a/drivers/mtd/nand/fsl_ifc_spl.c\n+++ b/drivers/mtd/nand/fsl_ifc_spl.c\n@@ -12,6 +12,14 @@\n #include <fsl_ifc.h>\n #include <linux/mtd/nand.h>\n \n+void nand_init(void)\n+{\n+}\n+\n+void nand_deselect(void)\n+{\n+}\n+\n static inline int is_blank(uchar *addr, int page_size)\n {\n \tint i;\ndiff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h\nindex 71021cf..1136278 100644\n--- a/include/configs/ls1021aqds.h\n+++ b/include/configs/ls1021aqds.h\n@@ -79,6 +79,39 @@ unsigned long get_board_ddr_clk(void);\n #define CONFIG_SYS_NO_FLASH\n #endif\n \n+#ifdef CONFIG_NAND_BOOT\n+#define CONFIG_SYS_FSL_PBL_RCW\tboard/freescale/ls1021aqds/ls102xa_rcw_nand.cfg\n+#define CONFIG_SPL_FRAMEWORK\n+#define CONFIG_SPL_LDSCRIPT\t\"arch/$(ARCH)/cpu/u-boot-spl.lds\"\n+#define CONFIG_SPL_LIBCOMMON_SUPPORT\n+#define CONFIG_SPL_LIBGENERIC_SUPPORT\n+#define CONFIG_SPL_ENV_SUPPORT\n+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT\n+#define CONFIG_SPL_I2C_SUPPORT\n+#define CONFIG_SPL_WATCHDOG_SUPPORT\n+#define CONFIG_SPL_SERIAL_SUPPORT\n+#define CONFIG_SPL_NAND_SUPPORT\n+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT\n+\n+#define CONFIG_SPL_TEXT_BASE\t\t0x10000000\n+#define CONFIG_SPL_MAX_SIZE\t\t0x1a000\n+#define CONFIG_SPL_STACK\t\t0x1001d000\n+#define CONFIG_SPL_PAD_TO\t\t0x1c000\n+#define CONFIG_SYS_TEXT_BASE\t\t0x82000000\n+\n+#define CONFIG_SYS_NAND_U_BOOT_SIZE\t(400 << 10)\n+#define CONFIG_SYS_NAND_U_BOOT_OFFS\tCONFIG_SPL_PAD_TO\n+#define CONFIG_SYS_NAND_PAGE_SIZE\t2048\n+#define CONFIG_SYS_NAND_U_BOOT_DST\tCONFIG_SYS_TEXT_BASE\n+#define CONFIG_SYS_NAND_U_BOOT_START\tCONFIG_SYS_TEXT_BASE\n+\n+#define CONFIG_SYS_SPL_MALLOC_START\t0x80200000\n+#define CONFIG_SYS_SPL_MALLOC_SIZE\t0x100000\n+#define CONFIG_SPL_BSS_START_ADDR\t0x80100000\n+#define CONFIG_SPL_BSS_MAX_SIZE\t\t0x80000\n+#define CONFIG_SYS_MONITOR_LEN\t\t0x80000\n+#endif\n+\n #ifndef CONFIG_SYS_TEXT_BASE\n #define CONFIG_SYS_TEXT_BASE\t\t0x67f80000\n #endif\n@@ -249,6 +282,40 @@ unsigned long get_board_ddr_clk(void);\n #define CONFIG_SYS_FPGA_FTIM3\t\t0x0\n #endif\n \n+#if defined(CONFIG_NAND_BOOT)\n+#define CONFIG_SYS_CSPR0_EXT\t\tCONFIG_SYS_NAND_CSPR_EXT\n+#define CONFIG_SYS_CSPR0\t\tCONFIG_SYS_NAND_CSPR\n+#define CONFIG_SYS_AMASK0\t\tCONFIG_SYS_NAND_AMASK\n+#define CONFIG_SYS_CSOR0\t\tCONFIG_SYS_NAND_CSOR\n+#define CONFIG_SYS_CS0_FTIM0\t\tCONFIG_SYS_NAND_FTIM0\n+#define CONFIG_SYS_CS0_FTIM1\t\tCONFIG_SYS_NAND_FTIM1\n+#define CONFIG_SYS_CS0_FTIM2\t\tCONFIG_SYS_NAND_FTIM2\n+#define CONFIG_SYS_CS0_FTIM3\t\tCONFIG_SYS_NAND_FTIM3\n+#define CONFIG_SYS_CSPR1_EXT\t\tCONFIG_SYS_NOR0_CSPR_EXT\n+#define CONFIG_SYS_CSPR1\t\tCONFIG_SYS_NOR0_CSPR\n+#define CONFIG_SYS_AMASK1\t\tCONFIG_SYS_NOR_AMASK\n+#define CONFIG_SYS_CSOR1\t\tCONFIG_SYS_NOR_CSOR\n+#define CONFIG_SYS_CS1_FTIM0\t\tCONFIG_SYS_NOR_FTIM0\n+#define CONFIG_SYS_CS1_FTIM1\t\tCONFIG_SYS_NOR_FTIM1\n+#define CONFIG_SYS_CS1_FTIM2\t\tCONFIG_SYS_NOR_FTIM2\n+#define CONFIG_SYS_CS1_FTIM3\t\tCONFIG_SYS_NOR_FTIM3\n+#define CONFIG_SYS_CSPR2_EXT\t\tCONFIG_SYS_NOR1_CSPR_EXT\n+#define CONFIG_SYS_CSPR2\t\tCONFIG_SYS_NOR1_CSPR\n+#define CONFIG_SYS_AMASK2\t\tCONFIG_SYS_NOR_AMASK\n+#define CONFIG_SYS_CSOR2\t\tCONFIG_SYS_NOR_CSOR\n+#define CONFIG_SYS_CS2_FTIM0\t\tCONFIG_SYS_NOR_FTIM0\n+#define CONFIG_SYS_CS2_FTIM1\t\tCONFIG_SYS_NOR_FTIM1\n+#define CONFIG_SYS_CS2_FTIM2\t\tCONFIG_SYS_NOR_FTIM2\n+#define CONFIG_SYS_CS2_FTIM3\t\tCONFIG_SYS_NOR_FTIM3\n+#define CONFIG_SYS_CSPR3_EXT\t\tCONFIG_SYS_FPGA_CSPR_EXT\n+#define CONFIG_SYS_CSPR3\t\tCONFIG_SYS_FPGA_CSPR\n+#define CONFIG_SYS_AMASK3\t\tCONFIG_SYS_FPGA_AMASK\n+#define CONFIG_SYS_CSOR3\t\tCONFIG_SYS_FPGA_CSOR\n+#define CONFIG_SYS_CS3_FTIM0\t\tCONFIG_SYS_FPGA_FTIM0\n+#define CONFIG_SYS_CS3_FTIM1\t\tCONFIG_SYS_FPGA_FTIM1\n+#define CONFIG_SYS_CS3_FTIM2\t\tCONFIG_SYS_FPGA_FTIM2\n+#define CONFIG_SYS_CS3_FTIM3\t\tCONFIG_SYS_FPGA_FTIM3\n+#else\n #define CONFIG_SYS_CSPR0_EXT\t\tCONFIG_SYS_NOR0_CSPR_EXT\n #define CONFIG_SYS_CSPR0\t\tCONFIG_SYS_NOR0_CSPR\n #define CONFIG_SYS_AMASK0\t\tCONFIG_SYS_NOR_AMASK\n@@ -281,6 +348,7 @@ unsigned long get_board_ddr_clk(void);\n #define CONFIG_SYS_CS3_FTIM1\t\tCONFIG_SYS_FPGA_FTIM1\n #define CONFIG_SYS_CS3_FTIM2\t\tCONFIG_SYS_FPGA_FTIM2\n #define CONFIG_SYS_CS3_FTIM3\t\tCONFIG_SYS_FPGA_FTIM3\n+#endif\n \n /*\n * Serial Port\n", "prefixes": [ "U-Boot", "v3", "8/8" ] }