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GET /api/patches/400439/?format=api
{ "id": 400439, "url": "http://patchwork.ozlabs.org/api/patches/400439/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1413533175-28185-1-git-send-email-b18965@freescale.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1413533175-28185-1-git-send-email-b18965@freescale.com>", "list_archive_url": null, "date": "2014-10-17T08:06:15", "name": "[U-Boot,v3,7/8] arm: ls102xa: Add SD boot support for LS1021ATWR board", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "84806c67444d037965842c7ac4714e56c811f92d", "submitter": { "id": 13010, "url": "http://patchwork.ozlabs.org/api/people/13010/?format=api", "name": "Alison Wang", "email": "b18965@freescale.com" }, "delegate": { "id": 2666, "url": "http://patchwork.ozlabs.org/api/users/2666/?format=api", "username": "yorksun", "first_name": "York", "last_name": "Sun", "email": "yorksun@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1413533175-28185-1-git-send-email-b18965@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/400439/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/400439/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id 8D32D1400EA\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 17 Oct 2014 19:07:08 +1100 (AEDT)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 7D0514B605;\n\tFri, 17 Oct 2014 10:07:06 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id zlzETsT9YZSj; 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Fri, 17 Oct 2014\n\t08:06:51 +0000", "from titan.ap.freescale.net ([10.192.208.233])\n\tby az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id\n\ts9H86nIV026280; Fri, 17 Oct 2014 01:06:49 -0700" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "Alison Wang <b18965@freescale.com>", "To": "<yorksun@freescale.com>, <u-boot@lists.denx.de>", "Date": "Fri, 17 Oct 2014 16:06:15 +0800", "Message-ID": "<1413533175-28185-1-git-send-email-b18965@freescale.com>", "X-Mailer": "git-send-email 2.1.0.27.g96db324", "X-EOPAttributedMessage": "0", "X-Forefront-Antispam-Report": "CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI;\n\tEFV:NLI; SFV:NSPM;\n\tSFS:(10019020)(6009001)(199003)(54534003)(189002)(85852003)(87936001)(89996001)(87286001)(93916002)(92566001)(92726001)(88136002)(50986999)(77156001)(81156004)(62966002)(36756003)(106466001)(44976005)(64706001)(31966008)(95666004)(48376002)(99396003)(105606002)(85306004)(107046002)(20776003)(21056001)(47776003)(97736003)(229853001)(120916001)(26826002)(6806004)(33646002)(69596002)(84676001)(4396001)(19580395003)(102836001)(19580405001)(50226001)(50466002)(68736004)(104016003)(104166001)(46102003)(76482002)(80022003)(42262002);\n\tDIR:OUT; SFP:1102; SCL:1; SRVR:BLUPR03MB373;\n\tH:az84smr01.freescale.net; FPR:; MLV:ovrnspm;\n\tPTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; ", "MIME-Version": "1.0", "X-Microsoft-Antispam": [ "UriScan:;", "BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB373;" ], "X-Exchange-Antispam-Report-Test": "UriScan:;", "X-Forefront-PRVS": "0367A50BB1", "Received-SPF": "Fail (protection.outlook.com: domain of freescale.com does not\n\tdesignate 192.88.158.2 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.158.2; helo=az84smr01.freescale.net;", "Authentication-Results": "spf=fail (sender IP is 192.88.158.2)\n\tsmtp.mailfrom=alison.wang@freescale.com; ", "X-OriginatorOrg": "freescale.com", "Subject": "[U-Boot] [PATCH v3 7/8] arm: ls102xa: Add SD boot support for\n\tLS1021ATWR board", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.13", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "u-boot-bounces@lists.denx.de", "Errors-To": "u-boot-bounces@lists.denx.de" }, "content": "This patch adds SD boot support for LS1021ATWR board. SPL\nframework is used. PBL initialize the internal RAM and copy\nSPL to it, then SPL initialize DDR using SPD and copy u-boot\nfrom SD card to DDR, finally SPL transfer control to u-boot.\n\nSigned-off-by: Chen Lu <chen.lu@freescale.com>\nSigned-off-by: Alison Wang <alison.wang@freescale.com>\nSigned-off-by: Jason Jin <jason.jin@freescale.com>\n---\nChange log:\n v3: Update MAINTAINERS file.\n Update PBI and RCW for SD boot.\n v2: Use generic u-boot-spl.lds.\n\n board/freescale/ls1021atwr/MAINTAINERS | 1 +\n board/freescale/ls1021atwr/ls1021atwr.c | 30 ++++++++++++++++\n board/freescale/ls1021atwr/ls102xa_pbi.cfg | 12 +++++++\n board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg | 14 ++++++++\n configs/ls1021atwr_sdcard_defconfig | 4 +++\n include/configs/ls1021atwr.h | 51 +++++++++++++++++++++++++++\n 6 files changed, 112 insertions(+)\n create mode 100644 board/freescale/ls1021atwr/ls102xa_pbi.cfg\n create mode 100644 board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg\n create mode 100644 configs/ls1021atwr_sdcard_defconfig", "diff": "diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS\nindex 4e5bc15..651d43e 100644\n--- a/board/freescale/ls1021atwr/MAINTAINERS\n+++ b/board/freescale/ls1021atwr/MAINTAINERS\n@@ -4,3 +4,4 @@ S:\tMaintained\n F:\tboard/freescale/ls1021atwr/\n F:\tinclude/configs/ls1021atwr.h\n F:\tconfigs/ls1021atwr_nor_defconfig\n+F:\tconfigs/ls1021atwr_sdcard_defconfig\ndiff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c\nindex ff7130e..d82602d 100644\n--- a/board/freescale/ls1021atwr/ls1021atwr.c\n+++ b/board/freescale/ls1021atwr/ls1021atwr.c\n@@ -16,6 +16,7 @@\n #include <netdev.h>\n #include <fsl_mdio.h>\n #include <tsec.h>\n+#include <spl.h>\n \n DECLARE_GLOBAL_DATA_PTR;\n \n@@ -65,6 +66,7 @@ struct cpld_data {\n \tu8 rev2;\t\t/* Reserved */\n };\n \n+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)\n static void convert_serdes_mux(int type, int need_reset);\n \n void cpld_show(void)\n@@ -100,11 +102,14 @@ void cpld_show(void)\n \t in_8(&cpld_data->serdes_mux));\n #endif\n }\n+#endif\n \n int checkboard(void)\n {\n \tputs(\"Board: LS1021ATWR\\n\");\n+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)\n \tcpld_show();\n+#endif\n \n \treturn 0;\n }\n@@ -213,6 +218,7 @@ int board_eth_init(bd_t *bis)\n }\n #endif\n \n+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)\n int config_serdes_mux(void)\n {\n \tstruct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);\n@@ -244,6 +250,7 @@ int config_serdes_mux(void)\n \n \treturn 0;\n }\n+#endif\n \n int board_early_init_f(void)\n {\n@@ -265,6 +272,25 @@ int board_early_init_f(void)\n \treturn 0;\n }\n \n+#ifdef CONFIG_SPL_BUILD\n+void board_init_f(ulong dummy)\n+{\n+\t/* Set global data pointer */\n+\tgd = &gdata;\n+\n+\t/* Clear the BSS */\n+\tmemset(__bss_start, 0, __bss_end - __bss_start);\n+\n+\tget_clocks();\n+\n+\tpreloader_console_init();\n+\n+\tdram_init();\n+\n+\tboard_init_r(NULL, 0);\n+}\n+#endif\n+\n int board_init(void)\n {\n \tstruct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;\n@@ -279,8 +305,10 @@ int board_init(void)\n \n #ifndef CONFIG_SYS_FSL_NO_SERDES\n \tfsl_serdes_init();\n+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)\n \tconfig_serdes_mux();\n #endif\n+#endif\n \n \treturn 0;\n }\n@@ -309,6 +337,7 @@ u16 flash_read16(void *addr)\n \treturn (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);\n }\n \n+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)\n static void convert_flash_bank(char bank)\n {\n \tstruct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);\n@@ -491,3 +520,4 @@ U_BOOT_CMD(\n \t\"\t-change lane C & lane D to PCIeX2\\n\"\n \t\"\\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\\n\"\n );\n+#endif\ndiff --git a/board/freescale/ls1021atwr/ls102xa_pbi.cfg b/board/freescale/ls1021atwr/ls102xa_pbi.cfg\nnew file mode 100644\nindex 0000000..f1a1b63\n--- /dev/null\n+++ b/board/freescale/ls1021atwr/ls102xa_pbi.cfg\n@@ -0,0 +1,12 @@\n+#PBI commands\n+\n+09570200 ffffffff\n+09570158 00000300\n+8940007c 21f47300\n+\n+#Configure Scratch register\n+09ee0200 10000000\n+#Configure alternate space\n+09570158 00001000\n+#Flush PBL data\n+096100c0 000FFFFF\ndiff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg\nnew file mode 100644\nindex 0000000..911489b\n--- /dev/null\n+++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg\n@@ -0,0 +1,14 @@\n+#PBL preamble and RCW header\n+aa55aa55 01ee0100\n+\n+#enable IFC, disable QSPI and DSPI\n+#0608000a 00000000 00000000 00000000\n+#20000000 00404000 60025a00 21042000\n+#00200000 00000000 00000000 01038000\n+#00000000 001b1200 00000000 00000000\n+\n+#disable IFC, enable QSPI and DSPI\n+0608000a 00000000 00000000 00000000\n+20000000 00407900 60025a00 21046000\n+00000000 00000000 00000000 00038000\n+20024800 881b7540 00000000 00000000\ndiff --git a/configs/ls1021atwr_sdcard_defconfig b/configs/ls1021atwr_sdcard_defconfig\nnew file mode 100644\nindex 0000000..0eb556a\n--- /dev/null\n+++ b/configs/ls1021atwr_sdcard_defconfig\n@@ -0,0 +1,4 @@\n+CONFIG_SPL=y\n+CONFIG_SYS_EXTRA_OPTIONS=\"RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT\"\n++S:CONFIG_ARM=y\n++S:CONFIG_TARGET_LS1021ATWR=y\ndiff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h\nindex 1914e3d..9c8ef68 100644\n--- a/include/configs/ls1021atwr.h\n+++ b/include/configs/ls1021atwr.h\n@@ -35,6 +35,39 @@\n #define CONFIG_SYS_CLK_FREQ\t\t100000000\n #define CONFIG_DDR_CLK_FREQ\t\t100000000\n \n+#ifdef CONFIG_RAMBOOT_PBL\n+#define CONFIG_SYS_FSL_PBL_PBI\tboard/freescale/ls1021atwr/ls102xa_pbi.cfg\n+#endif\n+\n+#ifdef CONFIG_SD_BOOT\n+#define CONFIG_SYS_FSL_PBL_RCW\tboard/freescale/ls1021atwr/ls102xa_rcw_sd.cfg\n+#define CONFIG_SPL_FRAMEWORK\n+#define CONFIG_SPL_LDSCRIPT\t\"arch/$(ARCH)/cpu/u-boot-spl.lds\"\n+#define CONFIG_SPL_LIBCOMMON_SUPPORT\n+#define CONFIG_SPL_LIBGENERIC_SUPPORT\n+#define CONFIG_SPL_ENV_SUPPORT\n+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT\n+#define CONFIG_SPL_I2C_SUPPORT\n+#define CONFIG_SPL_WATCHDOG_SUPPORT\n+#define CONFIG_SPL_SERIAL_SUPPORT\n+#define CONFIG_SPL_MMC_SUPPORT\n+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR\t\t0xe8\n+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS\t\t0x400\n+\n+#define CONFIG_SPL_TEXT_BASE\t\t0x10000000\n+#define CONFIG_SPL_MAX_SIZE\t\t0x1a000\n+#define CONFIG_SPL_STACK\t\t0x1001d000\n+#define CONFIG_SPL_PAD_TO\t\t0x1c000\n+#define CONFIG_SYS_TEXT_BASE\t\t0x82000000\n+\n+#define CONFIG_SYS_SPL_MALLOC_START\t0x80200000\n+#define CONFIG_SYS_SPL_MALLOC_SIZE\t0x100000\n+#define CONFIG_SPL_BSS_START_ADDR\t0x80100000\n+#define CONFIG_SPL_BSS_MAX_SIZE\t\t0x80000\n+#define CONFIG_SYS_MONITOR_LEN\t\t0x80000\n+#define CONFIG_SYS_NO_FLASH\n+#endif\n+\n #ifndef CONFIG_SYS_TEXT_BASE\n #define CONFIG_SYS_TEXT_BASE\t\t0x67f80000\n #endif\n@@ -51,6 +84,7 @@\n /*\n * IFC Definitions\n */\n+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)\n #define CONFIG_FSL_IFC\n #define CONFIG_SYS_FLASH_BASE\t\t0x60000000\n #define CONFIG_SYS_FLASH_BASE_PHYS\tCONFIG_SYS_FLASH_BASE\n@@ -94,6 +128,7 @@\n \n #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS\n #define CONFIG_SYS_WRITE_SWAPPED_DATA\n+#endif\n \n /* CPLD */\n \n@@ -237,7 +272,12 @@\n \n #define CONFIG_CMDLINE_TAG\n #define CONFIG_CMDLINE_EDITING\n+\n+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)\n #define CONFIG_CMD_IMLS\n+#else\n+#undef CONFIG_CMD_IMLS\n+#endif\n \n #define CONFIG_HWCONFIG\n #define HWCONFIG_BUFFER_SIZE\t\t128\n@@ -284,17 +324,28 @@\n #define CONFIG_SYS_INIT_SP_ADDR \\\n \t(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)\n \n+#ifdef CONFIG_SPL_BUILD\n+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE\n+#else\n #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */\n+#endif\n \n /*\n * Environment\n */\n #define CONFIG_ENV_OVERWRITE\n \n+#if defined(CONFIG_SD_BOOT)\n+#define CONFIG_ENV_OFFSET\t\t(1024 * 1024)\n+#define CONFIG_ENV_IS_IN_MMC\n+#define CONFIG_SYS_MMC_ENV_DEV\t\t0\n+#define CONFIG_ENV_SIZE\t\t\t0x20000\n+#else\n #define CONFIG_ENV_IS_IN_FLASH\n #define CONFIG_ENV_ADDR\t\t(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)\n #define CONFIG_ENV_SIZE\t\t\t0x20000\n #define CONFIG_ENV_SECT_SIZE\t\t0x20000 /* 128K (one sector) */\n+#endif\n \n #define CONFIG_OF_LIBFDT\n #define CONFIG_OF_BOARD_SETUP\n", "prefixes": [ "U-Boot", "v3", "7/8" ] }