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GET /api/patches/400121/?format=api
{ "id": 400121, "url": "http://patchwork.ozlabs.org/api/patches/400121/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/patch/1413428973-29982-1-git-send-email-Li.Xiubo@freescale.com/", "project": { "id": 19, "url": "http://patchwork.ozlabs.org/api/projects/19/?format=api", "name": "Linux IMX development", "link_name": "linux-imx", "list_id": "linux-imx-kernel.lists.patchwork.ozlabs.org", "list_email": "linux-imx-kernel@lists.patchwork.ozlabs.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1413428973-29982-1-git-send-email-Li.Xiubo@freescale.com>", "list_archive_url": null, "date": "2014-10-16T03:09:33", "name": "[v4] ARM: ls1021a: add gating clocks to IP blocks.", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "42624d612cc9cc8b154373901b9fa93f32433e35", "submitter": { "id": 44085, "url": "http://patchwork.ozlabs.org/api/people/44085/?format=api", "name": "Xiubo Li", "email": "Li.Xiubo@freescale.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-imx/patch/1413428973-29982-1-git-send-email-Li.Xiubo@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/400121/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/400121/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming-imx@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-imx@bilbo.ozlabs.org", "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n\t[IPv6:2001:1868:205::9])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3B3571400D2\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tThu, 16 Oct 2014 14:15:14 +1100 (EST)", "from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux))\n\tid 1XebSZ-0005zC-RE; Thu, 16 Oct 2014 03:10:39 +0000", "from mail-by2on0145.outbound.protection.outlook.com\n\t([207.46.100.145] helo=na01-by2-obe.outbound.protection.outlook.com)\n\tby bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat\n\tLinux)) id 1XebSV-0005mk-7L\n\tfor linux-arm-kernel@lists.infradead.org;\n\tThu, 16 Oct 2014 03:10:36 +0000", "from BN3PR0301CA0074.namprd03.prod.outlook.com (25.160.152.170) by\n\tBN1PR0301MB0610.namprd03.prod.outlook.com (25.160.170.25) with\n\tMicrosoft SMTP\n\tServer (TLS) id 15.0.1049.19; Thu, 16 Oct 2014 03:10:11 +0000", "from BY2FFO11FD041.protection.gbl (2a01:111:f400:7c0c::112) by\n\tBN3PR0301CA0074.outlook.office365.com (2a01:111:e400:401e::42) with\n\tMicrosoft SMTP Server (TLS) id 15.0.1054.13 via Frontend Transport;\n\tThu, 16 Oct 2014 03:10:11 +0000", "from az84smr01.freescale.net (192.88.158.2) by\n\tBY2FFO11FD041.mail.protection.outlook.com (10.1.14.226) with\n\tMicrosoft SMTP\n\tServer (TLS) id 15.0.1039.16 via Frontend Transport; Thu, 16 Oct 2014\n\t03:10:11 +0000", "from titan.ap.freescale.net ([10.192.208.233])\n\tby az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id\n\ts9G3A7SH011360; Wed, 15 Oct 2014 20:10:08 -0700" ], "From": "Xiubo Li <Li.Xiubo@freescale.com>", "To": "<shawn.guo@linaro.org>", "Subject": "[PATCH v4] ARM: ls1021a: add gating clocks to IP blocks.", "Date": "Thu, 16 Oct 2014 11:09:33 +0800", "Message-ID": "<1413428973-29982-1-git-send-email-Li.Xiubo@freescale.com>", "X-Mailer": "git-send-email 2.1.0.27.g96db324", "X-EOPAttributedMessage": "0", "X-Forefront-Antispam-Report": "CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI;\n\tEFV:NLI; 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sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.158.2; helo=az84smr01.freescale.net;", "Authentication-Results": "spf=fail (sender IP is 192.88.158.2)\n\tsmtp.mailfrom=Li.Xiubo@freescale.com; ", "X-OriginatorOrg": "freescale.com", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20141015_201035_391216_ADF0F719 ", "X-CRM114-Status": "GOOD ( 16.25 )", "X-Spam-Score": "-0.2 (/)", "X-Spam-Report": "SpamAssassin version 3.4.0 on bombadil.infradead.org summary:\n\tContent analysis details: (-0.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [207.46.100.145 listed in list.dnswl.org]\n\t-0.2 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2)\n\t[207.46.100.145 listed in wl.mailspike.net]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 SPF_HELO_PASS SPF: HELO matches SPF record", "Cc": "Xiubo Li <Li.Xiubo@freescale.com>, linux-arm-kernel@lists.infradead.org", "X-BeenThere": "linux-arm-kernel@lists.infradead.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-arm-kernel/>", "List-Post": "<mailto:linux-arm-kernel@lists.infradead.org>", "List-Help": "<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>", "Errors-To": "linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org", "List-Id": "linux-imx-kernel.lists.patchwork.ozlabs.org" }, "content": "A given application may not use all the peripherals on the device.\nIn this case, it may be desirable to disable unused peripherals.\nDCFG provides a mechanism for gating clocks to IP blocks that are\nnot used when running an application.\n\nSigned-off-by: Xiubo Li <Li.Xiubo@freescale.com>\n---\n\nChange in V4:\n- Convert all the bits BE as default.\n- Follow some tips from Shawn to be the same with other clk drivers of fsl.\n\n\n\n .../devicetree/bindings/clock/ls1021a-clock.txt | 27 +++\n arch/arm/mach-imx/Makefile | 2 +\n arch/arm/mach-imx/clk-ls1021a.c | 191 +++++++++++++++++++++\n arch/arm/mach-imx/clk.h | 8 +\n include/dt-bindings/clock/ls1021a-clock.h | 55 ++++++\n 5 files changed, 283 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/clock/ls1021a-clock.txt\n create mode 100644 arch/arm/mach-imx/clk-ls1021a.c\n create mode 100644 include/dt-bindings/clock/ls1021a-clock.h", "diff": "diff --git a/Documentation/devicetree/bindings/clock/ls1021a-clock.txt b/Documentation/devicetree/bindings/clock/ls1021a-clock.txt\nnew file mode 100644\nindex 0000000..e53d976\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/clock/ls1021a-clock.txt\n@@ -0,0 +1,27 @@\n+Gating clock bindings for Freescale LS1021A SOC\n+\n+Required properties:\n+- compatible:\t\tShould be \"fsl,ls1021a-gate\"\n+- reg:\t\t\tAddress and length of the register set\n+- #clock-cells:\t\tShould be <1>\n+\n+The clock consumers should specify the desired clock by having one clock\n+ID in its \"clocks\" phandle cell.\n+Please see include/dt-bindings/clock/ls1021a-clock.h for the full list of\n+LS1021A clock IDs.\n+\n+Example:\n+\n+gate: gate@1ee0000 {\n+\tcompatible = \"fsl,ls1021a-gate\";\n+\treg = <0x0 0x1ee0000 0x0 0x10000>;\n+\t#clock-cells = <1>;\n+};\n+\n+wdog0: wdog@2ad0000 {\n+\tcompatible = \"fsl,ls1021a-wdt\", \"fsl,imx21-wdt\";\n+\treg = <0x0 0x2ad0000 0x0 0x10000>;\n+\tinterrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;\n+\tclocks = <&gate LS1021A_CLK_WDOG12_EN>;\n+\tclock-names = \"wdog12_en\";\n+};\ndiff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile\nindex 6e4fcd8..f6a1544 100644\n--- a/arch/arm/mach-imx/Makefile\n+++ b/arch/arm/mach-imx/Makefile\n@@ -110,4 +110,6 @@ obj-$(CONFIG_SOC_IMX53) += mach-imx53.o\n \n obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o\n \n+obj-$(CONFIG_SOC_LS1021A) += clk-ls1021a.o\n+\n obj-y += devices/\ndiff --git a/arch/arm/mach-imx/clk-ls1021a.c b/arch/arm/mach-imx/clk-ls1021a.c\nnew file mode 100644\nindex 0000000..bba7c9a\n--- /dev/null\n+++ b/arch/arm/mach-imx/clk-ls1021a.c\n@@ -0,0 +1,191 @@\n+/*\n+ * Copyright 2014 Freescale Semiconductor, Inc.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ */\n+\n+#include <linux/clk.h>\n+#include <linux/mfd/syscon.h>\n+#include <linux/of_address.h>\n+#include <linux/slab.h>\n+#include <dt-bindings/clock/ls1021a-clock.h>\n+\n+#include \"clk.h\"\n+\n+static struct clk *clks[LS1021A_CLK_END];\n+static struct clk_onecell_data clk_data;\n+\n+/* The DCFG registers are in big endian mode on LS1021A SoC */\n+static u8 ls1021a_clk_shift_be(u8 shift)\n+{\n+\tu8 m, n;\n+\n+\tm = shift / 8;\n+\tn = shift % 8;\n+\n+\treturn (u8)((3 - m) * 8 + n);\n+}\n+\n+static void __init ls1021a_clocks_init(struct device_node *np)\n+{\n+\tstatic void __iomem *dcfg_base;\n+\tint i;\n+\n+#define DCFG_CCSR_DEVDISR1\t(dcfg_base + 0x70)\n+#define DCFG_CCSR_DEVDISR2\t(dcfg_base + 0x74)\n+#define DCFG_CCSR_DEVDISR3\t(dcfg_base + 0x78)\n+#define DCFG_CCSR_DEVDISR4\t(dcfg_base + 0x7c)\n+#define DCFG_CCSR_DEVDISR5\t(dcfg_base + 0x80)\n+#define DCFG_CCSR_RSTRQMR1\t(dcfg_base + 0xc0)\n+\n+\tif (dcfg_base) {\n+\t\tpr_warn(\"LS1021A gate clk has already added.\\n\");\n+\t\treturn;\n+\t}\n+\n+\tdcfg_base = of_iomap(np, 0);\n+\n+\tBUG_ON(!dcfg_base);\n+\n+\tclks[LS1021A_CLK_PBL_EN] = ls1021a_clk_gate(\"pbl_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR1,\n+\t\t\t\t\t\tls1021a_clk_shift_be(0));\n+\tclks[LS1021A_CLK_ESDHC_EN] = ls1021a_clk_gate(\"esdhc_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR1,\n+\t\t\t\t\t\tls1021a_clk_shift_be(2));\n+\tclks[LS1021A_CLK_DMA1_EN] = ls1021a_clk_gate(\"dma1_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR1,\n+\t\t\t\t\t\tls1021a_clk_shift_be(8));\n+\tclks[LS1021A_CLK_DMA2_EN] = ls1021a_clk_gate(\"dma2_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR1,\n+\t\t\t\t\t\tls1021a_clk_shift_be(9));\n+\tclks[LS1021A_CLK_USB3_PHY_EN] = ls1021a_clk_gate(\"usb3_phy_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR1,\n+\t\t\t\t\t\tls1021a_clk_shift_be(12));\n+\tclks[LS1021A_CLK_USB2_EN] = ls1021a_clk_gate(\"usb2_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR1,\n+\t\t\t\t\t\tls1021a_clk_shift_be(13));\n+\tclks[LS1021A_CLK_SATA_EN] = ls1021a_clk_gate(\"sata_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR1,\n+\t\t\t\t\t\tls1021a_clk_shift_be(16));\n+\tclks[LS1021A_CLK_USB3_EN] = ls1021a_clk_gate(\"usb3_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR1,\n+\t\t\t\t\t\tls1021a_clk_shift_be(17));\n+\tclks[LS1021A_CLK_SEC_EN] = ls1021a_clk_gate(\"sec_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR1,\n+\t\t\t\t\t\tls1021a_clk_shift_be(22));\n+\tclks[LS1021A_CLK_2D_ACE_EN] = ls1021a_clk_gate(\"2d_ace_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR1,\n+\t\t\t\t\t\tls1021a_clk_shift_be(30));\n+\tclks[LS1021A_CLK_QE_EN] = ls1021a_clk_gate(\"qe_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR1,\n+\t\t\t\t\t\tls1021a_clk_shift_be(31));\n+\n+\tclks[LS1021A_CLK_ETSEC1_EN] = ls1021a_clk_gate(\"etsec1_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR2,\n+\t\t\t\t\t\tls1021a_clk_shift_be(0));\n+\tclks[LS1021A_CLK_ETSEC2_EN] = ls1021a_clk_gate(\"etsec2_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR2,\n+\t\t\t\t\t\tls1021a_clk_shift_be(1));\n+\tclks[LS1021A_CLK_ETSEC3_EN] = ls1021a_clk_gate(\"etsec3_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR2,\n+\t\t\t\t\t\tls1021a_clk_shift_be(2));\n+\n+\tclks[LS1021A_CLK_PEX1_EN] = ls1021a_clk_gate(\"pex1_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR3,\n+\t\t\t\t\t\tls1021a_clk_shift_be(0));\n+\tclks[LS1021A_CLK_PEX2_EN] = ls1021a_clk_gate(\"pex2_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR3,\n+\t\t\t\t\t\tls1021a_clk_shift_be(1));\n+\n+\tclks[LS1021A_CLK_DUART1_EN] = ls1021a_clk_gate(\"duart1_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR4,\n+\t\t\t\t\t\tls1021a_clk_shift_be(2));\n+\tclks[LS1021A_CLK_DUART2_EN] = ls1021a_clk_gate(\"duart2_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR4,\n+\t\t\t\t\t\tls1021a_clk_shift_be(3));\n+\tclks[LS1021A_CLK_QSPI_EN] = ls1021a_clk_gate(\"qspi_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR4,\n+\t\t\t\t\t\tls1021a_clk_shift_be(4));\n+\n+\tclks[LS1021A_CLK_DDR_EN] = ls1021a_clk_gate(\"ddr_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5,\n+\t\t\t\t\t\tls1021a_clk_shift_be(0));\n+\tclks[LS1021A_CLK_OCRAM1_EN] = ls1021a_clk_gate(\"ocram1_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5,\n+\t\t\t\t\t\tls1021a_clk_shift_be(4));\n+\tclks[LS1021A_CLK_IFC_EN] = ls1021a_clk_gate(\"ifc_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5,\n+\t\t\t\t\t\tls1021a_clk_shift_be(8));\n+\tclks[LS1021A_CLK_GPIO_EN] = ls1021a_clk_gate(\"gpio_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5,\n+\t\t\t\t\t\tls1021a_clk_shift_be(9));\n+\tclks[LS1021A_CLK_DBG_EN] = ls1021a_clk_gate(\"dbg_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5,\n+\t\t\t\t\t\tls1021a_clk_shift_be(10));\n+\tclks[LS1021A_CLK_FLEXCAN1_EN] = ls1021a_clk_gate(\"flexcan1_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5,\n+\t\t\t\t\t\tls1021a_clk_shift_be(12));\n+\tclks[LS1021A_CLK_FLEXCAN234_EN] = ls1021a_clk_gate(\"flexcan234_en\",\n+\t\t\t\t\t\t\"dummy\", DCFG_CCSR_DEVDISR5,\n+\t\t\t\t\t\tls1021a_clk_shift_be(13));\n+\t/* For flextimer 2/3/4/5/6/7/8 */\n+\tclks[LS1021A_CLK_FLEXTIMER_EN] = ls1021a_clk_gate(\"flextimer_en\",\n+\t\t\t\t\t\t\"dummy\", DCFG_CCSR_DEVDISR5,\n+\t\t\t\t\t\tls1021a_clk_shift_be(14));\n+\tclks[LS1021A_CLK_SECMON_EN] = ls1021a_clk_gate(\"secmon_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5,\n+\t\t\t\t\t\tls1021a_clk_shift_be(17));\n+\tclks[LS1021A_CLK_WDOG_EN] = ls1021a_clk_gate(\"wdog_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_RSTRQMR1,\n+\t\t\t\t\t\tls1021a_clk_shift_be(22));\n+\tclks[LS1021A_CLK_WDOG12_EN] = ls1021a_clk_gate(\"wdog12_en\", \"wdog_en\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5,\n+\t\t\t\t\t\tls1021a_clk_shift_be(21));\n+\tclks[LS1021A_CLK_I2C23_EN] = ls1021a_clk_gate(\"i2c23_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5,\n+\t\t\t\t\t\tls1021a_clk_shift_be(22));\n+\t/* For SAI 1/2/3/4 */\n+\tclks[LS1021A_CLK_SAI_EN] = ls1021a_clk_gate(\"sai_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5,\n+\t\t\t\t\t\tls1021a_clk_shift_be(23));\n+\t/* For lpuart 2/3/4/5/6 */\n+\tclks[LS1021A_CLK_LPUART_EN] = ls1021a_clk_gate(\"lpuart_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5,\n+\t\t\t\t\t\tls1021a_clk_shift_be(24));\n+\tclks[LS1021A_CLK_DSPI12_EN] = ls1021a_clk_gate(\"dspi12_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5,\n+\t\t\t\t\t\tls1021a_clk_shift_be(25));\n+\tclks[LS1021A_CLK_ASRC_EN] = ls1021a_clk_gate(\"asrc_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5,\n+\t\t\t\t\t\tls1021a_clk_shift_be(26));\n+\tclks[LS1021A_CLK_SPDIF_EN] = ls1021a_clk_gate(\"spdif_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5,\n+\t\t\t\t\t\tls1021a_clk_shift_be(27));\n+\tclks[LS1021A_CLK_I2C1_EN] = ls1021a_clk_gate(\"i2c1_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5,\n+\t\t\t\t\t\tls1021a_clk_shift_be(29));\n+\tclks[LS1021A_CLK_LPUART1_EN] = ls1021a_clk_gate(\"lpuart1_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5,\n+\t\t\t\t\t\tls1021a_clk_shift_be(30));\n+\tclks[LS1021A_CLK_FLEXTIMER1_EN] = ls1021a_clk_gate(\"flextimer1_en\",\n+\t\t\t\t\t\t\"dummy\", DCFG_CCSR_DEVDISR5,\n+\t\t\t\t\t\tls1021a_clk_shift_be(31));\n+\n+\tfor (i = 0; i < LS1021A_CLK_END; i++) {\n+\t\tif (IS_ERR(clks[i])) {\n+\t\t\tpr_err(\"LS1021A clk %d: register failed with %ld\\n\",\n+\t\t\t i, PTR_ERR(clks[i]));\n+\t\t\tBUG();\n+\t\t}\n+\t}\n+\n+\t/* Add the clocks to provider list */\n+\tclk_data.clks = clks;\n+\tclk_data.clk_num = LS1021A_CLK_END;\n+\tof_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);\n+}\n+CLK_OF_DECLARE(ls1021a, \"fsl,ls1021a-gate\", ls1021a_clocks_init);\ndiff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h\nindex 4cdf8b6..cfbae8c 100644\n--- a/arch/arm/mach-imx/clk.h\n+++ b/arch/arm/mach-imx/clk.h\n@@ -107,6 +107,14 @@ static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,\n \t\t\tshift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);\n }\n \n+static inline struct clk *ls1021a_clk_gate(const char *name, const char *parent,\n+\t\tvoid __iomem *reg, u8 shift)\n+{\n+\treturn clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT |\n+\t\t\tCLK_IGNORE_UNUSED, reg,\tshift,\n+\t\t\tCLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);\n+}\n+\n static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,\n \t\tu8 shift, u8 width, const char **parents, int num_parents)\n {\ndiff --git a/include/dt-bindings/clock/ls1021a-clock.h b/include/dt-bindings/clock/ls1021a-clock.h\nnew file mode 100644\nindex 0000000..09b47d7\n--- /dev/null\n+++ b/include/dt-bindings/clock/ls1021a-clock.h\n@@ -0,0 +1,55 @@\n+/*\n+ * Copyright 2014 Freescale Semiconductor, Inc.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ */\n+\n+#ifndef __DT_BINDINGS_CLOCK_LS1021A_H\n+#define __DT_BINDINGS_CLOCK_LS1021A_H\n+\n+#define LS1021A_CLK_DUMMY\t0\n+#define LS1021A_CLK_PBL_EN\t1\n+#define LS1021A_CLK_ESDHC_EN\t2\n+#define LS1021A_CLK_DMA1_EN\t3\n+#define LS1021A_CLK_DMA2_EN\t4\n+#define LS1021A_CLK_USB3_PHY_EN\t5\n+#define LS1021A_CLK_USB2_EN\t6\n+#define LS1021A_CLK_SATA_EN\t7\n+#define LS1021A_CLK_USB3_EN\t8\n+#define LS1021A_CLK_SEC_EN\t9\n+#define LS1021A_CLK_2D_ACE_EN\t10\n+#define LS1021A_CLK_QE_EN\t11\n+#define LS1021A_CLK_ETSEC1_EN\t12\n+#define LS1021A_CLK_ETSEC2_EN\t13\n+#define LS1021A_CLK_ETSEC3_EN\t14\n+#define LS1021A_CLK_PEX1_EN\t15\n+#define LS1021A_CLK_PEX2_EN\t16\n+#define LS1021A_CLK_DUART1_EN\t17\n+#define LS1021A_CLK_DUART2_EN\t18\n+#define LS1021A_CLK_QSPI_EN\t19\n+#define LS1021A_CLK_DDR_EN\t20\n+#define LS1021A_CLK_OCRAM1_EN\t21\n+#define LS1021A_CLK_IFC_EN\t22\n+#define LS1021A_CLK_GPIO_EN\t23\n+#define LS1021A_CLK_DBG_EN\t24\n+#define LS1021A_CLK_FLEXCAN1_EN\t25\n+#define LS1021A_CLK_FLEXCAN234_EN\t26\n+#define LS1021A_CLK_FLEXTIMER_EN\t27\n+#define LS1021A_CLK_SECMON_EN\t28\n+#define LS1021A_CLK_WDOG_EN\t29\n+#define LS1021A_CLK_WDOG12_EN\t30\n+#define LS1021A_CLK_I2C23_EN\t31\n+#define LS1021A_CLK_SAI_EN\t32\n+#define LS1021A_CLK_LPUART_EN\t33\n+#define LS1021A_CLK_DSPI12_EN\t34\n+#define LS1021A_CLK_ASRC_EN\t35\n+#define LS1021A_CLK_SPDIF_EN\t36\n+#define LS1021A_CLK_I2C1_EN\t37\n+#define LS1021A_CLK_LPUART1_EN\t38\n+#define LS1021A_CLK_FLEXTIMER1_EN\t39\n+#define LS1021A_CLK_END\t\t40\n+\n+#endif /* __DT_BINDINGS_CLOCK_LS1021A_H */\n", "prefixes": [ "v4" ] }