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GET /api/patches/391216/?format=api
{ "id": 391216, "url": "http://patchwork.ozlabs.org/api/patches/391216/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/patch/1411123047-7544-1-git-send-email-Li.Xiubo@freescale.com/", "project": { "id": 19, "url": "http://patchwork.ozlabs.org/api/projects/19/?format=api", "name": "Linux IMX development", "link_name": "linux-imx", "list_id": "linux-imx-kernel.lists.patchwork.ozlabs.org", "list_email": "linux-imx-kernel@lists.patchwork.ozlabs.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1411123047-7544-1-git-send-email-Li.Xiubo@freescale.com>", "list_archive_url": null, "date": "2014-09-19T10:37:27", "name": "ARM: ls1021a: add gating clocks to IP blocks.", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0487c1f3fa2cbd7feeb2668cba16c46418092e49", "submitter": { "id": 44085, "url": "http://patchwork.ozlabs.org/api/people/44085/?format=api", "name": "Xiubo Li", "email": "Li.Xiubo@freescale.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-imx/patch/1411123047-7544-1-git-send-email-Li.Xiubo@freescale.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/391216/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/391216/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming-imx@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-imx@bilbo.ozlabs.org", "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n\t[IPv6:2001:1868:205::9])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 58E9414018C\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tFri, 19 Sep 2014 20:40:27 +1000 (EST)", "from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux))\n\tid 1XUvZq-0007B5-9Q; Fri, 19 Sep 2014 10:38:10 +0000", "from mail-bn1bon0119.outbound.protection.outlook.com\n\t([157.56.111.119] helo=na01-bn1-obe.outbound.protection.outlook.com)\n\tby bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat\n\tLinux)) id 1XUvZl-00073F-RZ\n\tfor linux-arm-kernel@lists.infradead.org;\n\tFri, 19 Sep 2014 10:38:07 +0000", "from CH1PR03CA003.namprd03.prod.outlook.com (10.255.156.148) by\n\tBY2PR0301MB0614.namprd03.prod.outlook.com (25.160.125.24) with\n\tMicrosoft SMTP\n\tServer (TLS) id 15.0.1034.13; Fri, 19 Sep 2014 10:37:41 +0000", "from BN1BFFO11FD034.protection.gbl (10.255.156.132) by\n\tCH1PR03CA003.outlook.office365.com (10.255.156.148) with Microsoft\n\tSMTP\n\tServer (TLS) id 15.0.1034.13 via Frontend Transport; Fri, 19 Sep 2014\n\t10:37:41 +0000", "from az84smr01.freescale.net (192.88.158.2) by\n\tBN1BFFO11FD034.mail.protection.outlook.com (10.58.144.97) with\n\tMicrosoft SMTP\n\tServer (TLS) id 15.0.1029.15 via Frontend Transport; Fri, 19 Sep 2014\n\t10:37:40 +0000", "from titan.ap.freescale.net ([10.192.208.233])\n\tby az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id\n\ts8JAbYWK028477; Fri, 19 Sep 2014 03:37:35 -0700" ], "From": "Xiubo Li <Li.Xiubo@freescale.com>", "To": "<shawn.guo@freescale.com>, <kernel@pengutronix.de>,\n\t<linux-arm-kernel@lists.infradead.org>, <linux@arm.linux.org.uk>,\n\t<robh+dt@kernel.org>, <pawel.moll@arm.com>, <mark.rutland@arm.com>,\n\t<ijc+devicetree@hellion.org.uk>, <galak@codeaurora.org>", "Subject": "[PATCH] ARM: ls1021a: add gating clocks to IP blocks.", "Date": "Fri, 19 Sep 2014 18:37:27 +0800", "Message-ID": "<1411123047-7544-1-git-send-email-Li.Xiubo@freescale.com>", "X-Mailer": "git-send-email 2.1.0.27.g96db324", "X-EOPAttributedMessage": "0", "X-Forefront-Antispam-Report": "CIP:192.88.158.2; CTRY:US; IPV:CAL; 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domain of freescale.com does not\n\tdesignate 192.88.158.2 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.158.2; helo=az84smr01.freescale.net;", "Authentication-Results": "spf=fail (sender IP is 192.88.158.2)\n\tsmtp.mailfrom=Li.Xiubo@freescale.com; ", "X-OriginatorOrg": "freescale.com", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20140919_033806_266605_4A4A157C ", "X-CRM114-Status": "GOOD ( 12.37 )", "X-Spam-Score": "-0.3 (/)", "X-Spam-Report": "SpamAssassin version 3.4.0 on bombadil.infradead.org summary:\n\tContent analysis details: (-0.3 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [157.56.111.119 listed in list.dnswl.org]\n\t-0.3 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2)\n\t[157.56.111.119 listed in wl.mailspike.net]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 SPF_HELO_PASS SPF: HELO matches SPF record", "Cc": "Xiubo Li <Li.Xiubo@freescale.com>, linux-kernel@vger.kernel.org", "X-BeenThere": "linux-arm-kernel@lists.infradead.org", "X-Mailman-Version": "2.1.18-1", "Precedence": "list", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-arm-kernel/>", "List-Post": "<mailto:linux-arm-kernel@lists.infradead.org>", "List-Help": "<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>", "Errors-To": "linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org", "List-Id": "linux-imx-kernel.lists.patchwork.ozlabs.org" }, "content": "A given application may not use all the peripherals on the device.\nIn this case, it may be desirable to disable unused peripherals.\nDCFG provides a mechanism for gating clocks to IP blocks that are\nnot used when running an application.\n\nSigned-off-by: Xiubo Li <Li.Xiubo@freescale.com>\n---\n arch/arm/mach-imx/Makefile | 2 +\n arch/arm/mach-imx/clk-ls1021a.c | 124 ++++++++++++++++++++++++++++++\n arch/arm/mach-imx/clk.h | 21 +++++\n include/dt-bindings/clock/ls1021a-clock.h | 54 +++++++++++++\n 4 files changed, 201 insertions(+)\n create mode 100644 arch/arm/mach-imx/clk-ls1021a.c\n create mode 100644 include/dt-bindings/clock/ls1021a-clock.h", "diff": "diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile\nindex 6e4fcd8..f6a1544 100644\n--- a/arch/arm/mach-imx/Makefile\n+++ b/arch/arm/mach-imx/Makefile\n@@ -110,4 +110,6 @@ obj-$(CONFIG_SOC_IMX53) += mach-imx53.o\n \n obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o\n \n+obj-$(CONFIG_SOC_LS1021A) += clk-ls1021a.o\n+\n obj-y += devices/\ndiff --git a/arch/arm/mach-imx/clk-ls1021a.c b/arch/arm/mach-imx/clk-ls1021a.c\nnew file mode 100644\nindex 0000000..680b616\n--- /dev/null\n+++ b/arch/arm/mach-imx/clk-ls1021a.c\n@@ -0,0 +1,124 @@\n+/*\n+ * Copyright 2014 Freescale Semiconductor, Inc.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ *\n+ */\n+\n+#include <linux/clk.h>\n+#include <linux/mfd/syscon.h>\n+#include <linux/of_address.h>\n+#include <dt-bindings/clock/ls1021a-clock.h>\n+\n+#include \"clk.h\"\n+\n+static struct clk *clk[LS1021A_CLK_END];\n+static struct clk_onecell_data clk_data;\n+\n+static void __init ls1021a_clocks_init(struct device_node *np)\n+{\n+\tvoid __iomem *dcfg_base;\n+\n+#define DCFG_CCSR_DEVDISR1\t(dcfg_base + 0x70)\n+#define DCFG_CCSR_DEVDISR2\t(dcfg_base + 0x74)\n+#define DCFG_CCSR_DEVDISR3\t(dcfg_base + 0x78)\n+#define DCFG_CCSR_DEVDISR4\t(dcfg_base + 0x7c)\n+#define DCFG_CCSR_DEVDISR5\t(dcfg_base + 0x80)\n+\n+\tdcfg_base = of_iomap(np, 0);\n+\n+\tBUG_ON(!dcfg_base);\n+\n+\tclk[LS1021A_CLK_PBL_EN] = ls1021a_clk_gate(\"pbl_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR1, 0, true);\n+\tclk[LS1021A_CLK_ESDHC_EN] = ls1021a_clk_gate(\"esdhc_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR1, 2, true);\n+\tclk[LS1021A_CLK_DMA1_EN] = ls1021a_clk_gate(\"dma1_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR1, 8, true);\n+\tclk[LS1021A_CLK_DMA2_EN] = ls1021a_clk_gate(\"dma2_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR1, 9, true);\n+\tclk[LS1021A_CLK_USB3_PHY_EN] = ls1021a_clk_gate(\"usb3_phy_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR1, 12, true);\n+\tclk[LS1021A_CLK_USB2_EN] = ls1021a_clk_gate(\"usb2_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR1, 13, true);\n+\tclk[LS1021A_CLK_SATA_EN] = ls1021a_clk_gate(\"sata_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR1, 16, true);\n+\tclk[LS1021A_CLK_USB3_EN] = ls1021a_clk_gate(\"usb3_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR1, 17, true);\n+\tclk[LS1021A_CLK_SEC_EN] = ls1021a_clk_gate(\"sec_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR1, 22, true);\n+\tclk[LS1021A_CLK_2D_ACE_EN] = ls1021a_clk_gate(\"2d_ace_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR1, 30, true);\n+\tclk[LS1021A_CLK_QE_EN] = ls1021a_clk_gate(\"qe_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR1, 31, true);\n+\n+\tclk[LS1021A_CLK_ETSEC1_EN] = ls1021a_clk_gate(\"etsec1_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR2, 0, true);\n+\tclk[LS1021A_CLK_ETSEC2_EN] = ls1021a_clk_gate(\"etsec2_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR2, 1, true);\n+\tclk[LS1021A_CLK_ETSEC3_EN] = ls1021a_clk_gate(\"etsec3_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR2, 2, true);\n+\n+\tclk[LS1021A_CLK_PEX1_EN] = ls1021a_clk_gate(\"pex1_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR3, 0, true);\n+\tclk[LS1021A_CLK_PEX2_EN] = ls1021a_clk_gate(\"pex2_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR3, 1, true);\n+\n+\tclk[LS1021A_CLK_DUART1_EN] = ls1021a_clk_gate(\"duart1_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR4, 2, true);\n+\tclk[LS1021A_CLK_DUART2_EN] = ls1021a_clk_gate(\"duart2_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR4, 3, true);\n+\tclk[LS1021A_CLK_QSPI_EN] = ls1021a_clk_gate(\"qspi_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR4, 4, true);\n+\n+\tclk[LS1021A_CLK_DDR_EN] = ls1021a_clk_gate(\"ddr_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5, 0, true);\n+\tclk[LS1021A_CLK_OCRAM1_EN] = ls1021a_clk_gate(\"ocram1_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5, 4, true);\n+\tclk[LS1021A_CLK_IFC_EN] = ls1021a_clk_gate(\"ifc_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5, 8, true);\n+\tclk[LS1021A_CLK_GPIO_EN] = ls1021a_clk_gate(\"gpio_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5, 9, true);\n+\tclk[LS1021A_CLK_DBG_EN] = ls1021a_clk_gate(\"dbg_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5, 10, true);\n+\tclk[LS1021A_CLK_FLEXCAN1_EN] = ls1021a_clk_gate(\"flexcan1_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5, 12, true);\n+\tclk[LS1021A_CLK_FLEXCAN234_EN] = ls1021a_clk_gate(\"flexcan234_en\",\n+\t\t\t\t\t\"dummy\", DCFG_CCSR_DEVDISR5, 13, true);\n+\t/* For flextiemr 2/3/4/5/6/7/8 */\n+\tclk[LS1021A_CLK_FLEXTIMER_EN] = ls1021a_clk_gate(\"flextimer_en\",\n+\t\t\t\t\t\"dummy\", DCFG_CCSR_DEVDISR5, 14, true);\n+\tclk[LS1021A_CLK_SECMON_EN] = ls1021a_clk_gate(\"secmon_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5, 17, true);\n+\tclk[LS1021A_CLK_WDOG12_EN] = ls1021a_clk_gate(\"wdog12_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5, 21, true);\n+\tclk[LS1021A_CLK_I2C23_EN] = ls1021a_clk_gate(\"i2c23_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5, 22, true);\n+\t/* For SAI 1/2/3/4 */\n+\tclk[LS1021A_CLK_SAI_EN] = ls1021a_clk_gate(\"sai_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5, 23, true);\n+\t/* For lpuart 2/3/4/5/6 */\n+\tclk[LS1021A_CLK_LPUART_EN] = ls1021a_clk_gate(\"lpuart_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5, 24, true);\n+\tclk[LS1021A_CLK_DSPI12_EN] = ls1021a_clk_gate(\"dspi12_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5, 25, true);\n+\tclk[LS1021A_CLK_ASRC_EN] = ls1021a_clk_gate(\"asrc_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5, 26, true);\n+\tclk[LS1021A_CLK_SPDIF_EN] = ls1021a_clk_gate(\"spdif_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5, 27, true);\n+\tclk[LS1021A_CLK_I2C1_EN] = ls1021a_clk_gate(\"i2c1_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5, 29, true);\n+\tclk[LS1021A_CLK_LPUART1_EN] = ls1021a_clk_gate(\"lpuart1_en\", \"dummy\",\n+\t\t\t\t\t\tDCFG_CCSR_DEVDISR5, 30, true);\n+\tclk[LS1021A_CLK_FLEXTIMER1_EN] = ls1021a_clk_gate(\"flextimer1_en\",\n+\t\t\t\t\t\"dummy\", DCFG_CCSR_DEVDISR5, 31, true);\n+\n+\t/* Add the clocks to provider list */\n+\tclk_data.clks = clk;\n+\tclk_data.clk_num = ARRAY_SIZE(clk);\n+\tof_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);\n+}\n+CLK_OF_DECLARE(ls1021a, \"fsl,ls1021a-gate\", ls1021a_clocks_init);\ndiff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h\nindex 4cdf8b6..dd9e369 100644\n--- a/arch/arm/mach-imx/clk.h\n+++ b/arch/arm/mach-imx/clk.h\n@@ -107,6 +107,27 @@ static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,\n \t\t\tshift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);\n }\n \n+/* The DCFG registers are in big endian mode on LS1021A SoC */\n+static inline u8 ls1021a_clk_calculate_shift(u8 shift)\n+{\n+\tint m, n;\n+\n+\tm = shift / 8;\n+\tn = shift % 8;\n+\n+\treturn (3 - m) * 8 + n;\n+}\n+\n+static inline struct clk *ls1021a_clk_gate(const char *name, const char *parent,\n+\t\tvoid __iomem *reg, u8 shift, bool big_endian)\n+{\n+\tif (big_endian)\n+\t\tshift = ls1021a_clk_calculate_shift(shift);\n+\n+\treturn clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,\n+\t\t\tshift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);\n+}\n+\n static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,\n \t\tu8 shift, u8 width, const char **parents, int num_parents)\n {\ndiff --git a/include/dt-bindings/clock/ls1021a-clock.h b/include/dt-bindings/clock/ls1021a-clock.h\nnew file mode 100644\nindex 0000000..f259882\n--- /dev/null\n+++ b/include/dt-bindings/clock/ls1021a-clock.h\n@@ -0,0 +1,54 @@\n+/*\n+ * Copyright 2014 Freescale Semiconductor, Inc.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation; either version 2 of the License, or\n+ * (at your option) any later version.\n+ */\n+\n+#ifndef __DT_BINDINGS_CLOCK_LS1021A_H\n+#define __DT_BINDINGS_CLOCK_LS1021A_H\n+\n+#define LS1021A_CLK_DUMMY\t0\n+#define LS1021A_CLK_PBL_EN\t1\n+#define LS1021A_CLK_ESDHC_EN\t2\n+#define LS1021A_CLK_DMA1_EN\t3\n+#define LS1021A_CLK_DMA2_EN\t4\n+#define LS1021A_CLK_USB3_PHY_EN\t5\n+#define LS1021A_CLK_USB2_EN\t6\n+#define LS1021A_CLK_SATA_EN\t7\n+#define LS1021A_CLK_USB3_EN\t8\n+#define LS1021A_CLK_SEC_EN\t9\n+#define LS1021A_CLK_2D_ACE_EN\t10\n+#define LS1021A_CLK_QE_EN\t11\n+#define LS1021A_CLK_ETSEC1_EN\t12\n+#define LS1021A_CLK_ETSEC2_EN\t13\n+#define LS1021A_CLK_ETSEC3_EN\t14\n+#define LS1021A_CLK_PEX1_EN\t15\n+#define LS1021A_CLK_PEX2_EN\t16\n+#define LS1021A_CLK_DUART1_EN\t17\n+#define LS1021A_CLK_DUART2_EN\t18\n+#define LS1021A_CLK_QSPI_EN\t19\n+#define LS1021A_CLK_DDR_EN\t20\n+#define LS1021A_CLK_OCRAM1_EN\t21\n+#define LS1021A_CLK_IFC_EN\t22\n+#define LS1021A_CLK_GPIO_EN\t23\n+#define LS1021A_CLK_DBG_EN\t24\n+#define LS1021A_CLK_FLEXCAN1_EN\t25\n+#define LS1021A_CLK_FLEXCAN234_EN\t26\n+#define LS1021A_CLK_FLEXTIMER_EN\t27\n+#define LS1021A_CLK_SECMON_EN\t28\n+#define LS1021A_CLK_WDOG12_EN\t28\n+#define LS1021A_CLK_I2C23_EN\t30\n+#define LS1021A_CLK_SAI_EN\t31\n+#define LS1021A_CLK_LPUART_EN\t32\n+#define LS1021A_CLK_DSPI12_EN\t33\n+#define LS1021A_CLK_ASRC_EN\t34\n+#define LS1021A_CLK_SPDIF_EN\t35\n+#define LS1021A_CLK_I2C1_EN\t36\n+#define LS1021A_CLK_LPUART1_EN\t37\n+#define LS1021A_CLK_FLEXTIMER1_EN\t38\n+#define LS1021A_CLK_END\t\t39\n+\n+#endif /* __DT_BINDINGS_CLOCK_LS1021A_H */\n", "prefixes": [] }